From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ot1-f66.google.com (mail-ot1-f66.google.com [209.85.210.66]) by mx.groups.io with SMTP id smtpd.web11.15495.1583345576444419604 for ; Wed, 04 Mar 2020 10:12:56 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=yFYvTPJm; spf=pass (domain: linaro.org, ip: 209.85.210.66, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-ot1-f66.google.com with SMTP id x97so2962918ota.6 for ; Wed, 04 Mar 2020 10:12:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oKr3W7QD6klf/e+myKE+5AIC5dd4q8EphN7wMeoqi5o=; b=yFYvTPJm6he56NQSE0mcriqH2dYCIczTnrOkZGjtetU65zHH9ymRyIHgcNh3Q2TgUk AGk24kDj3zEbiEngGlrPKVEMC4rx1QWXQ0f0wF43/rJLq3OoQAcTUXACpbK/CadeN5Jr nv80DGZ5vNCUPh0zRVx5uHsDcgdq958W1kd5oGsGSKV6ooPipcCSS13QykcEkIV41BET bfhaQQpCqZjCLlQ8vb/M95/XWTVlGd2D1IyVPL9n0PutqjQt3UmpdVFOqSHVzTQjKJ9r 2O6/XafK+LvnFZCLEqkGeeiDPN7ITGYggGRVLDNyCxB7FNPhHf9nuj5VJWaPT0MCopEd yJMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oKr3W7QD6klf/e+myKE+5AIC5dd4q8EphN7wMeoqi5o=; b=GcKtRb2w4rSwvITUnSuJMiPT9CYENBM+liG3lhyZOhyrhNJPJgeC/D3STnrXiDrDny U6/xBSt3FKjkCZCbYH1TqR7zKd6doF2Tag/5bj7wWf03wt//7izXJZu638P0a1HI92yA U3hBrGr2tmFDCE+bFxT/Y9InKUnprD1w/U/NV15plvR/GPmg24aj7ZDlopnD8aZZHHve do0/VWo3tq1jJeZbn/4YJAIh/a4Dd/M8sg/kMuUNrSG/qO5lKQWrPykeZEx1KVaDsNn9 m7MsVYYpm+2+G8/ybMXZG8EzUqaYNRhZoQj1DeuDpoMhO09jSvfSmD2I9jdZPfbE6Cgr NQ3g== X-Gm-Message-State: ANhLgQ20tiAdTUzL80s+E9mm8KBuw0nxUmsHBYGOE4ie0zmmjrufDVeA lDfrh6oZMtYEUyGV7YZo3ll9xucoPoPKFA== X-Google-Smtp-Source: ADFU+vs02CVNvn6t+VbjOI4dS7LUAqsKMHoaYyFGkJqDHP/hrVLQ22GhezXO3Ti0JYvMcItGyjEIhQ== X-Received: by 2002:a05:6830:19ec:: with SMTP id t12mr1821677ott.161.1583345575145; Wed, 04 Mar 2020 10:12:55 -0800 (PST) Return-Path: Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:12:54 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH v2 1/9] ArmPlatformPkg/PrePi: replace set/way cache ops with by-VA ones Date: Wed, 4 Mar 2020 19:12:38 +0100 Message-Id: <20200304181246.23513-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> Cache maintenance operations by set/way are only intended to be used in the context of on/offlining a core, while it has been taken out of the coherency domain. Any use intended to ensure that the contents of the cache have made it to main memory is unreliable, since cacheline migration and non-architected system caches may cause these contents to linger elsewhere, without being visible in main memory once the MMU and caches are disabled. In KVM on Linux, there are horrid hacks in place to ensure that such set/way operations are trapped, and replaced with a single by-VA clean/invalidate of the entire guest VA space once the MMU state changes, which can be costly, and is unnecessary if we manage the caches a bit more carefully, and perform maintenance by virtual address only. So let's get rid of the call to ArmInvalidateDataCache () in the PrePeiCore startup code, and instead, invalidate the UEFI memory region by virtual address, which is the only memory region we will be touching with the caches and MMU both disabled and enabled. (This will lead to data corruption if data written with the MMU off is shadowed by clean, stale cachelines that stick around when the MMU is enabled again.) Signed-off-by: Ard Biesheuvel Acked-by: Laszlo Ersek Tested-By: Pete Batard --- ArmPlatformPkg/PrePi/PeiMPCore.inf | 1 + ArmPlatformPkg/PrePi/PeiUniCore.inf | 1 + ArmPlatformPkg/PrePi/PrePi.c | 8 +++++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiMPCore.inf index 9c5da0d42a7b..053f9fd9e616 100644 --- a/ArmPlatformPkg/PrePi/PeiMPCore.inf +++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf @@ -37,6 +37,7 @@ [Packages] [LibraryClasses] BaseLib + CacheMaintenanceLib DebugLib DebugAgentLib ArmLib diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/PeiUniCore.inf index ee9b05b25337..78d218ae09ca 100644 --- a/ArmPlatformPkg/PrePi/PeiUniCore.inf +++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf @@ -37,6 +37,7 @@ [Packages] [LibraryClasses] BaseLib + CacheMaintenanceLib DebugLib DebugAgentLib ArmLib diff --git a/ArmPlatformPkg/PrePi/PrePi.c b/ArmPlatformPkg/PrePi/PrePi.c index 2bb144958139..254fb331733e 100644 --- a/ArmPlatformPkg/PrePi/PrePi.c +++ b/ArmPlatformPkg/PrePi/PrePi.c @@ -8,6 +8,7 @@ #include +#include #include #include #include @@ -178,8 +179,6 @@ CEntryPoint ( // Data Cache enabled on Primary core when MMU is enabled. ArmDisableDataCache (); - // Invalidate Data cache - ArmInvalidateDataCache (); // Invalidate instruction cache ArmInvalidateInstructionCache (); // Enable Instruction Caches on all cores. @@ -200,6 +199,10 @@ CEntryPoint ( // If not primary Jump to Secondary Main if (ArmPlatformIsPrimaryCore (MpId)) { + + InvalidateDataCacheRange ((VOID *)UefiMemoryBase, + FixedPcdGet32(PcdSystemMemoryUefiRegionSize)); + // Goto primary Main. PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp); } else { @@ -209,4 +212,3 @@ CEntryPoint ( // DXE Core should always load and never return ASSERT (FALSE); } - -- 2.17.1