From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f196.google.com (mail-oi1-f196.google.com [209.85.167.196]) by mx.groups.io with SMTP id smtpd.web11.15498.1583345584796986499 for ; Wed, 04 Mar 2020 10:13:04 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=HgVIzfdN; spf=pass (domain: linaro.org, ip: 209.85.167.196, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-oi1-f196.google.com with SMTP id c1so3082300oiy.2 for ; Wed, 04 Mar 2020 10:13:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=76Ip4wsNqEsXmDAe/sMKuaqziD2hQ2DrzQ895hO8qB4=; b=HgVIzfdNsonGYMQAcGYLvs5/e9CJl1ujtorKJQOtH+k876hQQRlzERKHzuc/+24kpa lG4Lho56wgdICT0/kq2y6+332fXVf3DvNEJumej4ZjJJqTuZ/eYqlp1Bv9eNrr4H1oE7 sqGVYBpueFtmu9hOeP4oVkEUOUhLj9+Tn18glHjWM5Jgn7dDXtGOmnLvfRjL5LoypIHu VT0v2gWZMzDr3FHKUEmzwMhNHlJfIGsK4X4eC1KR/Ep30SO80XTIRF+gueh8eCjR3y8N GFmdYtdxahOpWnsAZZPPdaSEOF8q9gYViCDFi3BPo+9RzRPSoL/N/uXXVCpOcDLcku/D 031w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=76Ip4wsNqEsXmDAe/sMKuaqziD2hQ2DrzQ895hO8qB4=; b=twzTxVfUD1Saet714xSjNtu/sHCn2ACC+jBLZcArRcgGv/qzcAL6wWrqVQVhjIA5N8 /hNSS9YWO47nrTn013KTEUb303fU0HBm3hRWE8JBLnT/i9VJShbMGJk5O43xdmQG8ZKU x6oA0/n1QfMy3G/MLmQxGA7zybrQIxjxyT24iEdxMzTHmm9D6t/TQu2iyI/l77baTsmw 3agt2dLNKMuJajK7tF7IxQz7fVg3YBjoM+eurH4GfFS7WaCu+9kFs5abHRNjKOy1Sp0K 4RZWfS79DwjCmVPDqBammbBX+1lGHhnTa3Zi+i8kaPHAiwDcIIlbJfZB+UuE91h2fu4z J2Pw== X-Gm-Message-State: ANhLgQ2hrvH6cUR7eEDCyqhywV7hdd+1RGcDXQ5EcOCOeSi2QYnKGQMt 9hPBX5qTqJXHC8m8+fktEYBjz79noMy23w== X-Google-Smtp-Source: ADFU+vuzWg3qT3SO5U6SxH9olxwm3I6BNHTVxOQvnydOvRd15ffNHNGUAhe3vszeP2zk6T8+CZj9Jg== X-Received: by 2002:aca:af49:: with SMTP id y70mr2729712oie.92.1583345583696; Wed, 04 Mar 2020 10:13:03 -0800 (PST) Return-Path: Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:13:02 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH v2 5/9] ArmPkg/ArmMmuLib AARCH64: cache-invalidate initial page table entries Date: Wed, 4 Mar 2020 19:12:42 +0100 Message-Id: <20200304181246.23513-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> In the AARCH64 version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if set/way operations were the appropriate method to achieve this, doing an invalidate-all first and then populating the page table entries creates a window where page table entries could be loaded speculatively into the caches before we modify them, and shadow the new values that we write there. So let's get rid of the blanket clean/invalidate operations, and instead, update ArmUpdateTranslationTableEntry () to invalidate each page table entry *after* it is written if the MMU is still disabled at this point. On ARMv8, it is guaranteed that memory accesses done by the page table walker are cache coherent, and so we can ignore the case where the MMU is on. Since the MMU and D-cache are already off when we reach this point, we can drop the MMU and D-cache disables as well. Maintenance of the I-cache is unnecessary, since we are not modifying any code, and the installed mapping is guaranteed to be 1:1. This means we can also leave it enabled while the page table population code is running. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 9 ++++++++- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 9 --------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S index 1adf960377a2..f744cd6738b9 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -13,6 +13,8 @@ .set DAIF_RD_FIQ_BIT, (1 << 6) .set DAIF_RD_IRQ_BIT, (1 << 7) +.set SCTLR_ELx_M_BIT_POS, (0) + ASM_FUNC(ArmReadMidr) mrs x0, midr_el1 // Read from Main ID Register (MIDR) ret @@ -122,11 +124,16 @@ ASM_FUNC(ArmUpdateTranslationTableEntry) lsr x1, x1, #12 EL1_OR_EL2_OR_EL3(x0) 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1 + mrs x2, sctlr_el1 b 4f 2: tlbi vae2, x1 // TLB Invalidate VA , EL2 + mrs x2, sctlr_el2 b 4f 3: tlbi vae3, x1 // TLB Invalidate VA , EL3 -4: dsb nsh + mrs x2, sctlr_el3 +4: tbnz x2, SCTLR_ELx_M_BIT_POS, 5f + dc ivac, x0 // invalidate in Dcache if MMU is still off +5: dsb nsh isb ret diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index e8f5c69e3136..204e33c75f95 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -699,15 +699,6 @@ ArmConfigureMmu ( ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); - // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs - ArmDisableMmu (); - ArmDisableDataCache (); - ArmDisableInstructionCache (); - - // Make sure nothing sneaked into the cache - ArmCleanInvalidateDataCache (); - ArmInvalidateInstructionCache (); - TranslationTableAttribute = TT_ATTR_INDX_INVALID; while (MemoryTable->Length != 0) { -- 2.17.1