From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web12.10245.1583402440379152661 for ; Thu, 05 Mar 2020 02:00:40 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=fxYPyD7s; spf=pass (domain: linaro.org, ip: 209.85.128.67, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wm1-f67.google.com with SMTP id i9so5493271wml.4 for ; Thu, 05 Mar 2020 02:00:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rovMi5RCWP0BpsAR1e3/W9G6TuZFHjI/tmrfQQkgbbs=; b=fxYPyD7s6I1YlHBYrrYBa9jXt7nqsi44i3C8FTWGS3C+EP4qT9wKBS0pXUNY6mPuUU Q9XYwLK+PZcX+Ca/Myl+YcU1vb9nUsOKpTCdtLrhUAnVsjrPMialoLd573PPNyMiVsT7 6quaoWJD421HxS6Sy2KRWULxPjKfKIgpg13oTiMCpgTgJ0bU598jy3wdtPjyq07RiJ6a 3YFvOuVm+/1BveaVmO2d9DDU0jI+TfUw8LtyfON1qQkd4bUEhNJZjJVRhDZe5gEG1/rj qCZnYD9Ex0l0ZYAucBL8+3U21ET6IRDYZVwxFB0l0DLNwPiGb3AlLGI/Hw+xQ4U1pBtp lB6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rovMi5RCWP0BpsAR1e3/W9G6TuZFHjI/tmrfQQkgbbs=; b=tHSRsQE93MXWpNrx/05S0sCr7jjpEt3uE2h6TAKIX27TfFyGHWadNTUyWGDgHLa0nF 7Qa/8+w32VOjboKnzMgB0LKrDHTXXBElEWkMS18HOCN/nB5cI5nHF3xIX52ZkiaqC4qR /VnJLWbEW5VoS+Tfmg2b5keQN/1E+2Tb2lAw0nUDOhZxddnyuXb617PABtwGKNN+r3WF gRa+HSDXO8piaDJHKkc5i4rFnOdfR+X49lOk5JOtd2C/Kx9EhRCtTe24JWo2Bth2dpzG XL5BB0yORgQh1qJU+ncTJ89qWfIN72xbJg/FIGx6uxxlIVOWLPvH60B+s8KbPxAByKWK 1InQ== X-Gm-Message-State: ANhLgQ1J4X8wTDhBPK3yHzIcuB2Or9C04oMyE5L60YVxycnCcFgGAKEU oUif/ImuYIXuAj4IjMzSzL6NX0cmMRudNg== X-Google-Smtp-Source: ADFU+vvcF1pjbLTXRrdzG9dgZ8hg5kmprhirZLjHC1RUR5uLoDObzaj0A7pbsy1FwTj3pP/ZUpAkQA== X-Received: by 2002:a1c:e206:: with SMTP id z6mr8193615wmg.141.1583402437437; Thu, 05 Mar 2020 02:00:37 -0800 (PST) Return-Path: Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id g206sm8569051wme.46.2020.03.05.02.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 02:00:36 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH 2/2] ArmPkg/ArmMmuLib ARM: invalidate page tables as they are allocated Date: Thu, 5 Mar 2020 11:00:30 +0100 Message-Id: <20200305100030.20048-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200305100030.20048-1-ard.biesheuvel@linaro.org> References: <20200305100030.20048-1-ard.biesheuvel@linaro.org> Instead of performing two cache invalidations for each section entry that gets updated, perform the first invalidation, which is intended to clean the page tables from caches on systems where cache hits are permitted with the MMU and caches off. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 33 +++++++++++--------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index 0800ef560d89..11a1e704beab 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -147,6 +147,13 @@ PopulateLevel2PageTable ( BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry); + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables + // + InvalidateDataCacheRange ((VOID *)TranslationTable, + TRANSLATION_TABLE_PAGE_SIZE); + // Populate the new Level2 Page Table for the section PageEntry = (UINT32*)TranslationTable; for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { @@ -166,6 +173,12 @@ PopulateLevel2PageTable ( TranslationTable = (UINTN)AllocateAlignedPages ( EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE), TRANSLATION_TABLE_PAGE_ALIGNMENT); + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables + // + InvalidateDataCacheRange ((VOID *)TranslationTable, + TRANSLATION_TABLE_PAGE_SIZE); ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE); *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | @@ -179,13 +192,6 @@ PopulateLevel2PageTable ( ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT); - // - // Invalidate once to prevent page table updates to hit in the - // caches inadvertently. - // - InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset, - RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)); - for (Index = 0; Index < Pages; Index++) { *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes; PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE; @@ -268,14 +274,6 @@ FillTranslationTable ( SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase); while (RemainLength != 0) { - // - // Ensure that the assignment of the page table entry will not hit - // in the cache. Whether this could occur is IMPLEMENTATION DEFINED - // and thus permitted by the ARMv7 architecture. - // - ArmInvalidateDataCacheEntryByMVA ((UINTN)SectionEntry); - ArmDataSynchronizationBarrier (); - if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 && RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) { // Case: Physical address aligned on the Section Size (1MB) && the length @@ -348,6 +346,11 @@ ArmConfigureMmu ( *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE; } + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables + // + InvalidateDataCacheRange (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); // By default, mark the translation table as belonging to a uncached region -- 2.17.1