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From: "Ard Biesheuvel" <ard.biesheuvel@linaro.org>
To: devel@edk2.groups.io
Cc: leif@nuviainc.com, Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH 1/2] ArmPkg/ArmMmuLib ARM: simplify assignment of TTBR0 system register
Date: Thu,  5 Mar 2020 13:59:06 +0100	[thread overview]
Message-ID: <20200305125907.13680-2-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <20200305125907.13680-1-ard.biesheuvel@linaro.org>

The expression passed into ArmSetTTBR0 () in ArmConfigureMmu() is
sub-optimal at several levels:
- TranslationTable is already aligned, and if it wasn't, doing it
  here wouldn't help
- TTBRAttributes is guaranteed not to have any bits set outside of
  the 0x7f mask, so the mask operation is pointless as well,
- an additional (UINTN) cast for good measure is also not needed.

So simplify the expression.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
index 11a1e704beab..a6f44dbd5f21 100644
--- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
@@ -392,7 +392,7 @@ ArmConfigureMmu (
     }
   }
 
-  ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
+  ArmSetTTBR0 ((VOID *)((UINTN)TranslationTable | TTBRAttributes));
 
   //
   // The TTBCR register value is undefined at reset in the Non-Secure world.
-- 
2.17.1


  reply	other threads:[~2020-03-05 12:59 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-05 12:59 [PATCH 0/2] ArmPkg/ArmMmuLib ARM: some cleanups Ard Biesheuvel
2020-03-05 12:59 ` Ard Biesheuvel [this message]
2020-03-05 12:59 ` [PATCH 2/2] ArmPkg/ArmMmuLib ARM: drop memory type check for page tables Ard Biesheuvel
2020-03-05 16:50 ` [PATCH 0/2] ArmPkg/ArmMmuLib ARM: some cleanups Leif Lindholm

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