From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by mx.groups.io with SMTP id smtpd.web09.11908.1583413159967430933 for ; Thu, 05 Mar 2020 04:59:20 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=JWEpOubq; spf=pass (domain: linaro.org, ip: 209.85.128.68, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wm1-f68.google.com with SMTP id a5so6205337wmb.0 for ; Thu, 05 Mar 2020 04:59:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=57fgu0HeV0Wsvnx1qzRlTPI5YG5h7Pn105IYsRISjtQ=; b=JWEpOubqhdm8maYO5DIWn8PCZhEtMxDRkRAnpa6eNYFridEio7/BDuA7BCYeBg98cJ gRlSJ+CVGMPjrIl2U8byxNu2yFdgHa+Rf4+fCastpwdg019LVIpJJv9EVIW7iji1hSPR 3x/jyhRkBnB25IvBLVBateI9xTqDLpo+EXmPOQd/avWtk0Zu4s8ugP7KtnXh9yNXpSXU 3xUe0T1Qdl1FJ8rZYUURMKD4J9LEXxaWf9k8hu4/3jGpR2P1EGn7CajEap/Ui8Yg2iWl h+yvjr2V3DEAdeFeH0Y5vTAdLBz9QpoN+gupouhp0PbHe6Tynx4fJzVRq6IZIyBPlTlS aDjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=57fgu0HeV0Wsvnx1qzRlTPI5YG5h7Pn105IYsRISjtQ=; b=cq60wTeUqQ9rb1+6qO5WLkuEPxWmmHQUwIFJQ4rathTDs32hYV0ybEmy0jzxdcrap4 7q/0mD/VLLFIHP6lgysRL9aX6vVqSOzfFliwT38yt6qw3Ux8/dyiRDYIp9o0ZKLOqS0Z xyBUVJcR48NNox8K7+4mMmEIcQ1DO1Etmle38cUiNa4a+D3KGK07uoDi6KIdZqCEOh+X 4rwavbfU+33XjVid756oGnKg+R2BB4TtW8Il32B0OZ8QPrWVJrtQ1wtYWbhiZme6BR6/ 6maZFPL/+FFwFhDPySe4HRd1kpnQUtsHf/S1vAcGUVzdBrnF1ygl9Wkg7s5uIV0HvLhv 1gXA== X-Gm-Message-State: ANhLgQ2nJ2vgP92J9n/PiAPE8s6g0PQfUG+jVBCWiMWLkV/cYncSMmiX KQ2IKLgzd5S7nnD8qU97cim1QRLDBmsXkg== X-Google-Smtp-Source: ADFU+vvVbc9+REWlApIscg955oFNcRH8M0pAKN7bodosjbnldrdjF8Mq/2zz2nkZwHel9OTBK2lkgA== X-Received: by 2002:a1c:7ed0:: with SMTP id z199mr10075736wmc.52.1583413158167; Thu, 05 Mar 2020 04:59:18 -0800 (PST) Return-Path: Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id v8sm43019476wrw.2.2020.03.05.04.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 04:59:17 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH 2/2] ArmPkg/ArmMmuLib ARM: drop memory type check for page tables Date: Thu, 5 Mar 2020 13:59:07 +0100 Message-Id: <20200305125907.13680-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200305125907.13680-1-ard.biesheuvel@linaro.org> References: <20200305125907.13680-1-ard.biesheuvel@linaro.org> We already expect normal memory to be mapped writeback cacheable if EDK2 itself is to make use of it, so doing an early sanity check on the memory type of the allocation that the page tables happened to land in isn't very useful. So let's drop it. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index a6f44dbd5f21..15e836e75e8e 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -328,7 +328,6 @@ ArmConfigureMmu ( ) { VOID *TranslationTable; - ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute; UINT32 TTBRAttributes; TranslationTable = AllocateAlignedPages ( @@ -353,28 +352,13 @@ ArmConfigureMmu ( InvalidateDataCacheRange (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); - // By default, mark the translation table as belonging to a uncached region - TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; while (MemoryTable->Length != 0) { - // Find the memory attribute for the Translation Table - if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) { - TranslationTableAttribute = MemoryTable->Attributes; - } - FillTranslationTable (TranslationTable, MemoryTable); MemoryTable++; } - // Translate the Memory Attributes into Translation Table Register Attributes - if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) { - TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC; - } else { - // Page tables must reside in memory mapped as write-back cacheable - ASSERT (0); - return RETURN_UNSUPPORTED; - } - + TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC + : TTBR_WRITE_BACK_ALLOC; if (TTBRAttributes & TTBR_SHAREABLE) { if (PreferNonshareableMemory ()) { TTBRAttributes ^= TTBR_SHAREABLE; -- 2.17.1