From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.groups.io with SMTP id smtpd.web12.10755.1583491237820036288 for ; Fri, 06 Mar 2020 02:40:38 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=LdJG9GjJ; spf=pass (domain: linaro.org, ip: 209.85.221.46, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wr1-f46.google.com with SMTP id v11so1729920wrm.9 for ; Fri, 06 Mar 2020 02:40:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=g53nK0fK30S5twRXaLluh1kEeJlJXGlQMj6OnmVI2MA=; b=LdJG9GjJlTbyAOgpJFeUNRbo3c5Lvoo8v4ivhq0eQQeviXYoM0tFY+loJy9GMBUY1a EDb38DLGdol07uw7aQp+xeiyH9txN64Mhj2dESCWPbvBSlEGei46ZG2fVhHygcEQUQuG LaHTQheAnkXAiLqsXG9XT1ahbp/PU26l1VkjnPYksuajMvBdo6Ofw1HexnUxEOpwx+Ac f/eaSlbyzUJiUm9fhVfiUwSPSde6HOdPYP/Q5+zZ4kD9qDK5/m+7MWHDuy1RdAauT47L Kg/tAlD/GU3S+w28fcyL0/Bbifjye748bLWLZHt1OY+wmuuqXMo3FoEs5uCV76+BPYN5 ih7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=g53nK0fK30S5twRXaLluh1kEeJlJXGlQMj6OnmVI2MA=; b=Z0PDqFJhQbhHWA+6NRZ1efg8LtNwgoO99EZT7ttPt2rACobvdqvg7yfIJoUR1FIuPM 1nzxmISzxR/MnDFE/UtlECe711pb/JnW7HM+Bvcl1WTsDIQvmyZOvAThLYyV2hB9GrVe tbA3roe5UK+w1J4D62flydnJ5nzwfGEddiNnmqn/QwawNw6+WO2WALkUS+aIzjOwNSq4 v2MARhzw6W4H2alG1g1q3ASrHN7EwO2HARQRaHI63l650h8XbBJHQ0xw2in6Wik4V2d9 AnTA0LvX3qWO3QtUPRp/tqxgaYAL+G27GeTjs3tF1Jlb+v5QDGzPLUCCKxO4oKd0vF0j XpBA== X-Gm-Message-State: ANhLgQ0mvJMnORD2sjTOoTP4yx3nKRSrsBEIgm6WXWEfT6B9BYU+XzCU vnfxRAGDBsZ4GuFpK/JLRWEqCq/eXiYt0Q== X-Google-Smtp-Source: ADFU+vupmci7FAmCvXsIzKxtlm5lYoE2DI5isdkukORbu55o8zj0464M1NB3TwDGeqS8yy1y+BPCsg== X-Received: by 2002:a5d:4c52:: with SMTP id n18mr3609398wrt.403.1583491236136; Fri, 06 Mar 2020 02:40:36 -0800 (PST) Return-Path: Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id w8sm14586287wmm.0.2020.03.06.02.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2020 02:40:35 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH v2] ArmPkg/ArmMmuLib AARCH64: invalidate page tables before populating them Date: Fri, 6 Mar 2020 11:40:32 +0100 Message-Id: <20200306104032.30708-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 As it turns out, ARMv8 also permits accesses made with the MMU and caches off to hit in the caches, so to ensure that any modifications we make before enabling the MMU are visible afterwards as well, we should invalidate page tables right after allocation like we do now on ARM, if the MMU is still disabled at that point. Also, make sure that we don't only invalidate block and page entries when updating the individual entries, but give table entries the same treatment. Signed-off-by: Ard Biesheuvel --- v2: - drop redundant MMU enabled check when allocating the root table - add dmb+ivac for individual table entries (the change that was merged already only does this on block/page entries) ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 204e33c75f95..d4d823780a6a 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -129,6 +129,8 @@ ReplaceLiveEntry ( { if (!ArmMmuEnabled ()) { *Entry = Value; + ArmDataMemoryBarrier (); + ArmInvalidateDataCacheEntryByMVA ((UINTN)Entry); } else { ArmReplaceLiveTranslationEntry (Entry, Value, RegionStart); } @@ -282,6 +284,15 @@ GetBlockEntryListFromAddress ( return NULL; } + if (!ArmMmuEnabled ()) { + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, + TT_ENTRY_COUNT * sizeof(UINT64)); + } + // Populate the newly created lower level table SubTableBlockEntry = TranslationTable; for (Index = 0; Index < TT_ENTRY_COUNT; Index++) { @@ -306,10 +317,23 @@ GetBlockEntryListFromAddress ( return NULL; } + if (!ArmMmuEnabled ()) { + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, + TT_ENTRY_COUNT * sizeof(UINT64)); + } ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64)); // Fill the new BlockEntry with the TranslationTable *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY; + + if (!ArmMmuEnabled ()) { + ArmDataMemoryBarrier (); + ArmInvalidateDataCacheEntryByMVA ((UINTN)BlockEntry); + } } } } @@ -697,6 +721,12 @@ ArmConfigureMmu ( *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); } + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, + RootTableEntryCount * sizeof(UINT64)); ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); TranslationTableAttribute = TT_ATTR_INDX_INVALID; -- 2.17.1