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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id g7sm47053738wrm.72.2020.03.06.05.03.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2020 05:03:40 -0800 (PST) Date: Fri, 6 Mar 2020 13:03:39 +0000 From: "Leif Lindholm" To: Ard Biesheuvel Cc: devel@edk2.groups.io Subject: Re: [PATCH v2] ArmPkg/ArmMmuLib AARCH64: invalidate page tables before populating them Message-ID: <20200306130339.GG23627@bivouac.eciton.net> References: <20200306104032.30708-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20200306104032.30708-1-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Mar 06, 2020 at 11:40:32 +0100, Ard Biesheuvel wrote: > As it turns out, ARMv8 also permits accesses made with the MMU and > caches off to hit in the caches, so to ensure that any modifications > we make before enabling the MMU are visible afterwards as well, we Urgh. I thought v8 had changed that behaviour. > should invalidate page tables right after allocation like we do now on > ARM, if the MMU is still disabled at that point. > > Also, make sure that we don't only invalidate block and page entries > when updating the individual entries, but give table entries the same > treatment. > > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > v2: > - drop redundant MMU enabled check when allocating the root table > - add dmb+ivac for individual table entries (the change that was merged > already only does this on block/page entries) > > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 30 ++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index 204e33c75f95..d4d823780a6a 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -129,6 +129,8 @@ ReplaceLiveEntry ( > { > if (!ArmMmuEnabled ()) { > *Entry = Value; > + ArmDataMemoryBarrier (); > + ArmInvalidateDataCacheEntryByMVA ((UINTN)Entry); > } else { > ArmReplaceLiveTranslationEntry (Entry, Value, RegionStart); > } > @@ -282,6 +284,15 @@ GetBlockEntryListFromAddress ( > return NULL; > } > > + if (!ArmMmuEnabled ()) { > + // > + // Make sure we are not inadvertently hitting in the caches > + // when populating the page tables. > + // > + InvalidateDataCacheRange (TranslationTable, > + TT_ENTRY_COUNT * sizeof(UINT64)); > + } > + > // Populate the newly created lower level table > SubTableBlockEntry = TranslationTable; > for (Index = 0; Index < TT_ENTRY_COUNT; Index++) { > @@ -306,10 +317,23 @@ GetBlockEntryListFromAddress ( > return NULL; > } > > + if (!ArmMmuEnabled ()) { > + // > + // Make sure we are not inadvertently hitting in the caches > + // when populating the page tables. > + // > + InvalidateDataCacheRange (TranslationTable, > + TT_ENTRY_COUNT * sizeof(UINT64)); > + } > ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64)); > > // Fill the new BlockEntry with the TranslationTable > *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY; > + > + if (!ArmMmuEnabled ()) { > + ArmDataMemoryBarrier (); > + ArmInvalidateDataCacheEntryByMVA ((UINTN)BlockEntry); > + } > } > } > } > @@ -697,6 +721,12 @@ ArmConfigureMmu ( > *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); > } > > + // > + // Make sure we are not inadvertently hitting in the caches > + // when populating the page tables. > + // > + InvalidateDataCacheRange (TranslationTable, > + RootTableEntryCount * sizeof(UINT64)); > ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); > > TranslationTableAttribute = TT_ATTR_INDX_INVALID; > -- > 2.17.1 >