From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.groups.io with SMTP id smtpd.web10.177.1583520677189875239 for ; Fri, 06 Mar 2020 10:51:17 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=TbjbH+Bv; spf=pass (domain: nuviainc.com, ip: 209.85.128.65, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f65.google.com with SMTP id a132so3610613wme.1 for ; Fri, 06 Mar 2020 10:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=vRT4wtO4+uAQwFowVYOHRQQa840FNfc7NfbDrh5EQoQ=; b=TbjbH+BvvFZpaPRT1LG4ubNgTUYh4lLFqP7YaGoWgJOYBSM8KmMgWoS6MyP1qDceIk 2NwXmAOY6Z32tMfkrNKlifQx9XggALoPu38Cak6LNlBCwW9MsabNIs0hjwwK7yvSedhz Djej3AmeZep1NnWKOV7GODRxgVf/tDBXB90r6mjnRC5bovEc8ZN8df06FrKGienkZ4cR cDcRtKRx0IPDtehrciAuB9O38fDOsj5FW49Ws3Vn/cS2wNsEF5rejS7RprHJwBVevbmT KYup/fDBya/867dgWA2W901g5i6PzRqtOEKOEbkXkTGyXYFqIW8e5+jlfluq/8eieKjj /wCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=vRT4wtO4+uAQwFowVYOHRQQa840FNfc7NfbDrh5EQoQ=; b=VQ9lg0CMky7vlkGuCn8v5UuhoL7POypSJbwr4u6dmVEKA3sf5wh7Mh2RBp0ooRXLjw 5Aj6TtIclKROrc69+Ff8dp9RPIkFe78HbLAVXvG4mnq+4qb3XAxRuelonF9s4oITR+/8 C280z5udpVKPYESaTXUaUqqUu1CYnM0FXVeSEBHp3dqdnjAjRUqD2fL+VJ0PZovclCTh 12ssqR4AyW2foR73X1GzNsoJI/rpNp5I3Mex7WTplyl+0vLa4oIv0NWmzF5Ljf0KZssO gs+qTIFJm1NS3XILTeeWeBwcU/goib2XAJsLMnn5hsdTiioGlQNoH5wQ/8HLdj0gTg+C +xYA== X-Gm-Message-State: ANhLgQ0W5ICKg2wn3Esqqfxq5RIzFl7kFDWkP7GJOHugJDdunGOSisz6 cteG7Z0B/xX506uS/H9i19OOJw== X-Google-Smtp-Source: ADFU+vtA3dQaeW9lZqA1HXlVeV/PHAuxF1NitMs+cpVbDr+z+bBAliCXmfuYHQqFV1oBkpCeRgx1Gg== X-Received: by 2002:a7b:c4c3:: with SMTP id g3mr5187540wmk.131.1583520675823; Fri, 06 Mar 2020 10:51:15 -0800 (PST) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id i14sm2590196wmb.25.2020.03.06.10.51.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2020 10:51:15 -0800 (PST) Date: Fri, 6 Mar 2020 18:51:13 +0000 From: "Leif Lindholm" To: Ard Biesheuvel Cc: devel@edk2.groups.io Subject: Re: [PATCH v3 2/2] ArmPkg/ArmMmuLib AARCH64: invalidate page tables before populating them Message-ID: <20200306185113.GK23627@bivouac.eciton.net> References: <20200306161246.6392-1-ard.biesheuvel@linaro.org> <20200306161246.6392-3-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20200306161246.6392-3-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Mar 06, 2020 at 17:12:46 +0100, Ard Biesheuvel wrote: > As it turns out, ARMv8 also permits accesses made with the MMU and > caches off to hit in the caches, so to ensure that any modifications > we make before enabling the MMU are visible afterwards as well, we > should invalidate page tables right after allocation like we do now on > ARM, if the MMU is still disabled at that point. > > Signed-off-by: Ard Biesheuvel Urgh. Reviewed-by: Leif Lindholm > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index e36594fea3ad..10ca8bac6a3f 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -217,6 +217,14 @@ UpdateRegionMappingRec ( > return EFI_OUT_OF_RESOURCES; > } > > + if (!ArmMmuEnabled ()) { > + // > + // Make sure we are not inadvertently hitting in the caches > + // when populating the page tables. > + // > + InvalidateDataCacheRange (TranslationTable, EFI_PAGE_SIZE); > + } > + > if ((*Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) { > // > // We are splitting an existing block entry, so we have to populate > @@ -581,6 +589,12 @@ ArmConfigureMmu ( > *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); > } > > + // > + // Make sure we are not inadvertently hitting in the caches > + // when populating the page tables. > + // > + InvalidateDataCacheRange (TranslationTable, > + RootTableEntryCount * sizeof(UINT64)); > ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); > > TranslationTableAttribute = TT_ATTR_INDX_INVALID; > -- > 2.17.1 >