From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by mx.groups.io with SMTP id smtpd.web12.10671.1583570340035458881 for ; Sat, 07 Mar 2020 00:39:00 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=Lv/tDRYm; spf=pass (domain: linaro.org, ip: 209.85.221.67, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wr1-f67.google.com with SMTP id y17so5029706wrn.6 for ; Sat, 07 Mar 2020 00:38:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xWJP4gKUoQvU74FP0YdcZjrgPcoZf+QmKfpPwzOoadE=; b=Lv/tDRYmxlup/XHJ+7ERjuolz90VifvVZTAipsv1SCm1P0PHlW5JgC90bpW6nxN2FF Wq7qmSQPbrcu36XxjiLMYMh0iS6eR9gAkUK6qRWjS+ria1AQ9c+AeKEo3V/3+fnINRkA xxa8TKuQ0dLxECtpLbpzx/BPy5lbGxq6yBGStvRgPapikI0tQu4BsW9cS7F/MiFSUj7B EApC0J+I/a3LIuAY91kj6oIn06ZQHsNXgM72RnQ7DjwkMiQYmtZlP3XWGb6qPwKBYXM8 fsNwzFCkKX0lESYfDbiGgdqozWkfmexihcAUDiSjpKX1GLi+Zk/JIbewq0AyasCZhSG1 jkng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xWJP4gKUoQvU74FP0YdcZjrgPcoZf+QmKfpPwzOoadE=; b=I2+PREG7SXP3V5ZUaSQIv7q4fG072Md0dDYMvc7B5T5j4FDTc4rkUy3fvbjAVddaay leZyQ3Qq+12hBS5EjqPke4jyPyPm1GU9VuYrL40tRnG46MpTpOI0i/r1w5otFSX0Tdfa I7m/vPz29wsJW7RjjUe+cPVLo+3Yr4rv6CakOfFvXMe8W7u5aS+mdtlt8fG8/xRrOpZ3 EGY7gYONsGVvkkm0hc+2jJuiXnx2lMOJl8EwHmLlDSP0nWBdxSJoZdrfqaueE4Vk+Z4W FVgcITRKh8h8ba8NTPZUHm0MGRqQWFgc/cQW+vskGKVBtIO23QJsqoUzU0+dsrP4ValH 45Jg== X-Gm-Message-State: ANhLgQ2FUpMW5WzMt98DI8gXaTSw8Ou2OReKubuTrUSOvHr0YKMq1lCe Qtyi66ci/VuVbbTbMHVMu0xKWA9c5tFDOA== X-Google-Smtp-Source: ADFU+vt58F3rW4AGctGx3vnA0vW4I4jStSTvDgXbiOf+yO5xxgZyCPFvnCyAv0yNYXD+a9+LVoJWoA== X-Received: by 2002:adf:f4c9:: with SMTP id h9mr8823746wrp.168.1583570338228; Sat, 07 Mar 2020 00:38:58 -0800 (PST) Return-Path: Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id t14sm20430953wrp.63.2020.03.07.00.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Mar 2020 00:38:57 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH v4 2/2] ArmPkg/ArmMmuLib AARCH64: invalidate page tables before populating them Date: Sat, 7 Mar 2020 09:38:49 +0100 Message-Id: <20200307083849.8940-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200307083849.8940-1-ard.biesheuvel@linaro.org> References: <20200307083849.8940-1-ard.biesheuvel@linaro.org> As it turns out, ARMv8 also permits accesses made with the MMU and caches off to hit in the caches, so to ensure that any modifications we make before enabling the MMU are visible afterwards as well, we should invalidate page tables right after allocation like we do now on ARM, if the MMU is still disabled at that point. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 00a38bc31d0a..221175ca6535 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -204,6 +204,14 @@ UpdateRegionMappingRecursive ( return EFI_OUT_OF_RESOURCES; } + if (!ArmMmuEnabled ()) { + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, EFI_PAGE_SIZE); + } + if ((*Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) { // // We are splitting an existing block entry, so we have to populate @@ -602,6 +610,12 @@ ArmConfigureMmu ( *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); } + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, + RootTableEntryCount * sizeof(UINT64)); ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); TranslationTableAttribute = TT_ATTR_INDX_INVALID; -- 2.17.1