From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web10.11042.1583572217031546124 for ; Sat, 07 Mar 2020 01:10:17 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=JEIMhVAY; spf=pass (domain: linaro.org, ip: 209.85.128.67, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wm1-f67.google.com with SMTP id n8so917441wmc.4 for ; Sat, 07 Mar 2020 01:10:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hdnv5Kj08KcP3jm1+uPmKSDdhjrOFLrZVsMsaGyIbsM=; b=JEIMhVAYWzKpkQVAoIpFN2410OqmF16YvJLZF6QT27HzHP3fH0BV2uydD38akYJRBt wKKOkgxtOxdHHJqp1ggV53i8a/2YdDXmS2/lYBsQ7EhWRh+g3XFBx2V7soUjZFJQmdpt cLe6P1qU48tJv8WS5+h4hF5dGlxPg/jG21PQpKSUDciirXa4TkL2ZZoMXa6MDwjMYMGm ZuTm5BS6wxYWBzxB8a4sRubkdlDhMi360wcu9x+sJoY4cATl3YtFl493LhlVBECe4ZdA KHuDuxcmylFoLSvieThnT5pzWloQNzmIVRotmoF9NWsPnDjsGIuMYXKIL1LD7znlPXtF G7QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hdnv5Kj08KcP3jm1+uPmKSDdhjrOFLrZVsMsaGyIbsM=; b=B8LST4VoT42at9QWNr30e8vehDIKo6VxZ8KFAsHI6aqipaI5cHGhDLvja3mYZPC2DC hD4LM9A/isyX8HbQZl2FrvAoEVT1x4VoCjabxWuL10YeUMEDFif/EP52L5XFmlwO9qLZ v94I0VCAcM6eMzCcnu7WeHTqT3R95MpA4zfxRm7kXyaAR8FCJ+CW7tM/L2rzSNjfxUcJ 7HiBbP1bxSOZIYYFXTFf9S+Ur9hnGUpSS9uC44yDwb4bUQVc3bhuFQk/OcW3NIMDP6Va 1dCO3bZYzhm41tLS8e5chj6cZWHcVXmdPlECS1BkWZ3sWUOx3c+jpu9UUCp0o6tPrMzE rbyg== X-Gm-Message-State: ANhLgQ3p9pi5qU7oAdCcKk4kcf205eyw0Ib+SN0VZ1NFwHrdS+fr36lT bUEF0pGqS9sY/YwbRrVcPf9nOUGN/yT6qA== X-Google-Smtp-Source: ADFU+vs3IPz3d8KHhU64TbjFqhw+wUtjXnU4KIEejTMi5XjKEAQrInPEyYpPbDEcZ9ZudZIF+hFZwg== X-Received: by 2002:a05:600c:2241:: with SMTP id a1mr8810338wmm.59.1583572214996; Sat, 07 Mar 2020 01:10:14 -0800 (PST) Return-Path: Received: from e123331-lin.home ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id i204sm17088429wma.44.2020.03.07.01.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Mar 2020 01:10:14 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH 1/2] ArmPkg/ArmMmuLib AARCH64: drop pointless page table memory type check Date: Sat, 7 Mar 2020 10:10:07 +0100 Message-Id: <20200307091008.14918-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200307091008.14918-1-ard.biesheuvel@linaro.org> References: <20200307091008.14918-1-ard.biesheuvel@linaro.org> This is the AARCH64 counterpart of commit 1f3b1eb3082206e4, to remove a pointless check against the memory type of the allocations that the page tables happened to land in. On ArmV8, we use writeback cacheable exclusively for all memory. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 221175ca6535..f2eec7191328 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -497,7 +497,6 @@ ArmConfigureMmu ( ) { VOID* TranslationTable; - UINT32 TranslationTableAttribute; UINT64 MaxAddress; UINTN T0SZ; UINTN RootTableEntryCount; @@ -618,18 +617,7 @@ ArmConfigureMmu ( RootTableEntryCount * sizeof(UINT64)); ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); - TranslationTableAttribute = TT_ATTR_INDX_INVALID; while (MemoryTable->Length != 0) { - - DEBUG_CODE_BEGIN (); - // Find the memory attribute for the Translation Table - if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase && - (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase + - MemoryTable->Length) { - TranslationTableAttribute = MemoryTable->Attributes; - } - DEBUG_CODE_END (); - Status = FillTranslationTable (TranslationTable, MemoryTable); if (EFI_ERROR (Status)) { goto FREE_TRANSLATION_TABLE; @@ -637,9 +625,6 @@ ArmConfigureMmu ( MemoryTable++; } - ASSERT (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK || - TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK); - ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT -- 2.17.1