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From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com, Bret Barkelew <Bret.Barkelew@microsoft.com>,
	Sean Brogan <sean.brogan@microsoft.com>,
	Leif Lindholm <leif@nuviainc.com>,
	Michael D Kinney <michael.d.kinney@intel.com>,
	Gilbert Chen <gilbert.chen@hpe.com>,
	Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
Subject: [edk2/master PATCH RISC-V CI v2 4/5] .azurepipelines: Add RISC-V architecture on RISC-V EDK2 CI.
Date: Mon,  9 Mar 2020 17:53:17 +0800	[thread overview]
Message-ID: <20200309095318.7331-5-abner.chang@hpe.com> (raw)
In-Reply-To: <20200309095318.7331-1-abner.chang@hpe.com>

BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562

Add RISC-V architecture on RISC-V EDK2 CI.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
 .azurepipelines/Ubuntu-GCC5.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.azurepipelines/Ubuntu-GCC5.yml b/.azurepipelines/Ubuntu-GCC5.yml
index a26a3a2cb2..7cd67c98da 100644
--- a/.azurepipelines/Ubuntu-GCC5.yml
+++ b/.azurepipelines/Ubuntu-GCC5.yml
@@ -2,6 +2,7 @@
 # Azure Pipeline build file for a build using ubuntu and GCC5
 #
 # Copyright (c) Microsoft Corporation.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 trigger:
@@ -14,5 +15,5 @@ jobs:
   parameters:
     tool_chain_tag: 'GCC5'
     vm_image: 'ubuntu-latest'
-    arch_list: "IA32,X64,ARM,AARCH64"
+    arch_list: "IA32,X64,ARM,AARCH64,RISCV64"
 
-- 
2.25.0


  parent reply	other threads:[~2020-03-09 10:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-09  9:53 [edk2/master PATCH RISC-V CI v2 0/5] RISC-V EDK2 CI configuration files Abner Chang
2020-03-09  9:53 ` [edk2/master PATCH RISC-V CI v2 1/5] RiscVPlatformPkg: Add RiscVPlatformPkg yaml file for EDK2 CI Abner Chang
2020-03-20  0:51   ` [edk2-devel] " Michael D Kinney
2020-03-09  9:53 ` [edk2/master PATCH RISC-V CI v2 2/5] RiscVPkg: Add RiscVPkg " Abner Chang
2020-03-20  0:51   ` [edk2-devel] " Michael D Kinney
2020-03-22  3:12     ` Abner Chang
2020-03-09  9:53 ` [edk2/master PATCH RISC-V CI v2 3/5] BaseTools: Enable RISC-V architecture for RISC-V " Abner Chang
2020-03-21  0:32   ` [edk2-devel] " Rebecca Cran
2020-03-09  9:53 ` Abner Chang [this message]
2020-03-09  9:53 ` [edk2/master PATCH RISC-V CI v2 5/5] .pytool: Add RISC-V architecture on " Abner Chang

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