From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web10.10400.1583940741394476044 for ; Wed, 11 Mar 2020 08:32:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=Lf4rqtMK; spf=pass (domain: nuviainc.com, ip: 209.85.128.67, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f67.google.com with SMTP id n8so2578600wmc.4 for ; Wed, 11 Mar 2020 08:32:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dFm6YEK1Zl/P4sN1DNSUKJWKggcTzUX3jzm/byyEFzk=; b=Lf4rqtMKX+oXQS7e3mo0n0AkHYSRUnQCRpUR6b89bpUeC7aIqEfQ497TABiBdmFwrZ yS4r4LJbUIJCeTRULAOdVW2aiFjM0EKdCr9CIPQSsBdEoQ4exQwnDeqjawMWuxN6N1nP gzPCcVdNH8DV/8WgHLY58y5jXl5K+b3qLzvmqghd4aH5oROWbab6ir5MKBxJk5NDmTtU KjslaNmvU0FI9TtlVO98BZOR1/hqbA4PpBEpKZ1Qxm5C1/ET6snUFEPbysNnB7dDqv7C +EgILGAKQU/teWm4shmG75imauELegTHE36lRmU65vFaeNBKKlm/5xxrNTJUg6OMXCYl JXsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dFm6YEK1Zl/P4sN1DNSUKJWKggcTzUX3jzm/byyEFzk=; b=hgT5Hy+r683oym7A1U/b1HdRYRQ9pFtNaBL7JTA5V880KL+7EYRKiJW/qGlWd4VnFG fP7ycd++ZgdVLviRiF43l08MLenvXUac6HdW8CfA0BYfwqhSwFn9MdV4g8pgbZ2nOZ0x c3oMw3Mo+2Z1VFBD0+Yf1OEdD8D1VDbJH/IxlCSgm4LJNbx2VNKWAYBdxMdc2oOwTj6K XzVOIIB17UNlDEAPinjofhRbKiCvWcbwuHbyoZzw5vOzcKttVpeaknJao0Et48kTh8fN +8LnBiPTJcIAeO7mxe3/4up/yiYknLX+F6+yvWVuOeDFYAbdKizyb3t6OkHBzAKivwFa 8IOQ== X-Gm-Message-State: ANhLgQ1xghgKq5evaaN9GNknKJ1v8kM9+B/hM1v+WpdlX752IGEQAxxo wXmxD1LC7cBdNhlF15H52xowdfdzQOmJFqse+KZsZPhDrX3c03vCqdGplxzjXs6nZozIawws1Gc PK7ePbl8aMgVaLL2Z76+4+kmPUx1SvM8piMbPJVW1ezT64awaMFs6lY/1AKSSbEuJuw== X-Google-Smtp-Source: ADFU+vuiJgdyFX7nez3I2GjnHnXW5AHGyro9MviZy7tXXZl3eW/aDKobv4EGgmF2SurczFRS1aoBgA== X-Received: by 2002:a7b:c153:: with SMTP id z19mr4162998wmi.37.1583940739462; Wed, 11 Mar 2020 08:32:19 -0700 (PDT) Return-Path: Received: from vanye.hemma.eciton.net (cpc92302-cmbg19-2-0-cust304.5-4.cable.virginm.net. [82.1.209.49]) by smtp.gmail.com with ESMTPSA id c8sm62439515wru.7.2020.03.11.08.32.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 08:32:18 -0700 (PDT) From: "Leif Lindholm" To: devel@edk2.groups.io Cc: Laszlo Ersek , Ard Biesheuvel Subject: [PATCH 1/1] ArmVirtPkg: fix ASSERT in ArmVirtGicArchLib with virtualization=on Date: Wed, 11 Mar 2020 15:32:17 +0000 Message-Id: <20200311153217.18253-1-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit ArmVirtGicArchLib was originally implemented before virtualization emulation was implemented in QEMU, and the GICv2 model implemented only the physical copy of control registers. Enabling virtualization emulation to QEMU adds also the virtual copy, doubling the RegSize returned by FindCompatibleNodeReg () in ArmVirtGicArchLibConstructor (). This triggered an ASSERT when running QEMU with -M virt,virtualization=on. Address this by testing for both possible valid values of RegSize. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2588 Cc: Laszlo Ersek Cc: Ard Biesheuvel Signed-off-by: Leif Lindholm --- ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c index af6b3af60edf..5448865ad8e8 100644 --- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c +++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c @@ -110,7 +110,12 @@ ArmVirtGicArchLibConstructor ( break; case 2: - ASSERT (RegSize == 32); + // + // When the GICv2 is emulated with virtualization=on, it adds a virtual + // set of control registers. This means the register property can be + // either 32 or 64 bytes in size. + // + ASSERT ((RegSize == 32) || (RegSize == 64)); DistBase = SwapBytes64 (Reg[0]); CpuBase = SwapBytes64 (Reg[2]); -- 2.20.1