From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.1005.1584431548336664528 for ; Tue, 17 Mar 2020 00:52:28 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ashraf.javeed@intel.com) IronPort-SDR: Fnyac1fkUVBfsQeV46pgaaya58KG6nviK+TUsCGM96Ir+2KG5+2NQKSsskf8cPUolen694ym5q KORwlErw0VDw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2020 00:52:27 -0700 IronPort-SDR: oFLwAVtmGEw+vMhFs4sYSAvzzSEJbyhMr0UmoW7356fb5PBlffBy+1iqHsDqFNbD5DwEvpA7Wh vJmou+Z1rS4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,563,1574150400"; d="scan'208";a="236255993" Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 17 Mar 2020 00:52:25 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [PATCH V2] MdePkg-PciExpress40.h: DVSEC definition missing Date: Tue, 17 Mar 2020 13:22:22 +0530 Message-Id: <20200317075222.2960-1-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598 All registers definition of DVSEC are defined as per the PCI Express Base Specification 4.0 chapter 7.9.6. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu V2: fixed the comment section description for DVSEC definitions --- MdePkg/Include/IndustryStandard/PciExpress40.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h index 02c30a7757..0564d72861 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress40.h +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h @@ -77,7 +77,11 @@ typedef struct { UINT32 Reserved; PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1]; } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; +///@} +/// The Designated Vendor Specific Capability definitions +/// Based on section 7.9.6 of PCI Express Base Specification 4.0. +///@{ typedef union { struct { UINT32 DvsecVendorId : 16; //bit 0..15 -- 2.21.0.windows.1