From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.1090.1584432260079650166 for ; Tue, 17 Mar 2020 01:04:20 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: ashraf.javeed@intel.com) IronPort-SDR: iBt/P3RXiE1SL7lIsMRquzp1gx5JlgCNFYObLevfTRCRNHBA+Hyd5FONSzQtFC3oplWhD5zNGd cM3AoUl/kHsg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2020 01:04:18 -0700 IronPort-SDR: Q7woFe1ovYSuArWFWzM3zzGGTukln0t+ZD6PHZgoLkdkcq0HI6jYpIo34fI6dI6qejPZ8Bi/lI swcv/0pimVLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,563,1574150400"; d="scan'208";a="236258139" Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 17 Mar 2020 01:04:16 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: =?UTF-8?B?W1BBVENIIFYyXSDvu79NZGVQa2ctUGNpRXhwcmVzczQwLmg6IERWU0VDIGRlZmluaXRpb24gbWlzc2luZw==?= Date: Tue, 17 Mar 2020 13:34:13 +0530 Message-Id: <20200317080413.4312-1-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598 All registers definition of DVSEC are defined as per the PCI Express Base Specification 4.0 chapter 7.9.6. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu V2: fixed the comment section description for DVSEC definitions --- MdePkg/Include/IndustryStandard/PciExpress40.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h index 9d9b272546..0564d72861 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress40.h +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard. This header file may not define all structures. Please extend as required. Copyright (c) 2018, American Megatrends, Inc. All rights reserved.
+Copyright (c) 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -78,6 +79,33 @@ typedef struct { } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; ///@} +/// The Designated Vendor Specific Capability definitions +/// Based on section 7.9.6 of PCI Express Base Specification 4.0. +///@{ +typedef union { + struct { + UINT32 DvsecVendorId : 16; //bit 0..15 + UINT32 DvsecRevision : 4; //bit 16..19 + UINT32 DvsecLength : 12; //bit 20..31 + }Bits; + UINT32 Uint32; +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1; + +typedef union { + struct { + UINT16 DvsecId : 16; //bit 0..15 + }Bits; + UINT16 Uint16; +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; + UINT8 DesignatedVendorSpecific[1]; +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC; +///@} + #pragma pack() #endif -- 2.21.0.windows.1