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Received: from VI1PR0401MB2496.eurprd04.prod.outlook.com (10.168.65.10) by VI1PR0401MB2382.eurprd04.prod.outlook.com (10.169.130.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2814.21; Thu, 19 Mar 2020 14:36:51 +0000 Received: from VI1PR0401MB2496.eurprd04.prod.outlook.com ([fe80::196a:28a9:bb9:2fae]) by VI1PR0401MB2496.eurprd04.prod.outlook.com ([fe80::196a:28a9:bb9:2fae%9]) with mapi id 15.20.2835.017; Thu, 19 Mar 2020 14:36:50 +0000 From: Pankaj Bansal To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton Subject: [PATCH v2 10/28] Silicon/NXP: remove print information from Soc lib Date: Fri, 20 Mar 2020 20:05:25 +0530 Message-ID: <20200320143543.18615-11-pankaj.bansal@oss.nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200320143543.18615-1-pankaj.bansal@oss.nxp.com> References: <20200320143543.18615-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR02CA0042.apcprd02.prod.outlook.com (2603:1096:3:18::30) To VI1PR0401MB2496.eurprd04.prod.outlook.com (2603:10a6:800:56::10) Return-Path: pankaj.bansal@oss.nxp.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR02CA0042.apcprd02.prod.outlook.com (2603:1096:3:18::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2835.19 via Frontend Transport; Thu, 19 Mar 2020 14:36:48 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 740a83f2-1030-42d3-208d-08d7cc12f5e2 X-MS-TrafficTypeDiagnostic: VI1PR0401MB2382:|VI1PR0401MB2382: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-Forefront-PRVS: 0347410860 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(376002)(396003)(346002)(136003)(366004)(39860400002)(199004)(6666004)(316002)(186003)(16526019)(6506007)(8676002)(81166006)(81156014)(478600001)(86362001)(44832011)(19627235002)(26005)(8936002)(6486002)(5660300002)(52116002)(6512007)(956004)(66946007)(110136005)(66476007)(2616005)(2906002)(66556008)(1076003);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0401MB2382;H:VI1PR0401MB2496.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:0; Received-SPF: None (protection.outlook.com: oss.nxp.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: y/EV/hEO8Rt7xcEZA6vI/K7rJyKbkoHQeUyGzj7aC9t6noqBtwlo++X69wkJhVriGuGivwvQAfwxvpkzBjyz/SE03qC3gjZuWj/7cUzJlutfIH/Oks0G+vlNqwxmTq8Crv4VEA4KZiaSdjj0ARnHOCrUNNVpNLHR+XIWT1fnk4YefuqoYir7NC99f+ZiW4ha42y5/ng3hYhHmqK8amVv1iuupNm+cz0Lwk5HCDrSMoL1HRkihqCNjDQHCf1Fpx5822kAIikwjfrOxa9gouUUU5kVp6pfltTscoSzJZelyEx5KmO6ZNa6sTyICKl6AdsmPRLe6t6mJhDJggLSp/DZbIn7A6GLhc1RyKW2llTXwk9a8zntDREADJYhTe9yp8HoVx5good36fB8MxuK0Ob4fuZ7EZuslErAB6ph7QXqX0+Twa8jt/7GXcKR0m+Eo3b8 X-MS-Exchange-AntiSpam-MessageData: VGOioca5VG+fX7dZwLMZ/wTgCxumtZXZNpZfYhwsDSu2NNQAu9+XebRa4JLmwBFAelrL9D7GjNVhMTEU4zwgXcrsRJyMEbgvGzlPhULZLAYNNEnpWiLvRJkJCDshFCSNSmqMedanDIDPG4DKp5Uo5A== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 740a83f2-1030-42d3-208d-08d7cc12f5e2 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2020 14:36:50.5888 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BUqHZe74+T1eIgpYRVU+/eQWNy5epJqD7qbGGoyHxsza1tHN3mODkd+1T51O2ot+R8KttnH/uTYmhePXlhuMZg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2382 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Pankaj Bansal The Soc info being printed can be removed from SOC lib. We are in the process of implementing PEI Phase. After PEI phase impelmentation this info would be printed in common PEIM based on the information retrieved from PPIs. e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and core info. Signed-off-by: Pankaj Bansal --- Silicon/NXP/Library/SocLib/Chassis.c | 132 ---------------------- Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 16 +-- Silicon/NXP/Library/SocLib/NxpChassis.h | 26 +---- 3 files changed, 2 insertions(+), 172 deletions(-) diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index b8a8118c5e24..2f192e890bcf 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -216,67 +216,6 @@ CpuMaskNext ( return Cpu; } =20 -/* - * Print CPU information - */ -VOID -PrintCpuInfo ( - VOID - ) -{ - SYS_INFO SysInfo; - UINTN CoreIndex; - UINTN Core; - UINT32 Type; - UINT32 NumCpus; - UINT32 Mask; - CHAR8 *CoreName; - - GetSysInfo (&SysInfo); - DEBUG ((DEBUG_INIT, "Clock Configuration:")); - - NumCpus =3D CpuNumCores (); - Mask =3D CpuMask (); - - for (CoreIndex =3D 0, Core =3D CpuMaskNext(-1, Mask); - CoreIndex < NumCpus; - CoreIndex++, Core =3D CpuMaskNext(Core, Mask)) - { - if (!(CoreIndex % 3)) { - DEBUG ((DEBUG_INIT, "\n ")); - } - - Type =3D TP_ITYP_VERSION (QoriqCoreToType (Core)); - switch (Type) { - case TY_ITYP_VERSION_A7: - CoreName =3D "A7"; - break; - case TY_ITYP_VERSION_A53: - CoreName =3D "A53"; - break; - case TY_ITYP_VERSION_A57: - CoreName =3D "A57"; - break; - case TY_ITYP_VERSION_A72: - CoreName =3D "A72"; - break; - default: - CoreName =3D " Unknown Core "; - } - DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", - Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ)); - } - - DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBu= s / MHZ)); - DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ)); - - if (SysInfo.FreqFman[0] !=3D 0) { - DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[= 0] / MHZ)); - } - - DEBUG ((DEBUG_INIT, "\n")); -} - /* * Return system bus frequency */ @@ -307,77 +246,6 @@ GetSdxcFrequency ( return SocSysInfo.FreqSdhc; } =20 -/* - * Print Soc information - */ -VOID -PrintSoc ( - VOID - ) -{ - CHAR8 Buf[20]; - CCSR_GUR *GurBase; - UINTN Count; - // - // Svr : System Version Register - // - UINTN Svr; - UINTN Ver; - - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - - Svr =3D GurRead ((UINTN)&GurBase->Svr); - Ver =3D SVR_SOC_VER (Svr); - - for (Count =3D 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) =3D=3D Ver) { - AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name); - - if (IS_E_PROCESSOR (Svr)) { - AsciiStrCatS (Buf, sizeof (Buf), "E"); - } - break; - } - } - - DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n", - Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr))); - - return; -} - -/* - * Dump RCW (Reset Control Word) on console - */ -VOID -PrintRCW ( - VOID - ) -{ - CCSR_GUR *Base; - UINTN Count; - - Base =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - - /* - * Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - - DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):")); - for (Count =3D 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) { - UINT32 Rcw =3D SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]); - - if ((Count % 4) =3D=3D 0) { - DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4)); - } - - DEBUG ((DEBUG_INIT, " %08x", Rcw)); - } - - DEBUG ((DEBUG_INIT, "\n")); -} - /* * Setup SMMU in bypass mode * and also set its pagesize diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index bfb8b8cb339a..687a1d940066 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -1,7 +1,7 @@ /** @Soc.c SoC specific Library containg functions to initialize various SoC compon= ents =20 - Copyright 2017-2019 NXP + Copyright 2017-2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -131,10 +131,6 @@ GetSysInfo ( =20 /** Function to initialize SoC specific constructs - CPU Info - SoC Personality - Board Personality - RCW prints **/ VOID SocInit ( @@ -147,16 +143,6 @@ SocInit ( // Early init serial Port to get board information. // SerialPortInitialize (); - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n", - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE_= _)); - - PrintCpuInfo (); - - // - // Print Reset control Word - // - PrintRCW (); - PrintSoc (); =20 return; } diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/= SocLib/NxpChassis.h index 99f6439d8f35..a11acf71563e 100644 --- a/Silicon/NXP/Library/SocLib/NxpChassis.h +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h @@ -1,7 +1,7 @@ /** @file * Header defining the Base addresses, sizes, flags etc for chassis 1 * -* Copyright 2017-2019 NXP +* Copyright 2017-2020 NXP * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -54,14 +54,6 @@ typedef struct { UINTN SdhcClk; } SOC_CLOCK_INFO; =20 -/* - * Print Soc information - */ -VOID -PrintSoc ( - VOID - ); - /* * Initialize Clock structure */ @@ -79,22 +71,6 @@ SmmuInit ( VOID ); =20 -/* - * Print CPU information - */ -VOID -PrintCpuInfo ( - VOID - ); - -/* - * Dump RCW (Reset Control Word) on console - */ -VOID -PrintRCW ( - VOID - ); - UINT32 InitiatorType ( IN UINT32 Cluster, --=20 2.17.1