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Received: from VI1PR0401MB2496.eurprd04.prod.outlook.com (10.168.65.10) by VI1PR0401MB2254.eurprd04.prod.outlook.com (10.169.133.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2814.14; Thu, 19 Mar 2020 14:36:56 +0000 Received: from VI1PR0401MB2496.eurprd04.prod.outlook.com ([fe80::196a:28a9:bb9:2fae]) by VI1PR0401MB2496.eurprd04.prod.outlook.com ([fe80::196a:28a9:bb9:2fae%9]) with mapi id 15.20.2835.017; Thu, 19 Mar 2020 14:36:56 +0000 From: Pankaj Bansal To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton Subject: [PATCH v2 12/28] Silicon/NXP: Remove unnecessary PCDs Date: Fri, 20 Mar 2020 20:05:27 +0530 Message-ID: <20200320143543.18615-13-pankaj.bansal@oss.nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200320143543.18615-1-pankaj.bansal@oss.nxp.com> References: <20200320143543.18615-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR02CA0042.apcprd02.prod.outlook.com (2603:1096:3:18::30) To VI1PR0401MB2496.eurprd04.prod.outlook.com (2603:10a6:800:56::10) Return-Path: pankaj.bansal@oss.nxp.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR02CA0042.apcprd02.prod.outlook.com (2603:1096:3:18::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2835.19 via Frontend Transport; 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Received-SPF: None (protection.outlook.com: oss.nxp.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /yuFbnVB73cSSetnzmmB9BjWojVoISj3OUlHeWhsPz8c+S1wT6pO8yeZ4FXGWmVZvPpZNFCSRM1ixQQze4nzHZt5hzEGcA9RzQrMWrHf4vViQ7E9AtmBwoWDmpb/JNlTZbxLBbd0gVsIyAQq88Dpv7VOrZuU+OYguSojxA9iuqSRAfeqeWVW30RNY19/NRJZPoDaRYNMovshhtmFY2Taw8NbDisEFo2IeSBt3cHPgtqt4kefHAI4DNUi6pute9jbbC5rv/y3E2IDQqZOtR78905zy0viS05wSmaLD4XQ1S5/wb8A/Dr09ZZd5PSyoEc4QiZdSj395QR+eAAE2xSc9on4jdr+JeMxRY1VDX0/1gJPbhs5Elyf1sokMXaX2U4FDogO83+TcKM3nc9gJhy8m1BtptQ7bFbhwrHIjXejtu91PJ5s196yr8SX3TZEwHlW X-MS-Exchange-AntiSpam-MessageData: vdWJhhomOseekN3oWsqdPMAQQNyM8NJZTJdwksoVh9atdMN3MesOzMUso5V6kiys12zKpNym1MjqPtA2ZgvrcsNiyWqY9NJTeZeMctRqhL+qdhJJN1tu+KKy6JubXdmoI1JtnexoGDwhmWYU6ns8eA== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e0200f71-b5d1-452a-9985-08d7cc12f96f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2020 14:36:56.5441 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0d016tgQYU/FoxFjba6BdbUAKmj5IkCKWAayYpsQAxTKim6enQJ7sMYAUVByizQ4upuPEqJTDhb1IHYmgM6Aew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2254 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Pankaj Bansal The memory map of an SOC is fixed in hardware. it doesn't change with platform that uses SOC. So, there is no need to keep PCDs for these values and we can use macros for these in SOC header file. Any Platform using the SOC, can make use of the SOC header file. Signed-off-by: Pankaj Bansal --- .../Drivers/PlatformDxe/PlatformDxe.c | 15 ++-- .../Drivers/PlatformDxe/PlatformDxe.inf | 10 +-- .../Library/PlatformLib/ArmPlatformLib.inf | 21 +---- .../Library/PlatformLib/NxpQoriqLsMem.c | 79 +++++++++---------- Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 + Silicon/NXP/LS1043A/Include/Soc.h | 44 +++++++++++ Silicon/NXP/LS1043A/LS1043A.dsc.inc | 26 ------ Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +- Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 - Silicon/NXP/NxpQoriqLs.dec | 47 ----------- 10 files changed, 97 insertions(+), 150 deletions(-) create mode 100644 Silicon/NXP/LS1043A/Include/Soc.h diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b= /Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c index f89dcdeff3c1..62c400eb1a58 100644 --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c @@ -1,7 +1,7 @@ /** @file LS1043 DXE platform driver. =20 - Copyright 2018-2019 NXP + Copyright 2018-2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include =20 @@ -22,7 +23,7 @@ typedef struct { UINT8 EndDesc; } ADDRESS_SPACE_DESCRIPTOR; =20 -STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cControlle= r)]; +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS]; =20 STATIC EFI_STATUS @@ -65,19 +66,19 @@ PopulateI2cInformation ( { UINT32 Index; =20 - for (Index =3D 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) = { + for (Index =3D 0; Index < ARRAY_SIZE (mI2cDesc); Index++) { mI2cDesc[Index].StartDesc.Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; mI2cDesc[Index].StartDesc.Len =3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCR= IPTOR) - 3; mI2cDesc[Index].StartDesc.ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; mI2cDesc[Index].StartDesc.GenFlag =3D 0; mI2cDesc[Index].StartDesc.SpecificFlag =3D 0; mI2cDesc[Index].StartDesc.AddrSpaceGranularity =3D 32; - mI2cDesc[Index].StartDesc.AddrRangeMin =3D FixedPcdGet64 (PcdI2c0BaseA= ddr) + - (Index * FixedPcdGet32 (PcdI2= cSize)); + mI2cDesc[Index].StartDesc.AddrRangeMin =3D LS1043A_I2C0_PHYS_ADDRESS + + (Index * LS1043A_I2C_SIZE); mI2cDesc[Index].StartDesc.AddrRangeMax =3D mI2cDesc[Index].StartDesc.A= ddrRangeMin + - FixedPcdGet32 (PcdI2cSize) - = 1; + LS1043A_I2C_SIZE - 1; mI2cDesc[Index].StartDesc.AddrTranslationOffset =3D 0; - mI2cDesc[Index].StartDesc.AddrLen =3D FixedPcdGet32 (PcdI2cSize); + mI2cDesc[Index].StartDesc.AddrLen =3D LS1043A_I2C_SIZE; =20 mI2cDesc[Index].EndDesc =3D ACPI_END_TAG_DESCRIPTOR; } diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf= b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf index d689cf4db58e..038d48949a39 100644 --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf @@ -2,7 +2,7 @@ # # Component description file for LS1043 DXE platform driver. # -# Copyright 2018-2019 NXP +# Copyright 2018-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -21,9 +21,10 @@ [Sources] =20 [Packages] ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec + Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] @@ -43,10 +44,5 @@ [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES =20 -[FixedPcd] - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController - [Depex] TRUE diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf index f7ae74afc6ca..7563a1c43630 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -1,7 +1,7 @@ # @file # # Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. -# Copyright 2017, 2019 NXP +# Copyright 2017, 2019-2020 NXP # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -19,6 +19,7 @@ [Packages] ArmPlatformPkg/ArmPlatformPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec + Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] @@ -35,21 +36,3 @@ [Ppis] =20 [FixedPcd] gArmTokenSpaceGuid.PcdArmPrimaryCore - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c index c6c256da0727..f5fa308551aa 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -6,7 +6,7 @@ * * Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. -* Copyright 2017, 2019 NXP +* Copyright 2017, 2019-2020 NXP * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -16,7 +16,7 @@ #include #include #include -#include +#include =20 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 =20 @@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap ( { UINTN Index; ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; - DRAM_INFO DramInfo; =20 Index =3D 0; =20 @@ -51,24 +50,20 @@ ArmPlatformGetVirtualMemoryMap ( return; } =20 - if (GetDramBankInfo (&DramInfo)) { - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n")); - return; - } + VirtualMemoryTable[Index].PhysicalBase =3D LS1043A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_DRAM0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_DRAM0_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK; =20 - - for (Index =3D 0; Index < DramInfo.NumOfDrams; Index++) { - // DRAM1 (Must be 1st entry) - VirtualMemoryTable[Index].PhysicalBase =3D DramInfo.DramRegion[Index].= BaseAddress; - VirtualMemoryTable[Index].VirtualBase =3D DramInfo.DramRegion[Index].= BaseAddress; - VirtualMemoryTable[Index].Length =3D DramInfo.DramRegion[Index].= Size; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK; - } + VirtualMemoryTable[Index].PhysicalBase =3D LS1043A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_DRAM1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_DRAM1_SIZE; + VirtualMemoryTable[Index++].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK; =20 // CCSR Space - VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdCcsrBaseAdd= r); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdCcsrSize); + VirtualMemoryTable[Index].PhysicalBase =3D LS1043A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_CCSR_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_CCSR_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // IFC region 1 @@ -85,51 +80,51 @@ ArmPlatformGetVirtualMemoryMap ( // For write transactions from non-core masters (like system= DMA), the address // should be 16 byte aligned and the data size should be = multiple of 16 bytes. // - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 1BaseAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion1B= aseAddr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion1S= ize); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_IFC0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_IFC0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_IFC0_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // QMAN SWP - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQmanSwpBa= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQmanSwpBase= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQmanSwpSize= ); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_QMAN_SW_PORTAL_PHYS= _ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_QMAN_SW_PORTAL_PHYS_A= DDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_QMAN_SW_PORTAL_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; =20 // BMAN SWP - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdBmanSwpBa= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdBmanSwpBase= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdBmanSwpSize= ); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_BMAN_SW_PORTAL_PHYS= _ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_BMAN_SW_PORTAL_PHYS_A= DDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_QMAN_SW_PORTAL_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; =20 // IFC region 2 - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdIfcRegion= 2BaseAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdIfcRegion2B= aseAddr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdIfcRegion2S= ize); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_IFC1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_IFC1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_IFC1_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // PCIe1 - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp1Ba= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp1Base= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp1Base= Size); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_PCI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_PCI0_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_PCI_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // PCIe2 - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp2Ba= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp2Base= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp2Base= Size); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_PCI1_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_PCI1_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_PCI_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // PCIe3 - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdPciExp3Ba= seAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdPciExp3Base= Addr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdPciExp3Base= Size); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_PCI2_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_PCI2_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_PCI_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; =20 // QSPI region - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdQspiRegio= nBaseAddr); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdQspiRegionB= aseAddr); - VirtualMemoryTable[Index].Length =3D FixedPcdGet64 (PcdQspiRegionS= ize); + VirtualMemoryTable[++Index].PhysicalBase =3D LS1043A_QSPI_PHYS_ADDRESS; + VirtualMemoryTable[Index].VirtualBase =3D LS1043A_QSPI_PHYS_ADDRESS; + VirtualMemoryTable[Index].Length =3D LS1043A_QSPI_SIZE; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; =20 // End of Table diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Ch= assis2/NxpSoc.h index 74330b6205e7..6812beafe447 100644 --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h @@ -12,6 +12,8 @@ =20 #define CLK_FREQ 100000000 =20 +#define CHASSIS2_DCFG_ADDRESS 0x1EE0000 + /* SMMU Defintions */ #define SMMU_BASE_ADDR 0x09000000 #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Includ= e/Soc.h new file mode 100644 index 000000000000..441871757d67 --- /dev/null +++ b/Silicon/NXP/LS1043A/Include/Soc.h @@ -0,0 +1,44 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SOC_H__ +#define SOC_H__ + +/** + Soc Memory Map +**/ +#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000 +#define LS1043A_DRAM0_SIZE SIZE_2GB +#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000 +#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB + +#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000 +#define LS1043A_CCSR_SIZE 0xF000000 + +#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000 +#define LS1043A_IFC0_SIZE SIZE_512MB +#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000 +#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB + +#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000 +#define LS1043A_QSPI_SIZE SIZE_512MB + +#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000 +#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB +#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000 +#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB + +#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000 +#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000 +#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000 +#define LS1043A_PCI_SIZE SIZE_32GB + +#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000 +#define LS1043A_I2C_SIZE 0x10000 +#define LS1043A_I2C_NUM_CONTROLLERS 4 + +#endif // SOC_H__ diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS10= 43A.dsc.inc index f57a0d95b8e1..6239cfe761e6 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -29,32 +29,6 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE =20 - # - # CCSR Address Space and other attached Memories - # - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 - # # Big Endian IPs # diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index d992e53546f4..98ca2e162f7b 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -34,7 +34,7 @@ GetSysInfo ( CCSR_GUR *GurBase; UINTN SysClk; =20 - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); + GurBase =3D (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS; SysClk =3D CLK_FREQ; =20 SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index f75a8d19f5a5..b7c7fc78cc8f 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -36,5 +36,4 @@ [BuildOptions] [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 943dbac81013..b478560450b3 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -22,53 +22,6 @@ [Guids.common] gNxpNonDiscoverableI2cMasterGuid =3D { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e= , 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}} =20 [PcdsFixedAtBuild.common] - # - # Pcds for I2C Controller - # - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001 - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002 - - # - # Pcds for base address and size - # - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100 - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103 - gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105 - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106 - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107 - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108 - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109 - gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A - gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B - gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C - gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110 - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118 - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119 - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122 - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123 - - # - # IFC PCDs - # - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192 - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193 - # # Platform PCDs # --=20 2.17.1