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X-Microsoft-Antispam-Message-Info: qHUP1nyCKUxkuydVttVYs9uKFIn8CWr1mm6V7cfrzr9+13pUM8qb0ESTvavSmjWuDXRk1KY6CZJg2MK4NxP2zFPaZQxffCUT8Sv/6o+jNC9vCZVuEzkQMFAAURkXeEvj6VVijCsmZ6E4royeWK0L4H2b4+0I86xtuYfpSkphbeTgTF1pzRJprM7CILVqKxAZD2CW0yqDe46bpfUPhmEQ2GCl9x2bhNUJNvJXIXVYL4dzyL/fo9ZOaorG8y6delive1jUQbg+baDgLe5EPDNuWIpUSQnfY/vTepGuq/KavRFsha92kYUVajZoAf5Xtovl0WHnTmejEhJ4Fz7V7JSdweovKAQNXFImlGgEbeWIx04AqZcQ5owD4qvAiYB817y63kUMUuutD+Jv5al1v6Xo3XuTVMsPGXnMopCXwoAKE/JJd1CxkU8pMcV7gXT3EHpV X-MS-Exchange-AntiSpam-MessageData: M73/RY8AHCUhV0jRAI7hBEK79oPDlUb5h1SkPgvvXj6g7sQMXFejJHzd5UczYhAVEyq37MstEDbkgFNLdb4RMYjhfaWKcfRVpjZG+hwH/P8YoH9H3248IMijiIOnFxRjpEUWCKsRfGzktCY0rLUDKg== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c0ae7e11-e366-4cfe-72d7-08d7cc12fea6 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2020 14:37:05.4391 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4sPBtPw+lzCb39W6MPL2puXB21w7lEQNV4tYLyuPukeyVRPcEqv0Xv3+Zk1TG1sMt3+1V+wmeRegnBhSRGPg1Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2254 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Pankaj Bansal RAM retrieval using SMC commands is common to all Layerscape SOCs. Therefore, move it to commom MemoryInit Pei Lib. Signed-off-by: Pankaj Bansal --- Silicon/NXP/Include/DramInfo.h | 38 ----- .../Library/MemoryInitPei/MemoryInitPeiLib.c | 137 ++++++++++++++---- .../Library/MemoryInitPei/MemoryInitPeiLib.h | 25 ++++ .../MemoryInitPei/MemoryInitPeiLib.inf | 7 +- Silicon/NXP/Library/SocLib/Chassis.c | 67 --------- Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 - 6 files changed, 140 insertions(+), 135 deletions(-) delete mode 100644 Silicon/NXP/Include/DramInfo.h create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.= h deleted file mode 100644 index a934aaeff1f5..000000000000 --- a/Silicon/NXP/Include/DramInfo.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @file -* Header defining the structure for Dram Information -* -* Copyright 2019 NXP -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef DRAM_INFO_H_ -#define DRAM_INFO_H_ - -#include - -#define SMC_DRAM_BANK_INFO (0xC200FF12) - -typedef struct { - UINTN BaseAddress; - UINTN Size; -} DRAM_REGION_INFO; - -typedef struct { - UINT32 NumOfDrams; - UINT32 Reserved; - DRAM_REGION_INFO DramRegion[3]; -} DRAM_INFO; - -EFI_STATUS -GetDramBankInfo ( - IN OUT DRAM_INFO *DramInfo - ); - -VOID -UpdateDpaaDram ( - IN OUT DRAM_INFO *DramInfo - ); - -#endif /* DRAM_INFO_H_ */ diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon= /NXP/Library/MemoryInitPei/MemoryInitPeiLib.c index 3ea773678667..54d026ef1270 100644 --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -17,8 +17,10 @@ #include #include #include +#include + +#include "MemoryInitPeiLib.h" =20 -#include =20 VOID BuildMemoryTypeInformationHob ( @@ -68,10 +70,17 @@ MemoryPeim ( ) { ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + ARM_SMC_ARGS ArmSmcArgs; + INT32 Index; + UINTN DramSize; + UINTN BaseAddress; + UINTN Size; + UINTN Top; + DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS]; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; - EFI_PEI_HOB_POINTERS NextHob; - BOOLEAN Found; - DRAM_INFO DramInfo; + UINTN FdBase; + UINTN FdTop; + BOOLEAN FoundSystemMem; =20 // Get Virtual Memory Map from the Platform Library ArmPlatformGetVirtualMemoryMap (&MemoryTable); @@ -94,40 +103,112 @@ MemoryPeim ( EFI_RESOURCE_ATTRIBUTE_TESTED ); =20 - if (GetDramBankInfo (&DramInfo)) { - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n")); - return EFI_UNSUPPORTED; - } - - while (DramInfo.NumOfDrams--) { - // - // Check if the resource for the main system memory has been declared - // - Found =3D FALSE; - NextHob.Raw =3D GetHobList (); - while ((NextHob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, = NextHob.Raw)) !=3D NULL) { - if ((NextHob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SY= STEM_MEMORY) && - (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >=3D NextH= ob.ResourceDescriptor->PhysicalStart) && - (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDes= criptor->ResourceLength <=3D - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo= .DramRegion[DramInfo.NumOfDrams].Size)) - { - Found =3D TRUE; - break; + FoundSystemMem =3D FALSE; + ZeroMem (DramRegions, sizeof (DramRegions)); + + Index =3D -1; + do { + ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; + ArmSmcArgs.Arg1 =3D Index++; + + ArmCallSmc (&ArmSmcArgs); + ASSERT (!(ArmSmcArgs.Arg0 && !Index)); + if (!Index) { + DramSize =3D ArmSmcArgs.Arg1; + } else { + if (!ArmSmcArgs.Arg0) { + BaseAddress =3D ArmSmcArgs.Arg1; + Size =3D ArmSmcArgs.Arg2; + ASSERT (BaseAddress && Size); + + DramRegions[Index - 1].BaseAddress =3D BaseAddress; + DramRegions[Index - 1].Size =3D Size; + DramSize -=3D Size; + + DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", + Index, BaseAddress, Size)); } - NextHob.Raw =3D GET_NEXT_HOB (NextHob); + } + } while (DramSize && Index < MAX_DRAM_REGIONS); + + ASSERT (!DramSize); + + FdBase =3D (UINTN)FixedPcdGet64 (PcdFdBaseAddress); + FdTop =3D FdBase + (UINTN)FixedPcdGet32 (PcdFdSize); + + // Declare memory regios to system + for (Index =3D MAX_DRAM_REGIONS - 1; Index >=3D 0; Index--) { + if (!DramRegions[Index].Size) { + continue; } =20 - if (!Found) { - // Reserved the memory space occupied by the firmware volume + BaseAddress =3D DramRegions[Index].BaseAddress; + Top =3D DramRegions[Index].BaseAddress + DramRegions[Index].Size; + + // EDK2 does not have the concept of boot firmware copied into DRAM. + // To avoid the DXE core to overwrite this area we must create a memor= y + // allocation HOB for the region, but this only works if we split off = the + // underlying resource descriptor as well. + if (FdBase >=3D BaseAddress && FdTop <=3D Top) { + // Update Size + Size =3D FdBase - BaseAddress; + if (Size) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + BaseAddress, + Size + ); + } + // create the System Memory HOB for the firmware BuildResourceDescriptorHob ( EFI_RESOURCE_SYSTEM_MEMORY, ResourceAttributes, - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress, - DramInfo.DramRegion[DramInfo.NumOfDrams].Size + FdBase, + PcdGet32 (PcdFdSize) ); + // Create the System Memory HOB for the remaining region (top of the= FD)s + Size =3D Top - FdTop; + if (Size) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FdTop, + Size + ); + }; + // Mark the memory covering the Firmware Device as boot services dat= a + BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress), + FixedPcdGet32 (PcdFdSize), + EfiBootServicesData); + } else { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + DramRegions[Index].BaseAddress, + DramRegions[Index].Size + ); + } + + if (FoundSystemMem) { + continue; + } + + BaseAddress =3D DramRegions[Index].BaseAddress; + Size =3D DramRegions[Index].Size; + Top =3D DramRegions[Index].BaseAddress + DramRegions[Index].Size; + + if (FdBase >=3D BaseAddress && FdTop <=3D Top) { + Size -=3D (UINTN)FixedPcdGet32 (PcdFdSize); + } + + if (Size >=3D FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) { + FoundSystemMem =3D TRUE; } } =20 + ASSERT (FoundSystemMem); + // Build Memory Allocation Hob InitMmu (MemoryTable); =20 diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon= /NXP/Library/MemoryInitPei/MemoryInitPeiLib.h new file mode 100644 index 000000000000..edbf0ceaf638 --- /dev/null +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h @@ -0,0 +1,25 @@ +/** @file +* +* Copyright 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef MEMORY_INIT_PEI_LIB_H_ +#define MEMORY_INIT_PEI_LIB_H_ + +#include + +// Specifies the Maximum regions onto which DDR memory can be mapped in +// a Platform +#define MAX_DRAM_REGIONS 3 +#define SMC_DRAM_BANK_INFO (0xC200FF12) + +typedef struct { + UINTN BaseAddress; + UINTN Size; +} DRAM_REGION_INFO; + +#endif // MEMORY_INIT_PEI_LIB_H_ + diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silic= on/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf index a5bd39415def..ad2371115b17 100644 --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -18,7 +18,6 @@ [Defines] [Sources] MemoryInitPeiLib.c =20 - [Packages] ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec @@ -30,6 +29,7 @@ [Packages] [LibraryClasses] ArmMmuLib ArmPlatformLib + ArmSmcLib DebugLib HobLib PcdLib @@ -40,6 +40,11 @@ [Guids] [FeaturePcd] gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob =20 +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index 847331a63152..1ef99e8de25f 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -22,7 +22,6 @@ #include #include =20 -#include #include "NxpChassis.h" =20 UINT32 @@ -75,69 +74,3 @@ SmmuInit ( MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); } =20 -UINTN -GetDramSize ( - IN VOID - ) -{ - ARM_SMC_ARGS ArmSmcArgs; - - ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; - ArmSmcArgs.Arg1 =3D -1; - - ArmCallSmc (&ArmSmcArgs); - - if (ArmSmcArgs.Arg0) { - return 0; - } else { - return ArmSmcArgs.Arg1; - } -} - -EFI_STATUS -GetDramBankInfo ( - IN OUT DRAM_INFO *DramInfo - ) -{ - ARM_SMC_ARGS ArmSmcArgs; - UINT32 I; - UINTN DramSize; - - DramSize =3D GetDramSize (); - DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize)); - - // Ensure DramSize has been set - ASSERT (DramSize !=3D 0); - - I =3D 0; - - do { - ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; - ArmSmcArgs.Arg1 =3D I; - - ArmCallSmc (&ArmSmcArgs); - if (ArmSmcArgs.Arg0) { - if (I > 0) { - break; - } else { - ASSERT (ArmSmcArgs.Arg0 =3D=3D 0); - } - } - - DramInfo->DramRegion[I].BaseAddress =3D ArmSmcArgs.Arg1; - DramInfo->DramRegion[I].Size =3D ArmSmcArgs.Arg2; - - DramSize -=3D DramInfo->DramRegion[I].Size; - - DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", - I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size= )); - - I++; - } while (DramSize); - - DramInfo->NumOfDrams =3D I; - - DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDra= ms)); - - return EFI_SUCCESS; -} diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index b7c7fc78cc8f..99d89498e0e2 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -20,7 +20,6 @@ [Packages] Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] - ArmSmcLib BaseLib DebugLib IoAccessLib --=20 2.17.1