* [PATCH v2 01/28] Silicon/NXP: Add I2c lib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-03-31 11:51 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 02/28] Silicon/NXP: changes to use I2clib in i2cdxe Pankaj Bansal
` (28 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
I2c lib is going to be used in PrePeiCore sec module to get the
System clock information from devices connected to i2c (like fpga
or clock generator)
since we don't have support of DXE modules this early in boot stage,
move the i2c controller functionality in library.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/NxpQoriqLs.dsc.inc | 4 +-
Silicon/NXP/Include/Library/I2cLib.h | 120 ++++
Silicon/NXP/Library/I2cLib/I2cLib.c | 576 ++++++++++++++++++++
Silicon/NXP/Library/I2cLib/I2cLib.inf | 31 ++
Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 105 ++++
Silicon/NXP/NxpQoriqLs.dec | 10 +-
6 files changed, 844 insertions(+), 2 deletions(-)
create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index fa5f30dd3909..b28e0615f7ca 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -1,6 +1,6 @@
# @file
#
-# Copyright 2017-2019 NXP.
+# Copyright 2017-2020 NXP.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -94,6 +94,8 @@ [LibraryClasses.common]
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
+
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
diff --git a/Silicon/NXP/Include/Library/I2cLib.h b/Silicon/NXP/Include/Library/I2cLib.h
new file mode 100644
index 000000000000..e39237abd3ee
--- /dev/null
+++ b/Silicon/NXP/Include/Library/I2cLib.h
@@ -0,0 +1,120 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef I2C_LIB_H__
+#define I2C_LIB_H__
+
+#include <Uefi.h>
+#include <Pi/PiI2c.h>
+
+/**
+ software reset of the entire I2C module.
+ The module is reset and disabled.
+ Status register fields (IBSR) are cleared.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly reset the I2c module
+**/
+EFI_STATUS
+I2cReset (
+ IN UINTN Base
+ );
+
+/**
+ Early init I2C for reading the sysclk from I2c slave device.
+ I2c bus clock is determined from the clock input to I2c controller.
+ The clock input to I2c controller is derived from the sysclk.
+ sysclk is determined by clock generator, which is controller by i2c.
+
+ So, it's a chicken-egg problem to read the sysclk from clock generator.
+ To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
+ lowest value, in the hope that it won't be out of clock generator's supported
+ i2c clock frequency. Once we have the correct sysclk, we can setup the
+ correct i2c bus clock.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+**/
+EFI_STATUS
+I2cEarlyInitialize (
+ IN UINTN Base
+ );
+
+/**
+ Configure I2c bus to operate at a given speed
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] I2cBusClock Input clock to I2c controller
+ @param[in] Speed speed to be configured for I2c bus
+
+ @return EFI_SUCCESS successfuly setup the i2c bus
+**/
+EFI_STATUS
+I2cInitialize (
+ IN UINTN Base,
+ IN UINT64 I2cBusClock,
+ IN UINT64 Speed
+ );
+
+/**
+ Transfer data to/from I2c slave device
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which data is to be read
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
+ describing the I2C transaction
+
+ @return EFI_SUCCESS successfuly transfer the data
+ @return EFI_DEVICE_ERROR There was an error while transferring data through
+ I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusXfer (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket
+ );
+
+/**
+ Read a register from I2c slave device. This API is wrapper around I2cBusXfer
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which register value is
+ to be read
+ @param[in] RegAddress Register Address in Slave's memory map
+ @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to
+ I2c Slave for simple reads without any
+ register, make this value = 0
+ (RegAddress is don't care in that case)
+ @param[out] RegValue Value to be read from I2c slave's regiser
+ @param[in] RegValueNumBytes Number of bytes to read from I2c slave
+ register
+
+ @return EFI_SUCCESS successfuly read the registers
+ @return EFI_DEVICE_ERROR There was an error while transferring data through
+ I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusReadReg (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN UINT64 RegAddress,
+ IN UINT8 RegAddressWidthInBytes,
+ OUT UINT8 *RegValue,
+ IN UINT32 RegValueNumBytes
+ );
+
+#endif // I2C_LIB_H__
diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.c b/Silicon/NXP/Library/I2cLib/I2cLib.c
new file mode 100644
index 000000000000..08bf14c490be
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLib.c
@@ -0,0 +1,576 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2017, 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/I2cLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+
+#include "I2cLibInternal.h"
+
+/**
+ I2C divisor and Ibfd register values when glitch filter is enabled
+
+ In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
+ has been selected. A higher MUL value results in a lower sampling rate of
+ the I2C signals. This gives the I2C module greater immunity against glitches
+ in the I2C signals.
+**/
+STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchEnabled[] = {
+ { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 },
+ { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA },
+ { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 },
+ { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 },
+ { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A },
+ { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 },
+ { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 },
+ { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A },
+ { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 },
+ { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 },
+ { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 },
+ { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D },
+ { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 },
+ { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 },
+ { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC },
+ { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF },
+ { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 },
+ { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC },
+ { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF }
+};
+
+/**
+ I2C divisor and Ibfd register values when glitch filter is disabled
+
+ In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
+ has been selected. A higher MUL value results in a lower sampling rate of
+ the I2C signals. This gives the I2C module greater immunity against glitches
+ in the I2C signals.
+**/
+STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchDisabled[] = {
+ { 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 },
+ { 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 },
+ { 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 },
+ { 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 },
+ { 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 },
+ { 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 },
+ { 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B },
+ { 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 },
+ { 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 },
+ { 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 },
+ { 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C },
+ { 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F },
+ { 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 },
+ { 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC },
+ { 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF },
+ { 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 },
+ { 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC },
+ { 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF }
+};
+
+/**
+ ERR009203 : I2C may not work reliably with the default setting
+
+ Description : The clocking circuitry of I2C module may not work reliably due
+ to the slow rise time of SCL signal.
+ Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_EN]
+ to 1.
+**/
+STATIC
+VOID
+I2cErratumA009203 (
+ IN UINTN Base
+ )
+{
+ I2C_REGS *Regs;
+
+ Regs = (I2C_REGS *)Base;
+
+ MmioOr8 ((UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN);
+}
+
+/**
+ software reset of the entire I2C module.
+ The module is reset and disabled.
+ Status register fields (IBSR) are cleared.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly reset the I2c module
+**/
+EFI_STATUS
+I2cReset (
+ IN UINTN Base
+ )
+{
+ I2C_REGS *Regs;
+
+ Regs = (I2C_REGS *)Base;
+
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
+ MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
+ MmioAnd8 ((UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Early init I2C for reading the sysclk from I2c slave device.
+ I2c bus clock is determined from the clock input to I2c controller.
+ The clock input to I2c controller is derived from the sysclk.
+ sysclk is determined by clock generator, which is controller by i2c.
+
+ So, it's a chicken-egg problem to read the sysclk from clock generator.
+ To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
+ lowest value, in the hope that it won't be out of clock generator's supported
+ i2c clock frequency. Once we have the correct sysclk, we can setup the
+ correct i2c bus clock.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+**/
+EFI_STATUS
+I2cEarlyInitialize (
+ IN UINTN Base
+ )
+{
+ I2C_REGS *Regs;
+ UINT8 Ibfd;
+
+ Regs = (I2C_REGS *)Base;
+ if (FeaturePcdGet (PcdI2cErratumA009203)) {
+ I2cErratumA009203 (Base);
+ }
+
+ if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
+ Ibfd = ARRAY_LAST_ELEM (mI2cClockDivisorGlitchEnabled).Ibfd;
+ } else {
+ Ibfd = ARRAY_LAST_ELEM (mI2cClockDivisorGlitchDisabled).Ibfd;
+ }
+
+ MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
+
+ I2cReset (Base);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure I2c bus to operate at a given speed
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] I2cBusClock Input clock to I2c controller
+ @param[in] Speed speed to be configured for I2c bus
+
+ @return EFI_SUCCESS successfuly setup the i2c bus
+**/
+EFI_STATUS
+I2cInitialize (
+ IN UINTN Base,
+ IN UINT64 I2cBusClock,
+ IN UINT64 Speed
+ )
+{
+ I2C_REGS *Regs;
+ UINT16 ClockDivisor;
+ UINT8 Ibfd; // I2c Bus Frequency Dividor Register
+ CONST I2C_CLOCK_DIVISOR_PAIR *ClockDivisorPair;
+ UINT32 ClockDivisorPairSize;
+ UINT32 Index;
+
+ Regs = (I2C_REGS *)Base;
+ if (FeaturePcdGet (PcdI2cErratumA009203)) {
+ I2cErratumA009203 (Base);
+ }
+
+ Ibfd = 0;
+ ClockDivisor = (I2cBusClock + Speed - 1) / Speed;
+
+ if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
+ ClockDivisorPair = mI2cClockDivisorGlitchEnabled;
+ ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchEnabled);
+ } else {
+ ClockDivisorPair = mI2cClockDivisorGlitchDisabled;
+ ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchDisabled);
+ }
+
+ if (ClockDivisor > ClockDivisorPair[ClockDivisorPairSize - 1].Divisor) {
+ Ibfd = ClockDivisorPair[ClockDivisorPairSize - 1].Ibfd;
+ } else {
+ for (Index = 0; Index < ClockDivisorPairSize; Index++) {
+ if (ClockDivisorPair[Index].Divisor >= ClockDivisor) {
+ Ibfd = ClockDivisorPair[Index].Ibfd;
+ break;
+ }
+ }
+ }
+
+ MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
+
+ I2cReset (Base);
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cBusTestBusBusy (
+ IN I2C_REGS *Regs,
+ IN BOOLEAN TestBusy
+ )
+{
+ UINT32 Index;
+ UINT8 Reg;
+
+ for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
+ Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
+
+ if (Reg & I2C_IBSR_IBAL) {
+ MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
+ return EFI_NOT_READY;
+ }
+
+ if (TestBusy && (Reg & I2C_IBSR_IBB)) {
+ break;
+ }
+
+ if (!TestBusy && !(Reg & I2C_IBSR_IBB)) {
+ break;
+ }
+
+ MicroSecondDelay (1);
+ }
+
+ if (Index == I2C_NUM_RETRIES) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cTransferComplete (
+ IN I2C_REGS *Regs,
+ IN BOOLEAN TestRxAck
+)
+{
+ UINT32 Index;
+ UINT8 Reg;
+
+ for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
+ Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
+
+ if (Reg & I2C_IBSR_IBIF) {
+ // Write 1 to clear the IBIF field
+ MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
+ break;
+ }
+
+ MicroSecondDelay (1);
+ }
+
+ if (Index == I2C_NUM_RETRIES) {
+ return EFI_TIMEOUT;
+ }
+
+ if (TestRxAck && (Reg & I2C_IBSR_RXAK)) {
+ return EFI_NO_RESPONSE;
+ }
+
+ if (Reg & I2C_IBSR_TCF) {
+ return EFI_SUCCESS;
+ }
+
+ return EFI_DEVICE_ERROR;
+}
+
+STATIC
+EFI_STATUS
+I2cRead (
+ IN I2C_REGS *Regs,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_OPERATION *Operation,
+ IN BOOLEAN IsLastOperation
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+
+ // Write Slave Address
+ MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0);
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ // select Receive mode.
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX);
+ if (Operation->LengthInBytes > 1) {
+ // Set No ACK = 0
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_NOACK);
+ }
+
+ // Perform a dummy read to initiate the receive operation.
+ MmioRead8 ((UINTN)&Regs->Ibdr);
+
+ for (Index = 0; Index < Operation->LengthInBytes; Index++) {
+ Status = I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if (Index == (Operation->LengthInBytes - 2)) {
+ // Set No ACK = 1
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_NOACK);
+ } else if (Index == (Operation->LengthInBytes - 1)) {
+ if (!IsLastOperation) {
+ // select Transmit mode (for repeat start)
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_TXRX);
+ } else {
+ // Generate Stop Signal
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ }
+ Operation->Buffer[Index] = MmioRead8 ((UINTN)&Regs->Ibdr);
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cWrite (
+ IN I2C_REGS *Regs,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_OPERATION *Operation
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+
+ // Write Slave Address
+ MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) & (UINT8)(~BIT0));
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Write Data
+ for (Index = 0; Index < Operation->LengthInBytes; Index++) {
+ MmioWrite8 ((UINTN)&Regs->Ibdr, Operation->Buffer[Index]);
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cStop (
+ IN I2C_REGS *Regs
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Reg;
+
+ Status = EFI_SUCCESS;
+ Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
+ if (Reg & I2C_IBSR_IBB) {
+ // Generate Stop Signal
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ // Disable I2c Controller
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+I2cStart (
+ IN I2C_REGS *Regs
+ )
+{
+ EFI_STATUS Status;
+
+ MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
+ MmioAnd8 ((UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS));
+
+ //Wait controller to be stable
+ MicroSecondDelay (1);
+
+ // Generate Start Signal
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MSSL);
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Select Transmit Mode. set No ACK = 1
+ MmioOr8 ((UINTN)&Regs->Ibcr, (I2C_IBCR_TXRX | I2C_IBCR_NOACK));
+
+ return Status;
+}
+
+/**
+ Transfer data to/from I2c slave device
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which data is to be read
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
+ describing the I2C transaction
+
+ @return EFI_SUCCESS successfuly transfer the data
+ @return EFI_DEVICE_ERROR There was an error while transferring data through
+ I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusXfer (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket
+ )
+{
+ UINTN Index;
+ I2C_REGS *Regs;
+ EFI_I2C_OPERATION *Operation;
+ EFI_STATUS Status;
+ BOOLEAN IsLastOperation;
+
+ Regs = (I2C_REGS *)Base;
+ IsLastOperation = FALSE;
+
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ Status = I2cStart (Regs);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ for (Index = 0, Operation = RequestPacket->Operation;
+ Index < RequestPacket->OperationCount;
+ Index++, Operation++) {
+ if (Index == (RequestPacket->OperationCount - 1)) {
+ IsLastOperation = TRUE;
+ }
+ // Send repeat start after first transmit/recieve
+ if (Index) {
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_RSTA);
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+ }
+ // Read/write data
+ if (Operation->Flags & I2C_FLAG_READ) {
+ Status = I2cRead (Regs, SlaveAddress, Operation, IsLastOperation);
+ } else {
+ Status = I2cWrite (Regs, SlaveAddress, Operation);
+ }
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+ }
+
+ErrorExit:
+
+ I2cStop (Regs);
+
+ return Status;
+}
+
+/**
+ Read a register from I2c slave device. This API is wrapper around I2cBusXfer
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which register value is
+ to be read
+ @param[in] RegAddress Register Address in Slave's memory map
+ @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to
+ I2c Slave for simple reads without any
+ register, make this value = 0
+ (RegAddress is don't care in that case)
+ @param[out] RegValue Value to be read from I2c slave's regiser
+ @param[in] RegValueNumBytes Number of bytes to read from I2c slave
+ register
+
+ @return EFI_SUCCESS successfuly read the registers
+ @return EFI_DEVICE_ERROR There was an error while transferring data through
+ I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusReadReg (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN UINT64 RegAddress,
+ IN UINT8 RegAddressWidthInBytes,
+ OUT UINT8 *RegValue,
+ IN UINT32 RegValueNumBytes
+ )
+{
+ EFI_I2C_OPERATION *Operations;
+ I2C_REG_REQUEST RequestPacket;
+ UINTN OperationCount;
+ UINT8 Address[sizeof (RegAddress)];
+ UINT8 *PtrAddress;
+ EFI_STATUS Status;
+
+ ZeroMem (&RequestPacket, sizeof (RequestPacket));
+ OperationCount = 0;
+ Operations = RequestPacket.Operation;
+ PtrAddress = Address;
+
+ if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (RegAddressWidthInBytes != 0) {
+ Operations[OperationCount].LengthInBytes = RegAddressWidthInBytes;
+ Operations[OperationCount].Buffer = PtrAddress;
+ while (RegAddressWidthInBytes--) {
+ *PtrAddress++ = RegAddress >> (8 * RegAddressWidthInBytes);
+ }
+ OperationCount++;
+ }
+
+ Operations[OperationCount].LengthInBytes = RegValueNumBytes;
+ Operations[OperationCount].Buffer = RegValue;
+ Operations[OperationCount].Flags = I2C_FLAG_READ;
+ OperationCount++;
+
+ RequestPacket.OperationCount = OperationCount;
+
+ Status = I2cBusXfer (
+ Base, SlaveAddress,
+ (EFI_I2C_REQUEST_PACKET *)&RequestPacket
+ );
+
+ return Status;
+}
+
diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.inf b/Silicon/NXP/Library/I2cLib/I2cLib.inf
new file mode 100644
index 000000000000..b9bd79ac1ef1
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLib.inf
@@ -0,0 +1,31 @@
+# @file
+#
+# Component description file for I2cLib module
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = I2cLib
+ FILE_GUID = 8ecefc8f-a2c4-4091-b81f-20f7aeb0567f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = I2cLib
+
+[Sources.common]
+ I2cLib.c
+
+[LibraryClasses]
+ IoLib
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203
+
diff --git a/Silicon/NXP/Library/I2cLib/I2cLibInternal.h b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
new file mode 100644
index 000000000000..2ca4a3639d2c
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
@@ -0,0 +1,105 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef I2C_LIB_INTERNAL_H__
+#define I2C_LIB_INTERNAL_H__
+
+#include <Pi/PiI2c.h>
+#include <Uefi.h>
+
+/** Module Disable
+ 0b - The module is enabled. You must clear this field before any other IBCR
+ fields have any effect.
+ 1b - The module is reset and disabled. This is the power-on reset situation.
+ When high, the interface is held in reset, but registers can still be
+ accessed. Status register fields (IBSR) are not valid when the module
+ is disabled.
+**/
+#define I2C_IBCR_MDIS BIT7
+// I2c Bus Interrupt Enable
+#define I2C_IBCR_IBIE BIT6
+/** Master / Slave Mode 0b - Slave mode 1b - Master mode
+ When you change this field from 0 to 1, the module generates a START signal
+ on the bus and selects the master mode. When you change this field from 1 to
+ 0, the module generates a STOP signal and changes the operation mode from
+ master to slave. You should generate a STOP signal only if IBSR[IBIF]=1.
+ The module clears this field without generating a STOP signal when the
+ master loses arbitration.
+*/
+#define I2C_IBCR_MSSL BIT5
+// 0b - Receive 1b - Transmit
+#define I2C_IBCR_TXRX BIT4
+/** Data acknowledge disable
+ Values written to this field are only used when the I2C module is a receiver,
+ not a transmitter.
+ 0b - The module sends an acknowledge signal to the bus at the 9th clock bit
+ after receiving one byte of data.
+ 1b - The module does not send an acknowledge-signal response (that is,
+ acknowledge bit = 1).
+**/
+#define I2C_IBCR_NOACK BIT3
+/**Repeat START
+ If the I2C module is the current bus master, and you program RSTA=1, the I2C
+ module generates a repeated START condition. This field always reads as a 0.
+ If you attempt a repeated START at the wrong time, if the bus is owned by
+ another master the result is loss of arbitration.
+**/
+#define I2C_IBCR_RSTA BIT2
+// DMA enable
+#define I2C_IBCR_DMAEN BIT1
+
+// Transfer Complete
+#define I2C_IBSR_TCF BIT7
+// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy
+#define I2C_IBSR_IBB BIT5
+// Arbitration Lost. software must clear this field by writing a one to it.
+#define I2C_IBSR_IBAL BIT4
+// I2C bus interrupt flag
+#define I2C_IBSR_IBIF BIT1
+// Received acknowledge 0b - Acknowledge received 1b - No acknowledge received
+#define I2C_IBSR_RXAK BIT0
+
+//Bus idle interrupt enable
+#define I2C_IBIC_BIIE BIT7
+
+// Glitch filter enable
+#define I2C_IBDBG_GLFLT_EN BIT3
+
+#define I2C_BUS_TEST_BUSY TRUE
+#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY
+#define I2C_BUS_TEST_RX_ACK TRUE
+#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK
+
+#define ARRAY_LAST_ELEM(x) (x)[ARRAY_SIZE (x) - 1]
+#define I2C_NUM_RETRIES 500
+
+typedef struct _I2C_REGS {
+ UINT8 Ibad; // I2c Bus Address Register
+ UINT8 Ibfd; // I2c Bus Frequency Dividor Register
+ UINT8 Ibcr; // I2c Bus Control Register
+ UINT8 Ibsr; // I2c Bus Status Register
+ UINT8 Ibdr; // I2C Bus Data I/O Register
+ UINT8 Ibic; // I2C Bus Interrupt Config Register
+ UINT8 Ibdbg; // I2C Bus Debug Register
+} I2C_REGS;
+
+/*
+ * sorted list of clock divisor, Ibfd register value pairs
+ */
+typedef struct _I2C_CLOCK_DIVISOR_PAIR {
+ UINT16 Divisor;
+ UINT16 Ibfd; // I2c Bus Frequency Dividor Register value
+} I2C_CLOCK_DIVISOR_PAIR;
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION Operation[2];
+} I2C_REG_REQUEST;
+
+#endif // I2C_LIB_INTERNAL_H__
+
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 764b9bb0e2d3..4a1cfb3e278e 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -1,6 +1,6 @@
# @file.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -13,6 +13,10 @@ [Defines]
[Includes]
Include
+[LibraryClasses]
+ ## @libraryclass Provides services to read/write to I2c devices
+ I2cLib|Include/Library/I2cLib.h
+
[Guids.common]
gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
@@ -101,3 +105,7 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
+
+[PcdsFeatureFlag]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
+
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib
2020-03-20 14:35 ` [PATCH v2 01/28] Silicon/NXP: Add I2c lib Pankaj Bansal
@ 2020-03-31 11:51 ` Leif Lindholm
2020-04-06 6:14 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-03-31 11:51 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:16 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> I2c lib is going to be used in PrePeiCore sec module to get the
> System clock information from devices connected to i2c (like fpga
> or clock generator)
>
> since we don't have support of DXE modules this early in boot stage,
> move the i2c controller functionality in library.
This isn't moving the functionality to a library though - it is moving
the functionality to a library *and* adding new features. These are
two separate changes that should be two separate patches.
The content in this patch is mostly fine as the end result (but some
comments below).
I suggest this patch is reordered with 2/28 and all of the splitting
out part takes place in that patch. This patch can then be reduced to
... the bits that are currently impossible to see are changed (at
least the glitch fixing).
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Platform/NXP/NxpQoriqLs.dsc.inc | 4 +-
> Silicon/NXP/Include/Library/I2cLib.h | 120 ++++
> Silicon/NXP/Library/I2cLib/I2cLib.c | 576 ++++++++++++++++++++
> Silicon/NXP/Library/I2cLib/I2cLib.inf | 31 ++
> Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 105 ++++
> Silicon/NXP/NxpQoriqLs.dec | 10 +-
> 6 files changed, 844 insertions(+), 2 deletions(-)
> create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
>
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> index fa5f30dd3909..b28e0615f7ca 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -1,6 +1,6 @@
> # @file
> #
> -# Copyright 2017-2019 NXP.
> +# Copyright 2017-2020 NXP.
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -94,6 +94,8 @@ [LibraryClasses.common]
> NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
>
> + I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
> +
I think the changes to this file belong in 2/28.
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> diff --git a/Silicon/NXP/Include/Library/I2cLib.h b/Silicon/NXP/Include/Library/I2cLib.h
> new file mode 100644
> index 000000000000..e39237abd3ee
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/I2cLib.h
> @@ -0,0 +1,120 @@
> +/** @file
> + I2c Lib to control I2c controller.
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef I2C_LIB_H__
> +#define I2C_LIB_H__
> +
> +#include <Uefi.h>
> +#include <Pi/PiI2c.h>
> +
> +/**
> + software reset of the entire I2C module.
> + The module is reset and disabled.
> + Status register fields (IBSR) are cleared.
> +
> + @param[in] Base Base Address of I2c controller's registers
> +
> + @return EFI_SUCCESS successfuly reset the I2c module
> +**/
> +EFI_STATUS
> +I2cReset (
> + IN UINTN Base
> + );
> +
> +/**
> + Early init I2C for reading the sysclk from I2c slave device.
> + I2c bus clock is determined from the clock input to I2c controller.
> + The clock input to I2c controller is derived from the sysclk.
> + sysclk is determined by clock generator, which is controller by i2c.
> +
> + So, it's a chicken-egg problem to read the sysclk from clock generator.
> + To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
> + lowest value, in the hope that it won't be out of clock generator's supported
> + i2c clock frequency. Once we have the correct sysclk, we can setup the
> + correct i2c bus clock.
> +
> + @param[in] Base Base Address of I2c controller's registers
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> +**/
> +EFI_STATUS
> +I2cEarlyInitialize (
> + IN UINTN Base
> + );
> +
> +/**
> + Configure I2c bus to operate at a given speed
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] I2cBusClock Input clock to I2c controller
> + @param[in] Speed speed to be configured for I2c bus
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus
> +**/
> +EFI_STATUS
> +I2cInitialize (
> + IN UINTN Base,
> + IN UINT64 I2cBusClock,
> + IN UINT64 Speed
> + );
> +
> +/**
> + Transfer data to/from I2c slave device
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] SlaveAddress Slave Address from which data is to be read
> + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
> + describing the I2C transaction
> +
> + @return EFI_SUCCESS successfuly transfer the data
> + @return EFI_DEVICE_ERROR There was an error while transferring data through
> + I2c bus
> + @return EFI_NO_RESPONSE There was no Ack from i2c device
> + @return EFI_TIMEOUT I2c Bus is busy
> + @return EFI_NOT_READY I2c Bus Arbitration lost
> +**/
> +EFI_STATUS
> +I2cBusXfer (
> + IN UINTN Base,
> + IN UINT32 SlaveAddress,
> + IN EFI_I2C_REQUEST_PACKET *RequestPacket
> + );
> +
> +/**
> + Read a register from I2c slave device. This API is wrapper around I2cBusXfer
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] SlaveAddress Slave Address from which register value is
> + to be read
> + @param[in] RegAddress Register Address in Slave's memory map
> + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to
> + I2c Slave for simple reads without any
> + register, make this value = 0
> + (RegAddress is don't care in that case)
> + @param[out] RegValue Value to be read from I2c slave's regiser
> + @param[in] RegValueNumBytes Number of bytes to read from I2c slave
> + register
> +
> + @return EFI_SUCCESS successfuly read the registers
> + @return EFI_DEVICE_ERROR There was an error while transferring data through
> + I2c bus
> + @return EFI_NO_RESPONSE There was no Ack from i2c device
> + @return EFI_TIMEOUT I2c Bus is busy
> + @return EFI_NOT_READY I2c Bus Arbitration lost
> +**/
> +EFI_STATUS
> +I2cBusReadReg (
> + IN UINTN Base,
> + IN UINT32 SlaveAddress,
> + IN UINT64 RegAddress,
> + IN UINT8 RegAddressWidthInBytes,
> + OUT UINT8 *RegValue,
> + IN UINT32 RegValueNumBytes
> + );
> +
> +#endif // I2C_LIB_H__
> diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.c b/Silicon/NXP/Library/I2cLib/I2cLib.c
> new file mode 100644
> index 000000000000..08bf14c490be
> --- /dev/null
> +++ b/Silicon/NXP/Library/I2cLib/I2cLib.c
> @@ -0,0 +1,576 @@
> +/** @file
> + I2c Lib to control I2c controller.
> +
> + Copyright 2017, 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#include <Uefi.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/I2cLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/TimerLib.h>
> +
> +#include "I2cLibInternal.h"
> +
> +/**
> + I2C divisor and Ibfd register values when glitch filter is enabled
> +
> + In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
> + has been selected. A higher MUL value results in a lower sampling rate of
> + the I2C signals. This gives the I2C module greater immunity against glitches
> + in the I2C signals.
So this comment (and the subsequent one) have been cleaned up and no
longer refers to an SoC not yet upstream. But this has also removed
any reference to where these values come from.
Has NXP (including acquisitions) only ever produced one I2C
controller?
If there is no standalone name for the controller, can something be
said about the family of devices that contains it?
> +**/
> +STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchEnabled[] = {
> + { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 },
> + { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA },
> + { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 },
> + { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 },
> + { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A },
> + { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 },
> + { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 },
> + { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A },
> + { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 },
> + { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 },
> + { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 },
> + { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D },
> + { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 },
> + { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 },
> + { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC },
> + { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF },
> + { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 },
> + { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC },
> + { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF }
> +};
> +
> +/**
> + I2C divisor and Ibfd register values when glitch filter is disabled
> +
> + In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
> + has been selected. A higher MUL value results in a lower sampling rate of
> + the I2C signals. This gives the I2C module greater immunity against glitches
> + in the I2C signals.
> +**/
> +STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchDisabled[] = {
> + { 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 },
> + { 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 },
> + { 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 },
> + { 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 },
> + { 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 },
> + { 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 },
> + { 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B },
> + { 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 },
> + { 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 },
> + { 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 },
> + { 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C },
> + { 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F },
> + { 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 },
> + { 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC },
> + { 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF },
> + { 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 },
> + { 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC },
> + { 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF }
> +};
> +
> +/**
> + ERR009203 : I2C may not work reliably with the default setting
> +
> + Description : The clocking circuitry of I2C module may not work reliably due
> + to the slow rise time of SCL signal.
> + Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_EN]
> + to 1.
> +**/
> +STATIC
> +VOID
> +I2cErratumA009203 (
I'm still missing an explanation of why The function contains A009203
but the comment header describes ERR009203.
I suggested an addition to the file header comment, but can't see
anything there.
> + IN UINTN Base
> + )
> +{
> + I2C_REGS *Regs;
> +
> + Regs = (I2C_REGS *)Base;
> +
> + MmioOr8 ((UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN);
> +}
> +
> +/**
> + software reset of the entire I2C module.
> + The module is reset and disabled.
> + Status register fields (IBSR) are cleared.
> +
> + @param[in] Base Base Address of I2c controller's registers
> +
> + @return EFI_SUCCESS successfuly reset the I2c module
> +**/
> +EFI_STATUS
> +I2cReset (
> + IN UINTN Base
> + )
> +{
> + I2C_REGS *Regs;
> +
> + Regs = (I2C_REGS *)Base;
> +
> + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> + MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
> + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
> + MmioAnd8 ((UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Early init I2C for reading the sysclk from I2c slave device.
> + I2c bus clock is determined from the clock input to I2c controller.
> + The clock input to I2c controller is derived from the sysclk.
> + sysclk is determined by clock generator, which is controller by i2c.
> +
> + So, it's a chicken-egg problem to read the sysclk from clock generator.
> + To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
> + lowest value, in the hope that it won't be out of clock generator's supported
> + i2c clock frequency. Once we have the correct sysclk, we can setup the
> + correct i2c bus clock.
> +
> + @param[in] Base Base Address of I2c controller's registers
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> +**/
> +EFI_STATUS
> +I2cEarlyInitialize (
> + IN UINTN Base
> + )
> +{
> + I2C_REGS *Regs;
> + UINT8 Ibfd;
"Ibfd" is not more CamelCase compliant than "Ibc" is, and no more
descriptive. Please, if this is a term used in official NXP
documentation, add it to a glossary in the file header comment.
If not, please name it using camel case as something I can understand
what it is intended to be used for without already knowing.
... skims ahead ...
OK, so now it's "I2c Bus Frequency Dividor" (think that should be
Divider). Sure, that can be Ibfd *if* introduced in the file header
glossary, in *every* file that contains this abbreviation.
> +
> + Regs = (I2C_REGS *)Base;
> + if (FeaturePcdGet (PcdI2cErratumA009203)) {
> + I2cErratumA009203 (Base);
> + }
> +
> + if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
> + Ibfd = ARRAY_LAST_ELEM (mI2cClockDivisorGlitchEnabled).Ibfd;
> + } else {
> + Ibfd = ARRAY_LAST_ELEM (mI2cClockDivisorGlitchDisabled).Ibfd;
> + }
> +
> + MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
> +
> + I2cReset (Base);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Configure I2c bus to operate at a given speed
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] I2cBusClock Input clock to I2c controller
> + @param[in] Speed speed to be configured for I2c bus
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus
> +**/
> +EFI_STATUS
> +I2cInitialize (
> + IN UINTN Base,
> + IN UINT64 I2cBusClock,
> + IN UINT64 Speed
> + )
> +{
> + I2C_REGS *Regs;
> + UINT16 ClockDivisor;
> + UINT8 Ibfd; // I2c Bus Frequency Dividor Register
Introduction of non-standard abbreviations happen in the file header comment
block:
https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/v/release/2.20/5_source_files/52_spacing.html#5231-every-new-file-shall-begin-with-a-file-header-comment-block
> + CONST I2C_CLOCK_DIVISOR_PAIR *ClockDivisorPair;
> + UINT32 ClockDivisorPairSize;
> + UINT32 Index;
> +
> + Regs = (I2C_REGS *)Base;
> + if (FeaturePcdGet (PcdI2cErratumA009203)) {
> + I2cErratumA009203 (Base);
> + }
Is this erratum workaround intentionally invoked twice?
If so, the code could do with comments at all call sites explaining why.
I.e. "apply workaround before enabling controller", "re-apply
workaround after updating X", ...
> +
> + Ibfd = 0;
> + ClockDivisor = (I2cBusClock + Speed - 1) / Speed;
> +
> + if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
> + ClockDivisorPair = mI2cClockDivisorGlitchEnabled;
> + ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchEnabled);
> + } else {
> + ClockDivisorPair = mI2cClockDivisorGlitchDisabled;
> + ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchDisabled);
> + }
> +
> + if (ClockDivisor > ClockDivisorPair[ClockDivisorPairSize - 1].Divisor) {
> + Ibfd = ClockDivisorPair[ClockDivisorPairSize - 1].Ibfd;
> + } else {
> + for (Index = 0; Index < ClockDivisorPairSize; Index++) {
> + if (ClockDivisorPair[Index].Divisor >= ClockDivisor) {
> + Ibfd = ClockDivisorPair[Index].Ibfd;
> + break;
> + }
> + }
> + }
> +
> + MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
> +
> + I2cReset (Base);
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cBusTestBusBusy (
> + IN I2C_REGS *Regs,
> + IN BOOLEAN TestBusy
> + )
> +{
> + UINT32 Index;
> + UINT8 Reg;
> +
> + for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
> + Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
> +
> + if (Reg & I2C_IBSR_IBAL) {
> + MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
> + return EFI_NOT_READY;
> + }
> +
> + if (TestBusy && (Reg & I2C_IBSR_IBB)) {
> + break;
> + }
> +
> + if (!TestBusy && !(Reg & I2C_IBSR_IBB)) {
> + break;
> + }
> +
> + MicroSecondDelay (1);
> + }
> +
> + if (Index == I2C_NUM_RETRIES) {
> + return EFI_TIMEOUT;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cTransferComplete (
> + IN I2C_REGS *Regs,
> + IN BOOLEAN TestRxAck
> +)
> +{
> + UINT32 Index;
> + UINT8 Reg;
> +
> + for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
> + Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
> +
> + if (Reg & I2C_IBSR_IBIF) {
> + // Write 1 to clear the IBIF field
> + MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
> + break;
> + }
> +
> + MicroSecondDelay (1);
> + }
> +
> + if (Index == I2C_NUM_RETRIES) {
> + return EFI_TIMEOUT;
> + }
> +
> + if (TestRxAck && (Reg & I2C_IBSR_RXAK)) {
> + return EFI_NO_RESPONSE;
> + }
> +
> + if (Reg & I2C_IBSR_TCF) {
> + return EFI_SUCCESS;
> + }
> +
> + return EFI_DEVICE_ERROR;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cRead (
> + IN I2C_REGS *Regs,
> + IN UINT32 SlaveAddress,
> + IN EFI_I2C_OPERATION *Operation,
> + IN BOOLEAN IsLastOperation
> +)
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> +
> + // Write Slave Address
> + MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0);
> + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + // select Receive mode.
> + MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX);
> + if (Operation->LengthInBytes > 1) {
> + // Set No ACK = 0
> + MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_NOACK);
> + }
> +
> + // Perform a dummy read to initiate the receive operation.
> + MmioRead8 ((UINTN)&Regs->Ibdr);
> +
> + for (Index = 0; Index < Operation->LengthInBytes; Index++) {
> + Status = I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + if (Index == (Operation->LengthInBytes - 2)) {
> + // Set No ACK = 1
> + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_NOACK);
> + } else if (Index == (Operation->LengthInBytes - 1)) {
> + if (!IsLastOperation) {
> + // select Transmit mode (for repeat start)
> + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_TXRX);
> + } else {
> + // Generate Stop Signal
> + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + }
> + }
> + Operation->Buffer[Index] = MmioRead8 ((UINTN)&Regs->Ibdr);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cWrite (
> + IN I2C_REGS *Regs,
> + IN UINT32 SlaveAddress,
> + IN EFI_I2C_OPERATION *Operation
> +)
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> +
> + // Write Slave Address
> + MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) & (UINT8)(~BIT0));
> + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + // Write Data
> + for (Index = 0; Index < Operation->LengthInBytes; Index++) {
> + MmioWrite8 ((UINTN)&Regs->Ibdr, Operation->Buffer[Index]);
> + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cStop (
> + IN I2C_REGS *Regs
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Reg;
> +
> + Status = EFI_SUCCESS;
> + Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
> + if (Reg & I2C_IBSR_IBB) {
> + // Generate Stop Signal
> + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + }
> +
> + // Disable I2c Controller
> + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> +
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cStart (
> + IN I2C_REGS *Regs
> + )
> +{
> + EFI_STATUS Status;
> +
> + MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
> + MmioAnd8 ((UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS));
> +
> + //Wait controller to be stable
> + MicroSecondDelay (1);
> +
> + // Generate Start Signal
> + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MSSL);
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + // Select Transmit Mode. set No ACK = 1
> + MmioOr8 ((UINTN)&Regs->Ibcr, (I2C_IBCR_TXRX | I2C_IBCR_NOACK));
> +
> + return Status;
> +}
> +
> +/**
> + Transfer data to/from I2c slave device
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] SlaveAddress Slave Address from which data is to be read
> + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
> + describing the I2C transaction
> +
> + @return EFI_SUCCESS successfuly transfer the data
> + @return EFI_DEVICE_ERROR There was an error while transferring data through
> + I2c bus
> + @return EFI_NO_RESPONSE There was no Ack from i2c device
> + @return EFI_TIMEOUT I2c Bus is busy
> + @return EFI_NOT_READY I2c Bus Arbitration lost
> +**/
> +EFI_STATUS
> +I2cBusXfer (
> + IN UINTN Base,
> + IN UINT32 SlaveAddress,
> + IN EFI_I2C_REQUEST_PACKET *RequestPacket
> + )
> +{
> + UINTN Index;
> + I2C_REGS *Regs;
> + EFI_I2C_OPERATION *Operation;
> + EFI_STATUS Status;
> + BOOLEAN IsLastOperation;
> +
> + Regs = (I2C_REGS *)Base;
> + IsLastOperation = FALSE;
> +
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> + if (EFI_ERROR (Status)) {
> + goto ErrorExit;
> + }
> +
> + Status = I2cStart (Regs);
> + if (EFI_ERROR (Status)) {
> + goto ErrorExit;
> + }
> +
> + for (Index = 0, Operation = RequestPacket->Operation;
> + Index < RequestPacket->OperationCount;
> + Index++, Operation++) {
> + if (Index == (RequestPacket->OperationCount - 1)) {
> + IsLastOperation = TRUE;
> + }
> + // Send repeat start after first transmit/recieve
> + if (Index) {
> + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_RSTA);
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
> + if (EFI_ERROR (Status)) {
> + goto ErrorExit;
> + }
> + }
> + // Read/write data
> + if (Operation->Flags & I2C_FLAG_READ) {
> + Status = I2cRead (Regs, SlaveAddress, Operation, IsLastOperation);
> + } else {
> + Status = I2cWrite (Regs, SlaveAddress, Operation);
> + }
> + if (EFI_ERROR (Status)) {
> + goto ErrorExit;
> + }
> + }
> +
> +ErrorExit:
> +
> + I2cStop (Regs);
> +
> + return Status;
> +}
> +
> +/**
> + Read a register from I2c slave device. This API is wrapper around I2cBusXfer
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] SlaveAddress Slave Address from which register value is
> + to be read
> + @param[in] RegAddress Register Address in Slave's memory map
> + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to
> + I2c Slave for simple reads without any
> + register, make this value = 0
> + (RegAddress is don't care in that case)
> + @param[out] RegValue Value to be read from I2c slave's regiser
> + @param[in] RegValueNumBytes Number of bytes to read from I2c slave
> + register
> +
> + @return EFI_SUCCESS successfuly read the registers
> + @return EFI_DEVICE_ERROR There was an error while transferring data through
> + I2c bus
> + @return EFI_NO_RESPONSE There was no Ack from i2c device
> + @return EFI_TIMEOUT I2c Bus is busy
> + @return EFI_NOT_READY I2c Bus Arbitration lost
> +**/
> +EFI_STATUS
> +I2cBusReadReg (
> + IN UINTN Base,
> + IN UINT32 SlaveAddress,
> + IN UINT64 RegAddress,
> + IN UINT8 RegAddressWidthInBytes,
> + OUT UINT8 *RegValue,
> + IN UINT32 RegValueNumBytes
> + )
> +{
> + EFI_I2C_OPERATION *Operations;
> + I2C_REG_REQUEST RequestPacket;
> + UINTN OperationCount;
> + UINT8 Address[sizeof (RegAddress)];
> + UINT8 *PtrAddress;
This is too close to hungarian notation - AddressPtr works better.
/
Leif
> + EFI_STATUS Status;
> +
> + ZeroMem (&RequestPacket, sizeof (RequestPacket));
> + OperationCount = 0;
> + Operations = RequestPacket.Operation;
> + PtrAddress = Address;
> +
> + if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (RegAddressWidthInBytes != 0) {
> + Operations[OperationCount].LengthInBytes = RegAddressWidthInBytes;
> + Operations[OperationCount].Buffer = PtrAddress;
> + while (RegAddressWidthInBytes--) {
> + *PtrAddress++ = RegAddress >> (8 * RegAddressWidthInBytes);
> + }
> + OperationCount++;
> + }
> +
> + Operations[OperationCount].LengthInBytes = RegValueNumBytes;
> + Operations[OperationCount].Buffer = RegValue;
> + Operations[OperationCount].Flags = I2C_FLAG_READ;
> + OperationCount++;
> +
> + RequestPacket.OperationCount = OperationCount;
> +
> + Status = I2cBusXfer (
> + Base, SlaveAddress,
> + (EFI_I2C_REQUEST_PACKET *)&RequestPacket
> + );
> +
> + return Status;
> +}
> +
> diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.inf b/Silicon/NXP/Library/I2cLib/I2cLib.inf
> new file mode 100644
> index 000000000000..b9bd79ac1ef1
> --- /dev/null
> +++ b/Silicon/NXP/Library/I2cLib/I2cLib.inf
> @@ -0,0 +1,31 @@
> +# @file
> +#
> +# Component description file for I2cLib module
> +# Copyright 2017, 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = I2cLib
> + FILE_GUID = 8ecefc8f-a2c4-4091-b81f-20f7aeb0567f
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = I2cLib
> +
> +[Sources.common]
> + I2cLib.c
> +
> +[LibraryClasses]
> + IoLib
> + TimerLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[FeaturePcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203
> +
> diff --git a/Silicon/NXP/Library/I2cLib/I2cLibInternal.h b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> new file mode 100644
> index 000000000000..2ca4a3639d2c
> --- /dev/null
> +++ b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> @@ -0,0 +1,105 @@
> +/** @file
> + I2c Lib to control I2c controller.
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef I2C_LIB_INTERNAL_H__
> +#define I2C_LIB_INTERNAL_H__
> +
> +#include <Pi/PiI2c.h>
> +#include <Uefi.h>
> +
> +/** Module Disable
> + 0b - The module is enabled. You must clear this field before any other IBCR
> + fields have any effect.
> + 1b - The module is reset and disabled. This is the power-on reset situation.
> + When high, the interface is held in reset, but registers can still be
> + accessed. Status register fields (IBSR) are not valid when the module
> + is disabled.
> +**/
> +#define I2C_IBCR_MDIS BIT7
> +// I2c Bus Interrupt Enable
> +#define I2C_IBCR_IBIE BIT6
> +/** Master / Slave Mode 0b - Slave mode 1b - Master mode
> + When you change this field from 0 to 1, the module generates a START signal
> + on the bus and selects the master mode. When you change this field from 1 to
> + 0, the module generates a STOP signal and changes the operation mode from
> + master to slave. You should generate a STOP signal only if IBSR[IBIF]=1.
> + The module clears this field without generating a STOP signal when the
> + master loses arbitration.
> +*/
> +#define I2C_IBCR_MSSL BIT5
> +// 0b - Receive 1b - Transmit
> +#define I2C_IBCR_TXRX BIT4
> +/** Data acknowledge disable
> + Values written to this field are only used when the I2C module is a receiver,
> + not a transmitter.
> + 0b - The module sends an acknowledge signal to the bus at the 9th clock bit
> + after receiving one byte of data.
> + 1b - The module does not send an acknowledge-signal response (that is,
> + acknowledge bit = 1).
> +**/
> +#define I2C_IBCR_NOACK BIT3
> +/**Repeat START
> + If the I2C module is the current bus master, and you program RSTA=1, the I2C
> + module generates a repeated START condition. This field always reads as a 0.
> + If you attempt a repeated START at the wrong time, if the bus is owned by
> + another master the result is loss of arbitration.
> +**/
> +#define I2C_IBCR_RSTA BIT2
> +// DMA enable
> +#define I2C_IBCR_DMAEN BIT1
> +
> +// Transfer Complete
> +#define I2C_IBSR_TCF BIT7
> +// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy
> +#define I2C_IBSR_IBB BIT5
> +// Arbitration Lost. software must clear this field by writing a one to it.
> +#define I2C_IBSR_IBAL BIT4
> +// I2C bus interrupt flag
> +#define I2C_IBSR_IBIF BIT1
> +// Received acknowledge 0b - Acknowledge received 1b - No acknowledge received
> +#define I2C_IBSR_RXAK BIT0
> +
> +//Bus idle interrupt enable
> +#define I2C_IBIC_BIIE BIT7
> +
> +// Glitch filter enable
> +#define I2C_IBDBG_GLFLT_EN BIT3
> +
> +#define I2C_BUS_TEST_BUSY TRUE
> +#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY
> +#define I2C_BUS_TEST_RX_ACK TRUE
> +#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK
> +
> +#define ARRAY_LAST_ELEM(x) (x)[ARRAY_SIZE (x) - 1]
> +#define I2C_NUM_RETRIES 500
> +
> +typedef struct _I2C_REGS {
> + UINT8 Ibad; // I2c Bus Address Register
> + UINT8 Ibfd; // I2c Bus Frequency Dividor Register
> + UINT8 Ibcr; // I2c Bus Control Register
> + UINT8 Ibsr; // I2c Bus Status Register
> + UINT8 Ibdr; // I2C Bus Data I/O Register
> + UINT8 Ibic; // I2C Bus Interrupt Config Register
> + UINT8 Ibdbg; // I2C Bus Debug Register
> +} I2C_REGS;
> +
> +/*
> + * sorted list of clock divisor, Ibfd register value pairs
> + */
> +typedef struct _I2C_CLOCK_DIVISOR_PAIR {
> + UINT16 Divisor;
> + UINT16 Ibfd; // I2c Bus Frequency Dividor Register value
> +} I2C_CLOCK_DIVISOR_PAIR;
> +
> +typedef struct {
> + UINTN OperationCount;
> + EFI_I2C_OPERATION Operation[2];
> +} I2C_REG_REQUEST;
> +
> +#endif // I2C_LIB_INTERNAL_H__
> +
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 764b9bb0e2d3..4a1cfb3e278e 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -1,6 +1,6 @@
> # @file.
> #
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -13,6 +13,10 @@ [Defines]
> [Includes]
> Include
>
> +[LibraryClasses]
> + ## @libraryclass Provides services to read/write to I2c devices
> + I2cLib|Include/Library/I2cLib.h
> +
> [Guids.common]
> gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
> @@ -101,3 +105,7 @@ [PcdsFixedAtBuild.common]
> gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
> gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> +
> +[PcdsFeatureFlag]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> +
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib
2020-03-31 11:51 ` Leif Lindholm
@ 2020-04-06 6:14 ` Pankaj Bansal
2020-04-06 11:12 ` Leif Lindholm
0 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-06 6:14 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Tuesday, March 31, 2020 5:21 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib
>
> On Fri, Mar 20, 2020 at 20:05:16 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > I2c lib is going to be used in PrePeiCore sec module to get the
> > System clock information from devices connected to i2c (like fpga
> > or clock generator)
> >
> > since we don't have support of DXE modules this early in boot stage,
> > move the i2c controller functionality in library.
>
> This isn't moving the functionality to a library though - it is moving
> the functionality to a library *and* adding new features. These are
> two separate changes that should be two separate patches.
>
> The content in this patch is mostly fine as the end result (but some
> comments below).
>
> I suggest this patch is reordered with 2/28 and all of the splitting
> out part takes place in that patch. This patch can then be reduced to
> ... the bits that are currently impossible to see are changed (at
> least the glitch fixing).
Actually the I2cLib is not some bug fix over I2cDxe.
The I2cLib has been completely re-written.
This is because, I2cDxe was written assuming that the I2c transaction would
always be of (reg + data) type only (i.e. two operations) .
And also the Repeat start condition was not generated In the I2cDxe driver.
This caused the I2c Peripheral drivers which were written keeping the controller driver
In mind to issue two operations. Which caused bug in Pcf2129 RTC driver, that I am fixing in patch 3.
Now I have removed these assumptions as well as added Repeat start between successive operations, which
Comply with PI I2c spec.
So, it would be difficult for me to merge the 1 and 2.
>
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > Platform/NXP/NxpQoriqLs.dsc.inc | 4 +-
> > Silicon/NXP/Include/Library/I2cLib.h | 120 ++++
> > Silicon/NXP/Library/I2cLib/I2cLib.c | 576 ++++++++++++++++++++
> > Silicon/NXP/Library/I2cLib/I2cLib.inf | 31 ++
> > Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 105 ++++
> > Silicon/NXP/NxpQoriqLs.dec | 10 +-
> > 6 files changed, 844 insertions(+), 2 deletions(-)
> > create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
> > create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
> > create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
> > create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> >
> > diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc
> b/Platform/NXP/NxpQoriqLs.dsc.inc
> > index fa5f30dd3909..b28e0615f7ca 100644
> > --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> > +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> > @@ -1,6 +1,6 @@
> > # @file
> > #
> > -# Copyright 2017-2019 NXP.
> > +# Copyright 2017-2020 NXP.
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > #
> > @@ -94,6 +94,8 @@ [LibraryClasses.common]
> >
> NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl
> eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
> >
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRep
> ortStatusCodeLib.inf
> >
> > + I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
> > +
>
> I think the changes to this file belong in 2/28.
This I can add to 2/28
>
> > [LibraryClasses.common.SEC]
> > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> >
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
> ressLib.inf
> > diff --git a/Silicon/NXP/Include/Library/I2cLib.h
> b/Silicon/NXP/Include/Library/I2cLib.h
> > new file mode 100644
> > index 000000000000..e39237abd3ee
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Library/I2cLib.h
> > @@ -0,0 +1,120 @@
> > +/** @file
> > + I2c Lib to control I2c controller.
> > +
> > + Copyright 2020 NXP
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef I2C_LIB_H__
> > +#define I2C_LIB_H__
> > +
> > +#include <Uefi.h>
> > +#include <Pi/PiI2c.h>
> > +
> > +/**
> > + software reset of the entire I2C module.
> > + The module is reset and disabled.
> > + Status register fields (IBSR) are cleared.
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > +
> > + @return EFI_SUCCESS successfuly reset the I2c module
> > +**/
> > +EFI_STATUS
> > +I2cReset (
> > + IN UINTN Base
> > + );
> > +
> > +/**
> > + Early init I2C for reading the sysclk from I2c slave device.
> > + I2c bus clock is determined from the clock input to I2c controller.
> > + The clock input to I2c controller is derived from the sysclk.
> > + sysclk is determined by clock generator, which is controller by i2c.
> > +
> > + So, it's a chicken-egg problem to read the sysclk from clock generator.
> > + To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
> > + lowest value, in the hope that it won't be out of clock generator's supported
> > + i2c clock frequency. Once we have the correct sysclk, we can setup the
> > + correct i2c bus clock.
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > +
> > + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> > +**/
> > +EFI_STATUS
> > +I2cEarlyInitialize (
> > + IN UINTN Base
> > + );
> > +
> > +/**
> > + Configure I2c bus to operate at a given speed
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] I2cBusClock Input clock to I2c controller
> > + @param[in] Speed speed to be configured for I2c bus
> > +
> > + @return EFI_SUCCESS successfuly setup the i2c bus
> > +**/
> > +EFI_STATUS
> > +I2cInitialize (
> > + IN UINTN Base,
> > + IN UINT64 I2cBusClock,
> > + IN UINT64 Speed
> > + );
> > +
> > +/**
> > + Transfer data to/from I2c slave device
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] SlaveAddress Slave Address from which data is to be read
> > + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET
> structure
> > + describing the I2C transaction
> > +
> > + @return EFI_SUCCESS successfuly transfer the data
> > + @return EFI_DEVICE_ERROR There was an error while transferring data
> through
> > + I2c bus
> > + @return EFI_NO_RESPONSE There was no Ack from i2c device
> > + @return EFI_TIMEOUT I2c Bus is busy
> > + @return EFI_NOT_READY I2c Bus Arbitration lost
> > +**/
> > +EFI_STATUS
> > +I2cBusXfer (
> > + IN UINTN Base,
> > + IN UINT32 SlaveAddress,
> > + IN EFI_I2C_REQUEST_PACKET *RequestPacket
> > + );
> > +
> > +/**
> > + Read a register from I2c slave device. This API is wrapper around I2cBusXfer
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] SlaveAddress Slave Address from which register value is
> > + to be read
> > + @param[in] RegAddress Register Address in Slave's memory map
> > + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to
> send to
> > + I2c Slave for simple reads without any
> > + register, make this value = 0
> > + (RegAddress is don't care in that case)
> > + @param[out] RegValue Value to be read from I2c slave's regiser
> > + @param[in] RegValueNumBytes Number of bytes to read from I2c slave
> > + register
> > +
> > + @return EFI_SUCCESS successfuly read the registers
> > + @return EFI_DEVICE_ERROR There was an error while transferring data
> through
> > + I2c bus
> > + @return EFI_NO_RESPONSE There was no Ack from i2c device
> > + @return EFI_TIMEOUT I2c Bus is busy
> > + @return EFI_NOT_READY I2c Bus Arbitration lost
> > +**/
> > +EFI_STATUS
> > +I2cBusReadReg (
> > + IN UINTN Base,
> > + IN UINT32 SlaveAddress,
> > + IN UINT64 RegAddress,
> > + IN UINT8 RegAddressWidthInBytes,
> > + OUT UINT8 *RegValue,
> > + IN UINT32 RegValueNumBytes
> > + );
> > +
> > +#endif // I2C_LIB_H__
> > diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.c
> b/Silicon/NXP/Library/I2cLib/I2cLib.c
> > new file mode 100644
> > index 000000000000..08bf14c490be
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/I2cLib/I2cLib.c
> > @@ -0,0 +1,576 @@
> > +/** @file
> > + I2c Lib to control I2c controller.
> > +
> > + Copyright 2017, 2020 NXP
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#include <Uefi.h>
> > +#include <Library/BaseMemoryLib.h>
> > +#include <Library/I2cLib.h>
> > +#include <Library/IoLib.h>
> > +#include <Library/TimerLib.h>
> > +
> > +#include "I2cLibInternal.h"
> > +
> > +/**
> > + I2C divisor and Ibfd register values when glitch filter is enabled
> > +
> > + In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
> > + has been selected. A higher MUL value results in a lower sampling rate of
> > + the I2C signals. This gives the I2C module greater immunity against glitches
> > + in the I2C signals.
>
> So this comment (and the subsequent one) have been cleaned up and no
> longer refers to an SoC not yet upstream. But this has also removed
> any reference to where these values come from.
>
> Has NXP (including acquisitions) only ever produced one I2C
> controller?
> If there is no standalone name for the controller, can something be
> said about the family of devices that contains it?
I don't know if this is the only I2c IP that we have ever used.
I asked around and I could not get any definite answer to this question.
However, I will add the name of NXP QoriQ Layerscape family of SOCs in comment.
>
> > +**/
> > +STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchEnabled[] =
> {
> > + { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 },
> > + { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA },
> > + { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 },
> > + { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 },
> > + { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A },
> > + { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 },
> > + { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 },
> > + { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A },
> > + { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 },
> > + { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 },
> > + { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 },
> > + { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D },
> > + { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 },
> > + { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 },
> > + { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC },
> > + { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF },
> > + { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 },
> > + { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC },
> > + { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF }
> > +};
> > +
> > +/**
> > + I2C divisor and Ibfd register values when glitch filter is disabled
> > +
> > + In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
> > + has been selected. A higher MUL value results in a lower sampling rate of
> > + the I2C signals. This gives the I2C module greater immunity against glitches
> > + in the I2C signals.
> > +**/
> > +STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchDisabled[] =
> {
> > + { 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 },
> > + { 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 },
> > + { 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 },
> > + { 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 },
> > + { 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 },
> > + { 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 },
> > + { 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B },
> > + { 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 },
> > + { 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 },
> > + { 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 },
> > + { 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C },
> > + { 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F },
> > + { 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 },
> > + { 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC },
> > + { 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF },
> > + { 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 },
> > + { 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC },
> > + { 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF }
> > +};
> > +
> > +/**
> > + ERR009203 : I2C may not work reliably with the default setting
> > +
> > + Description : The clocking circuitry of I2C module may not work reliably due
> > + to the slow rise time of SCL signal.
> > + Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_EN]
> > + to 1.
> > +**/
> > +STATIC
> > +VOID
> > +I2cErratumA009203 (
>
> I'm still missing an explanation of why The function contains A009203
> but the comment header describes ERR009203.
> I suggested an addition to the file header comment, but can't see
> anything there.
The Errata in NXP design database are numbered as ERRXXXXX, while in software database
the errata are numbered as AXXXXX.
I asked around and I could only get that this is the convention that we have followed everywhere.
I will change the ERRXXXXX to AXXXXX.
The errata document that mentions this errata is not published in public domain.
However, I can give the link to other software in which this same errata has been added like:
https://elixir.bootlin.com/u-boot/latest/source/arch/arm/cpu/armv8/fsl-layerscape/soc.c#L283
>
> > + IN UINTN Base
> > + )
> > +{
> > + I2C_REGS *Regs;
> > +
> > + Regs = (I2C_REGS *)Base;
> > +
> > + MmioOr8 ((UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN);
> > +}
> > +
> > +/**
> > + software reset of the entire I2C module.
> > + The module is reset and disabled.
> > + Status register fields (IBSR) are cleared.
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > +
> > + @return EFI_SUCCESS successfuly reset the I2c module
> > +**/
> > +EFI_STATUS
> > +I2cReset (
> > + IN UINTN Base
> > + )
> > +{
> > + I2C_REGS *Regs;
> > +
> > + Regs = (I2C_REGS *)Base;
> > +
> > + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> > + MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
> > + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
> > + MmioAnd8 ((UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Early init I2C for reading the sysclk from I2c slave device.
> > + I2c bus clock is determined from the clock input to I2c controller.
> > + The clock input to I2c controller is derived from the sysclk.
> > + sysclk is determined by clock generator, which is controller by i2c.
> > +
> > + So, it's a chicken-egg problem to read the sysclk from clock generator.
> > + To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
> > + lowest value, in the hope that it won't be out of clock generator's supported
> > + i2c clock frequency. Once we have the correct sysclk, we can setup the
> > + correct i2c bus clock.
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > +
> > + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> > +**/
> > +EFI_STATUS
> > +I2cEarlyInitialize (
> > + IN UINTN Base
> > + )
> > +{
> > + I2C_REGS *Regs;
> > + UINT8 Ibfd;
>
> "Ibfd" is not more CamelCase compliant than "Ibc" is, and no more
> descriptive. Please, if this is a term used in official NXP
> documentation, add it to a glossary in the file header comment.
> If not, please name it using camel case as something I can understand
> what it is intended to be used for without already knowing.
Ok, I will add the abbreviations used in file header
>
> ... skims ahead ...
>
> OK, so now it's "I2c Bus Frequency Dividor" (think that should be
> Divider). Sure, that can be Ibfd *if* introduced in the file header
> glossary, in *every* file that contains this abbreviation.
>
Ok, I will add the abbreviations used in file header
> > +
> > + Regs = (I2C_REGS *)Base;
> > + if (FeaturePcdGet (PcdI2cErratumA009203)) {
> > + I2cErratumA009203 (Base);
> > + }
> > +
> > + if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
> > + Ibfd = ARRAY_LAST_ELEM (mI2cClockDivisorGlitchEnabled).Ibfd;
> > + } else {
> > + Ibfd = ARRAY_LAST_ELEM (mI2cClockDivisorGlitchDisabled).Ibfd;
> > + }
> > +
> > + MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
> > +
> > + I2cReset (Base);
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Configure I2c bus to operate at a given speed
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] I2cBusClock Input clock to I2c controller
> > + @param[in] Speed speed to be configured for I2c bus
> > +
> > + @return EFI_SUCCESS successfuly setup the i2c bus
> > +**/
> > +EFI_STATUS
> > +I2cInitialize (
> > + IN UINTN Base,
> > + IN UINT64 I2cBusClock,
> > + IN UINT64 Speed
> > + )
> > +{
> > + I2C_REGS *Regs;
> > + UINT16 ClockDivisor;
> > + UINT8 Ibfd; // I2c Bus Frequency Dividor Register
>
> Introduction of non-standard abbreviations happen in the file header comment
> block:
> https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-
> specification/content/v/release/2.20/5_source_files/52_spacing.html#5231-
> every-new-file-shall-begin-with-a-file-header-comment-block
Ok, I will add the abbreviations used in file header
>
> > + CONST I2C_CLOCK_DIVISOR_PAIR *ClockDivisorPair;
> > + UINT32 ClockDivisorPairSize;
> > + UINT32 Index;
> > +
> > + Regs = (I2C_REGS *)Base;
> > + if (FeaturePcdGet (PcdI2cErratumA009203)) {
> > + I2cErratumA009203 (Base);
> > + }
>
> Is this erratum workaround intentionally invoked twice?
> If so, the code could do with comments at all call sites explaining why.
> I.e. "apply workaround before enabling controller", "re-apply
> workaround after updating X", ...
Ok I will add the comments at call sites.
>
> > +
> > + Ibfd = 0;
> > + ClockDivisor = (I2cBusClock + Speed - 1) / Speed;
> > +
> > + if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
> > + ClockDivisorPair = mI2cClockDivisorGlitchEnabled;
> > + ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchEnabled);
> > + } else {
> > + ClockDivisorPair = mI2cClockDivisorGlitchDisabled;
> > + ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchDisabled);
> > + }
> > +
> > + if (ClockDivisor > ClockDivisorPair[ClockDivisorPairSize - 1].Divisor) {
> > + Ibfd = ClockDivisorPair[ClockDivisorPairSize - 1].Ibfd;
> > + } else {
> > + for (Index = 0; Index < ClockDivisorPairSize; Index++) {
> > + if (ClockDivisorPair[Index].Divisor >= ClockDivisor) {
> > + Ibfd = ClockDivisorPair[Index].Ibfd;
> > + break;
> > + }
> > + }
> > + }
> > +
> > + MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
> > +
> > + I2cReset (Base);
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cBusTestBusBusy (
> > + IN I2C_REGS *Regs,
> > + IN BOOLEAN TestBusy
> > + )
> > +{
> > + UINT32 Index;
> > + UINT8 Reg;
> > +
> > + for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
> > + Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
> > +
> > + if (Reg & I2C_IBSR_IBAL) {
> > + MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
> > + return EFI_NOT_READY;
> > + }
> > +
> > + if (TestBusy && (Reg & I2C_IBSR_IBB)) {
> > + break;
> > + }
> > +
> > + if (!TestBusy && !(Reg & I2C_IBSR_IBB)) {
> > + break;
> > + }
> > +
> > + MicroSecondDelay (1);
> > + }
> > +
> > + if (Index == I2C_NUM_RETRIES) {
> > + return EFI_TIMEOUT;
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cTransferComplete (
> > + IN I2C_REGS *Regs,
> > + IN BOOLEAN TestRxAck
> > +)
> > +{
> > + UINT32 Index;
> > + UINT8 Reg;
> > +
> > + for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
> > + Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
> > +
> > + if (Reg & I2C_IBSR_IBIF) {
> > + // Write 1 to clear the IBIF field
> > + MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
> > + break;
> > + }
> > +
> > + MicroSecondDelay (1);
> > + }
> > +
> > + if (Index == I2C_NUM_RETRIES) {
> > + return EFI_TIMEOUT;
> > + }
> > +
> > + if (TestRxAck && (Reg & I2C_IBSR_RXAK)) {
> > + return EFI_NO_RESPONSE;
> > + }
> > +
> > + if (Reg & I2C_IBSR_TCF) {
> > + return EFI_SUCCESS;
> > + }
> > +
> > + return EFI_DEVICE_ERROR;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cRead (
> > + IN I2C_REGS *Regs,
> > + IN UINT32 SlaveAddress,
> > + IN EFI_I2C_OPERATION *Operation,
> > + IN BOOLEAN IsLastOperation
> > +)
> > +{
> > + EFI_STATUS Status;
> > + UINTN Index;
> > +
> > + // Write Slave Address
> > + MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0);
> > + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + // select Receive mode.
> > + MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX);
> > + if (Operation->LengthInBytes > 1) {
> > + // Set No ACK = 0
> > + MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_NOACK);
> > + }
> > +
> > + // Perform a dummy read to initiate the receive operation.
> > + MmioRead8 ((UINTN)&Regs->Ibdr);
> > +
> > + for (Index = 0; Index < Operation->LengthInBytes; Index++) {
> > + Status = I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + if (Index == (Operation->LengthInBytes - 2)) {
> > + // Set No ACK = 1
> > + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_NOACK);
> > + } else if (Index == (Operation->LengthInBytes - 1)) {
> > + if (!IsLastOperation) {
> > + // select Transmit mode (for repeat start)
> > + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_TXRX);
> > + } else {
> > + // Generate Stop Signal
> > + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + }
> > + }
> > + Operation->Buffer[Index] = MmioRead8 ((UINTN)&Regs->Ibdr);
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cWrite (
> > + IN I2C_REGS *Regs,
> > + IN UINT32 SlaveAddress,
> > + IN EFI_I2C_OPERATION *Operation
> > +)
> > +{
> > + EFI_STATUS Status;
> > + UINTN Index;
> > +
> > + // Write Slave Address
> > + MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) &
> (UINT8)(~BIT0));
> > + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + // Write Data
> > + for (Index = 0; Index < Operation->LengthInBytes; Index++) {
> > + MmioWrite8 ((UINTN)&Regs->Ibdr, Operation->Buffer[Index]);
> > + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + }
> > + return EFI_SUCCESS;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cStop (
> > + IN I2C_REGS *Regs
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT8 Reg;
> > +
> > + Status = EFI_SUCCESS;
> > + Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
> > + if (Reg & I2C_IBSR_IBB) {
> > + // Generate Stop Signal
> > + MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + }
> > +
> > + // Disable I2c Controller
> > + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> > +
> > + return Status;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cStart (
> > + IN I2C_REGS *Regs
> > + )
> > +{
> > + EFI_STATUS Status;
> > +
> > + MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
> > + MmioAnd8 ((UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS));
> > +
> > + //Wait controller to be stable
> > + MicroSecondDelay (1);
> > +
> > + // Generate Start Signal
> > + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MSSL);
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + // Select Transmit Mode. set No ACK = 1
> > + MmioOr8 ((UINTN)&Regs->Ibcr, (I2C_IBCR_TXRX | I2C_IBCR_NOACK));
> > +
> > + return Status;
> > +}
> > +
> > +/**
> > + Transfer data to/from I2c slave device
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] SlaveAddress Slave Address from which data is to be read
> > + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET
> structure
> > + describing the I2C transaction
> > +
> > + @return EFI_SUCCESS successfuly transfer the data
> > + @return EFI_DEVICE_ERROR There was an error while transferring data
> through
> > + I2c bus
> > + @return EFI_NO_RESPONSE There was no Ack from i2c device
> > + @return EFI_TIMEOUT I2c Bus is busy
> > + @return EFI_NOT_READY I2c Bus Arbitration lost
> > +**/
> > +EFI_STATUS
> > +I2cBusXfer (
> > + IN UINTN Base,
> > + IN UINT32 SlaveAddress,
> > + IN EFI_I2C_REQUEST_PACKET *RequestPacket
> > + )
> > +{
> > + UINTN Index;
> > + I2C_REGS *Regs;
> > + EFI_I2C_OPERATION *Operation;
> > + EFI_STATUS Status;
> > + BOOLEAN IsLastOperation;
> > +
> > + Regs = (I2C_REGS *)Base;
> > + IsLastOperation = FALSE;
> > +
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> > + if (EFI_ERROR (Status)) {
> > + goto ErrorExit;
> > + }
> > +
> > + Status = I2cStart (Regs);
> > + if (EFI_ERROR (Status)) {
> > + goto ErrorExit;
> > + }
> > +
> > + for (Index = 0, Operation = RequestPacket->Operation;
> > + Index < RequestPacket->OperationCount;
> > + Index++, Operation++) {
> > + if (Index == (RequestPacket->OperationCount - 1)) {
> > + IsLastOperation = TRUE;
> > + }
> > + // Send repeat start after first transmit/recieve
> > + if (Index) {
> > + MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_RSTA);
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
> > + if (EFI_ERROR (Status)) {
> > + goto ErrorExit;
> > + }
> > + }
> > + // Read/write data
> > + if (Operation->Flags & I2C_FLAG_READ) {
> > + Status = I2cRead (Regs, SlaveAddress, Operation, IsLastOperation);
> > + } else {
> > + Status = I2cWrite (Regs, SlaveAddress, Operation);
> > + }
> > + if (EFI_ERROR (Status)) {
> > + goto ErrorExit;
> > + }
> > + }
> > +
> > +ErrorExit:
> > +
> > + I2cStop (Regs);
> > +
> > + return Status;
> > +}
> > +
> > +/**
> > + Read a register from I2c slave device. This API is wrapper around I2cBusXfer
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] SlaveAddress Slave Address from which register value is
> > + to be read
> > + @param[in] RegAddress Register Address in Slave's memory map
> > + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to
> send to
> > + I2c Slave for simple reads without any
> > + register, make this value = 0
> > + (RegAddress is don't care in that case)
> > + @param[out] RegValue Value to be read from I2c slave's regiser
> > + @param[in] RegValueNumBytes Number of bytes to read from I2c slave
> > + register
> > +
> > + @return EFI_SUCCESS successfuly read the registers
> > + @return EFI_DEVICE_ERROR There was an error while transferring data
> through
> > + I2c bus
> > + @return EFI_NO_RESPONSE There was no Ack from i2c device
> > + @return EFI_TIMEOUT I2c Bus is busy
> > + @return EFI_NOT_READY I2c Bus Arbitration lost
> > +**/
> > +EFI_STATUS
> > +I2cBusReadReg (
> > + IN UINTN Base,
> > + IN UINT32 SlaveAddress,
> > + IN UINT64 RegAddress,
> > + IN UINT8 RegAddressWidthInBytes,
> > + OUT UINT8 *RegValue,
> > + IN UINT32 RegValueNumBytes
> > + )
> > +{
> > + EFI_I2C_OPERATION *Operations;
> > + I2C_REG_REQUEST RequestPacket;
> > + UINTN OperationCount;
> > + UINT8 Address[sizeof (RegAddress)];
> > + UINT8 *PtrAddress;
>
> This is too close to hungarian notation - AddressPtr works better.
Ok. I will change it.
>
> /
> Leif
>
> > + EFI_STATUS Status;
> > +
> > + ZeroMem (&RequestPacket, sizeof (RequestPacket));
> > + OperationCount = 0;
> > + Operations = RequestPacket.Operation;
> > + PtrAddress = Address;
> > +
> > + if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if (RegAddressWidthInBytes != 0) {
> > + Operations[OperationCount].LengthInBytes = RegAddressWidthInBytes;
> > + Operations[OperationCount].Buffer = PtrAddress;
> > + while (RegAddressWidthInBytes--) {
> > + *PtrAddress++ = RegAddress >> (8 * RegAddressWidthInBytes);
> > + }
> > + OperationCount++;
> > + }
> > +
> > + Operations[OperationCount].LengthInBytes = RegValueNumBytes;
> > + Operations[OperationCount].Buffer = RegValue;
> > + Operations[OperationCount].Flags = I2C_FLAG_READ;
> > + OperationCount++;
> > +
> > + RequestPacket.OperationCount = OperationCount;
> > +
> > + Status = I2cBusXfer (
> > + Base, SlaveAddress,
> > + (EFI_I2C_REQUEST_PACKET *)&RequestPacket
> > + );
> > +
> > + return Status;
> > +}
> > +
> > diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.inf
> b/Silicon/NXP/Library/I2cLib/I2cLib.inf
> > new file mode 100644
> > index 000000000000..b9bd79ac1ef1
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/I2cLib/I2cLib.inf
> > @@ -0,0 +1,31 @@
> > +# @file
> > +#
> > +# Component description file for I2cLib module
> > +# Copyright 2017, 2020 NXP
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = I2cLib
> > + FILE_GUID = 8ecefc8f-a2c4-4091-b81f-20f7aeb0567f
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = I2cLib
> > +
> > +[Sources.common]
> > + I2cLib.c
> > +
> > +[LibraryClasses]
> > + IoLib
> > + TimerLib
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[FeaturePcd]
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203
> > +
> > diff --git a/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> > new file mode 100644
> > index 000000000000..2ca4a3639d2c
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> > @@ -0,0 +1,105 @@
> > +/** @file
> > + I2c Lib to control I2c controller.
> > +
> > + Copyright 2020 NXP
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef I2C_LIB_INTERNAL_H__
> > +#define I2C_LIB_INTERNAL_H__
> > +
> > +#include <Pi/PiI2c.h>
> > +#include <Uefi.h>
> > +
> > +/** Module Disable
> > + 0b - The module is enabled. You must clear this field before any other IBCR
> > + fields have any effect.
> > + 1b - The module is reset and disabled. This is the power-on reset situation.
> > + When high, the interface is held in reset, but registers can still be
> > + accessed. Status register fields (IBSR) are not valid when the module
> > + is disabled.
> > +**/
> > +#define I2C_IBCR_MDIS BIT7
> > +// I2c Bus Interrupt Enable
> > +#define I2C_IBCR_IBIE BIT6
> > +/** Master / Slave Mode 0b - Slave mode 1b - Master mode
> > + When you change this field from 0 to 1, the module generates a START
> signal
> > + on the bus and selects the master mode. When you change this field from 1
> to
> > + 0, the module generates a STOP signal and changes the operation mode
> from
> > + master to slave. You should generate a STOP signal only if IBSR[IBIF]=1.
> > + The module clears this field without generating a STOP signal when the
> > + master loses arbitration.
> > +*/
> > +#define I2C_IBCR_MSSL BIT5
> > +// 0b - Receive 1b - Transmit
> > +#define I2C_IBCR_TXRX BIT4
> > +/** Data acknowledge disable
> > + Values written to this field are only used when the I2C module is a receiver,
> > + not a transmitter.
> > + 0b - The module sends an acknowledge signal to the bus at the 9th clock bit
> > + after receiving one byte of data.
> > + 1b - The module does not send an acknowledge-signal response (that is,
> > + acknowledge bit = 1).
> > +**/
> > +#define I2C_IBCR_NOACK BIT3
> > +/**Repeat START
> > + If the I2C module is the current bus master, and you program RSTA=1, the
> I2C
> > + module generates a repeated START condition. This field always reads as a 0.
> > + If you attempt a repeated START at the wrong time, if the bus is owned by
> > + another master the result is loss of arbitration.
> > +**/
> > +#define I2C_IBCR_RSTA BIT2
> > +// DMA enable
> > +#define I2C_IBCR_DMAEN BIT1
> > +
> > +// Transfer Complete
> > +#define I2C_IBSR_TCF BIT7
> > +// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy
> > +#define I2C_IBSR_IBB BIT5
> > +// Arbitration Lost. software must clear this field by writing a one to it.
> > +#define I2C_IBSR_IBAL BIT4
> > +// I2C bus interrupt flag
> > +#define I2C_IBSR_IBIF BIT1
> > +// Received acknowledge 0b - Acknowledge received 1b - No acknowledge
> received
> > +#define I2C_IBSR_RXAK BIT0
> > +
> > +//Bus idle interrupt enable
> > +#define I2C_IBIC_BIIE BIT7
> > +
> > +// Glitch filter enable
> > +#define I2C_IBDBG_GLFLT_EN BIT3
> > +
> > +#define I2C_BUS_TEST_BUSY TRUE
> > +#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY
> > +#define I2C_BUS_TEST_RX_ACK TRUE
> > +#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK
> > +
> > +#define ARRAY_LAST_ELEM(x) (x)[ARRAY_SIZE (x) - 1]
> > +#define I2C_NUM_RETRIES 500
> > +
> > +typedef struct _I2C_REGS {
> > + UINT8 Ibad; // I2c Bus Address Register
> > + UINT8 Ibfd; // I2c Bus Frequency Dividor Register
> > + UINT8 Ibcr; // I2c Bus Control Register
> > + UINT8 Ibsr; // I2c Bus Status Register
> > + UINT8 Ibdr; // I2C Bus Data I/O Register
> > + UINT8 Ibic; // I2C Bus Interrupt Config Register
> > + UINT8 Ibdbg; // I2C Bus Debug Register
> > +} I2C_REGS;
> > +
> > +/*
> > + * sorted list of clock divisor, Ibfd register value pairs
> > + */
> > +typedef struct _I2C_CLOCK_DIVISOR_PAIR {
> > + UINT16 Divisor;
> > + UINT16 Ibfd; // I2c Bus Frequency Dividor Register value
> > +} I2C_CLOCK_DIVISOR_PAIR;
> > +
> > +typedef struct {
> > + UINTN OperationCount;
> > + EFI_I2C_OPERATION Operation[2];
> > +} I2C_REG_REQUEST;
> > +
> > +#endif // I2C_LIB_INTERNAL_H__
> > +
> > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> > index 764b9bb0e2d3..4a1cfb3e278e 100644
> > --- a/Silicon/NXP/NxpQoriqLs.dec
> > +++ b/Silicon/NXP/NxpQoriqLs.dec
> > @@ -1,6 +1,6 @@
> > # @file.
> > #
> > -# Copyright 2017-2019 NXP
> > +# Copyright 2017-2020 NXP
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > #
> > @@ -13,6 +13,10 @@ [Defines]
> > [Includes]
> > Include
> >
> > +[LibraryClasses]
> > + ## @libraryclass Provides services to read/write to I2c devices
> > + I2cLib|Include/Library/I2cLib.h
> > +
> > [Guids.common]
> > gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5,
> 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> > gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e,
> 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
> > @@ -101,3 +105,7 @@ [PcdsFixedAtBuild.common]
> >
> gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x0000031
> 2
> >
> gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x0000
> 0313
> >
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> > +
> > +[PcdsFeatureFlag]
> > +
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x0000
> 0315
> > +
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib
2020-04-06 6:14 ` Pankaj Bansal
@ 2020-04-06 11:12 ` Leif Lindholm
2020-04-09 7:39 ` [EXT] " Varun Sethi
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-06 11:12 UTC (permalink / raw)
To: Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
On Mon, Apr 06, 2020 at 06:14:38 +0000, Pankaj Bansal (OSS) wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Tuesday, March 31, 2020 5:21 PM
> > To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> > <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> > <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> > Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> > Subject: Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib
> >
> > On Fri, Mar 20, 2020 at 20:05:16 +0530, Pankaj Bansal wrote:
> > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > >
> > > I2c lib is going to be used in PrePeiCore sec module to get the
> > > System clock information from devices connected to i2c (like fpga
> > > or clock generator)
> > >
> > > since we don't have support of DXE modules this early in boot stage,
> > > move the i2c controller functionality in library.
> >
> > This isn't moving the functionality to a library though - it is moving
> > the functionality to a library *and* adding new features. These are
> > two separate changes that should be two separate patches.
> >
> > The content in this patch is mostly fine as the end result (but some
> > comments below).
> >
> > I suggest this patch is reordered with 2/28 and all of the splitting
> > out part takes place in that patch. This patch can then be reduced to
> > ... the bits that are currently impossible to see are changed (at
> > least the glitch fixing).
>
> Actually the I2cLib is not some bug fix over I2cDxe.
> The I2cLib has been completely re-written.
> This is because, I2cDxe was written assuming that the I2c transaction would
> always be of (reg + data) type only (i.e. two operations) .
> And also the Repeat start condition was not generated In the I2cDxe driver.
>
> This caused the I2c Peripheral drivers which were written keeping the controller driver
> In mind to issue two operations. Which caused bug in Pcf2129 RTC driver, that I am fixing in patch 3.
>
> Now I have removed these assumptions as well as added Repeat start between successive operations, which
> Comply with PI I2c spec.
>
> So, it would be difficult for me to merge the 1 and 2.
OK, that's fine[1] then, but that means that this commit message is
misleading. Please rewrite it to reflect the actual situation.
(And address the remaining comments on this.)
[1] It's not "fine" - this means we're ripping out and replacing even
more code that was just merged. This pattern needs to stop.
/
Leif
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [EXT] Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib
2020-04-06 11:12 ` Leif Lindholm
@ 2020-04-09 7:39 ` Varun Sethi
0 siblings, 0 replies; 81+ messages in thread
From: Varun Sethi @ 2020-04-09 7:39 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Samer El-Haj-Mahmoud, Jon Nettleton
Hi Leif,
Please find my response inline.
Regards
Varun
-----Original Message-----
From: Leif Lindholm <leif@nuviainc.com>
Sent: Monday, April 6, 2020 4:42 PM
To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
Subject: [EXT] Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib
Caution: EXT Email
On Mon, Apr 06, 2020 at 06:14:38 +0000, Pankaj Bansal (OSS) wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Tuesday, March 31, 2020 5:21 PM
> > To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D
> > Kinney <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun
> > Sethi <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> > Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> > Subject: Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib
> >
> > On Fri, Mar 20, 2020 at 20:05:16 +0530, Pankaj Bansal wrote:
> > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > >
> > > I2c lib is going to be used in PrePeiCore sec module to get the
> > > System clock information from devices connected to i2c (like fpga
> > > or clock generator)
> > >
> > > since we don't have support of DXE modules this early in boot
> > > stage, move the i2c controller functionality in library.
> >
> > This isn't moving the functionality to a library though - it is
> > moving the functionality to a library *and* adding new features.
> > These are two separate changes that should be two separate patches.
> >
> > The content in this patch is mostly fine as the end result (but some
> > comments below).
> >
> > I suggest this patch is reordered with 2/28 and all of the splitting
> > out part takes place in that patch. This patch can then be reduced
> > to ... the bits that are currently impossible to see are changed (at
> > least the glitch fixing).
>
> Actually the I2cLib is not some bug fix over I2cDxe.
> The I2cLib has been completely re-written.
> This is because, I2cDxe was written assuming that the I2c transaction
> would always be of (reg + data) type only (i.e. two operations) .
> And also the Repeat start condition was not generated In the I2cDxe driver.
>
> This caused the I2c Peripheral drivers which were written keeping the
> controller driver In mind to issue two operations. Which caused bug in Pcf2129 RTC driver, that I am fixing in patch 3.
>
> Now I have removed these assumptions as well as added Repeat start
> between successive operations, which Comply with PI I2c spec.
>
> So, it would be difficult for me to merge the 1 and 2.
>OK, that's fine[1] then, but that means that this commit message is misleading. Please rewrite it to reflect the actual situation.
>(And address the remaining comments on this.)
>[1] It's not "fine" - this means we're ripping out and replacing even
> more code that was just merged. This pattern needs to stop.
I agree Leif, we will take care of this going forward. Some of the modifications (as per the patchset) were done by Pankaj after the initial patches got merged. We thought that it would be a good idea to post these patches in oneshot. We will re-visit our upstream patch submission strategy and make sure that there are no conflicts going forward. We are already aligning upstream patches for other platforms with Pankaj's patchset.
Really appreciate your help.
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 02/28] Silicon/NXP: changes to use I2clib in i2cdxe
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
2020-03-20 14:35 ` [PATCH v2 01/28] Silicon/NXP: Add I2c lib Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-03-20 14:35 ` [PATCH v2 03/28] Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC Pankaj Bansal
` (27 subsequent siblings)
29 siblings, 0 replies; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
I2c lib contains the i2c controller functionality. this can be used
in I2c DXE driver to communicate with i2c devices.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 526 +-------------------------
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 44 +--
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 9 +-
3 files changed, 16 insertions(+), 563 deletions(-)
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index 853c426fbca2..848e707c1673 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -1,7 +1,7 @@
/** I2cDxe.c
I2c driver APIs for read, write, initialize, set speed and reset
- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,6 +10,7 @@
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
+#include <Library/I2cLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/TimerLib.h>
@@ -25,444 +26,6 @@ STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES mI2cControllerCapabilities = {
0
};
-STATIC CONST CLK_DIV mClkDiv[] = {
- { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
- { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
- { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
- { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
- { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
- { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
- { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
- { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
- { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
- { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
- { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
- { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
- { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
- { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
- { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }
-};
-
-/**
- Calculate and return proper clock divider
-
- @param Rate desired clock rate
-
- @retval ClkDiv Index value used to get Bus Clock Rate
-
-**/
-STATIC
-UINT8
-GetClkDivIndex (
- IN UINT32 Rate
- )
-{
- UINTN ClkRate;
- UINT32 Div;
- UINT8 Index;
-
- Index = 0;
- ClkRate = GetBusFrequency ();
-
- Div = (ClkRate + Rate - 1) / Rate;
-
- if (Div < mClkDiv[0].SCLDivider) {
- return 0;
- }
-
- do {
- if (mClkDiv[Index].SCLDivider >= Div ) {
- return Index;
- }
- Index++;
- } while (Index < ARRAY_SIZE (mClkDiv));
-
- return (ARRAY_SIZE (mClkDiv) - 1);
-}
-
-/**
- Function used to check if i2c is in mentioned state or not
-
- @param I2cRegs Pointer to I2C registers
- @param State i2c state need to be checked
-
- @retval EFI_NOT_READY Arbitration was lost
- @retval EFI_TIMEOUT Timeout occured
- @retval CurrState Value of state register
-
-**/
-STATIC
-EFI_STATUS
-WaitForI2cState (
- IN I2C_REGS *I2cRegs,
- IN UINT32 State
- )
-{
- UINT8 CurrState;
- UINT64 Count;
-
- for (Count = 0; Count < I2C_STATE_RETRIES; Count++) {
- MemoryFence ();
- CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
- if (CurrState & I2C_SR_IAL) {
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
- return EFI_NOT_READY;
- }
-
- if ((CurrState & (State >> 8)) == (UINT8)State) {
- return CurrState;
- }
- }
-
- return EFI_TIMEOUT;
-}
-
-/**
- Function to transfer byte on i2c
-
- @param I2cRegs Pointer to i2c registers
- @param Byte Byte to be transferred on i2c bus
-
- @retval EFI_NOT_READY Arbitration was lost
- @retval EFI_TIMEOUT Timeout occured
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Data transfer was succesful
-
-**/
-STATIC
-EFI_STATUS
-TransferByte (
- IN I2C_REGS *I2cRegs,
- IN UINT8 Byte
- )
-{
- EFI_STATUS RetVal;
-
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
- MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
-
- RetVal = WaitForI2cState (I2cRegs, IIF);
- if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
- return RetVal;
- }
-
- if (RetVal & I2C_SR_RX_NO_AK) {
- return EFI_NOT_FOUND;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Function to stop transaction on i2c bus
-
- @param I2cRegs Pointer to i2c registers
-
- @retval EFI_NOT_READY Arbitration was lost
- @retval EFI_TIMEOUT Timeout occured
- @retval EFI_SUCCESS Stop operation was successful
-
-**/
-STATIC
-EFI_STATUS
-I2cStop (
- IN I2C_REGS *I2cRegs
- )
-{
- EFI_STATUS RetVal;
- UINT32 Temp;
-
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
-
- Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
-
- RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
-
- if (RetVal < 0) {
- return RetVal;
- } else {
- return EFI_SUCCESS;
- }
-}
-
-/**
- Function to send start signal, Chip Address and
- memory offset
-
- @param I2cRegs Pointer to i2c base registers
- @param Chip Chip Address
- @param Offset Slave memory's offset
- @param AddressLength length of chip address
-
- @retval EFI_NOT_READY Arbitration lost
- @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Read was successful
-
-**/
-STATIC
-EFI_STATUS
-InitTransfer (
- IN I2C_REGS *I2cRegs,
- IN UINT8 Chip,
- IN UINT32 Offset,
- IN INT32 AddressLength
- )
-{
- UINT32 Temp;
- EFI_STATUS RetVal;
-
- // Enable I2C controller
- if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
- }
-
- if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
- MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
- }
-
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
- RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
- if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
- return RetVal;
- }
-
- // Start I2C transaction
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
- // set to master mode
- Temp |= I2C_CR_MSTA;
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
-
- RetVal = WaitForI2cState (I2cRegs, BUS_BUSY);
- if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
- return RetVal;
- }
-
- Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
-
- // write slave Address
- RetVal = TransferByte (I2cRegs, Chip << 1);
- if (RetVal != EFI_SUCCESS) {
- return RetVal;
- }
-
- if (AddressLength >= 0) {
- while (AddressLength--) {
- RetVal = TransferByte (I2cRegs, (Offset >> (AddressLength * 8)) & 0xff);
- if (RetVal != EFI_SUCCESS)
- return RetVal;
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Function to check if i2c bus is idle
-
- @param Base Pointer to base address of I2c controller
-
- @retval EFI_SUCCESS
-
-**/
-STATIC
-INT32
-I2cBusIdle (
- IN VOID *Base
- )
-{
- return EFI_SUCCESS;
-}
-
-/**
- Function to initiate data transfer on i2c bus
-
- @param I2cRegs Pointer to i2c base registers
- @param Chip Chip Address
- @param Offset Slave memory's offset
- @param AddressLength length of chip address
-
- @retval EFI_NOT_READY Arbitration lost
- @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Read was successful
-
-**/
-STATIC
-EFI_STATUS
-InitDataTransfer (
- IN I2C_REGS *I2cRegs,
- IN UINT8 Chip,
- IN UINT32 Offset,
- IN INT32 AddressLength
- )
-{
- EFI_STATUS RetVal;
- INT32 Retry;
-
- for (Retry = 0; Retry < RETRY_COUNT; Retry++) {
- RetVal = InitTransfer (I2cRegs, Chip, Offset, AddressLength);
- if (RetVal == EFI_SUCCESS) {
- return EFI_SUCCESS;
- }
-
- I2cStop (I2cRegs);
-
- if (EFI_NOT_FOUND == RetVal) {
- return RetVal;
- }
-
- // Disable controller
- if (RetVal != EFI_NOT_READY) {
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
- }
-
- if (I2cBusIdle (I2cRegs) < 0) {
- break;
- }
- }
- return RetVal;
-}
-
-/**
- Function to read data using i2c bus
-
- @param BaseAddr I2c Controller Base Address
- @param Chip Address of slave device from where data to be read
- @param Offset Offset of slave memory
- @param AddressLength Address length of slave
- @param Buffer A pointer to the destination buffer for the data
- @param Len Length of data to be read
-
- @retval EFI_NOT_READY Arbitration lost
- @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Read was successful
-
-**/
-STATIC
-EFI_STATUS
-I2cDataRead (
- IN UINTN BaseAddr,
- IN UINT8 Chip,
- IN UINT32 Offset,
- IN UINT32 AddressLength,
- IN UINT8 *Buffer,
- IN UINT32 Len
- )
-{
- EFI_STATUS RetVal;
- UINT32 Temp;
- INT32 I;
- I2C_REGS *I2cRegs;
-
- I2cRegs = (I2C_REGS *)(BaseAddr);
-
- RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
- if (RetVal != EFI_SUCCESS) {
- return RetVal;
- }
-
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
- Temp |= I2C_CR_RSTA;
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
-
- RetVal = TransferByte (I2cRegs, (Chip << 1) | 1);
- if (RetVal != EFI_SUCCESS) {
- I2cStop (I2cRegs);
- return RetVal;
- }
-
- // setup bus to read data
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
- Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
- if (Len == 1) {
- Temp |= I2C_CR_TX_NO_AK;
- }
-
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
-
- // Dummy Read to initiate recieve operation
- MmioRead8 ((UINTN)&I2cRegs->I2cDr);
-
- for (I = 0; I < Len; I++) {
- RetVal = WaitForI2cState (I2cRegs, IIF);
- if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
- I2cStop (I2cRegs);
- return RetVal;
- }
- //
- // It must generate STOP before read I2DR to prevent
- // controller from generating another clock cycle
- //
- if (I == (Len - 1)) {
- I2cStop (I2cRegs);
- } else if (I == (Len - 2)) {
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
- Temp |= I2C_CR_TX_NO_AK;
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
- }
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
- Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
- }
-
- I2cStop (I2cRegs);
-
- return EFI_SUCCESS;
-}
-
-/**
- Function to write data using i2c bus
-
- @param BaseAddr I2c Controller Base Address
- @param Chip Address of slave device where data to be written
- @param Offset Offset of slave memory
- @param AddressLength Address length of slave
- @param Buffer A pointer to the source buffer for the data
- @param Len Length of data to be write
-
- @retval EFI_NOT_READY Arbitration lost
- @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Read was successful
-
-**/
-STATIC
-EFI_STATUS
-I2cDataWrite (
- IN UINTN BaseAddr,
- IN UINT8 Chip,
- IN UINT32 Offset,
- IN INT32 AddressLength,
- OUT UINT8 *Buffer,
- IN INT32 Len
- )
-{
- EFI_STATUS RetVal;
- I2C_REGS *I2cRegs;
- INT32 I;
-
- I2cRegs = (I2C_REGS *)BaseAddr;
-
- RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
- if (RetVal != EFI_SUCCESS) {
- return RetVal;
- }
-
- // Write operation
- for (I = 0; I < Len; I++) {
- RetVal = TransferByte (I2cRegs, Buffer[I]);
- if (RetVal != EFI_SUCCESS) {
- break;
- }
- }
-
- I2cStop (I2cRegs);
- return RetVal;
-}
-
/**
Function to set i2c bus frequency
@@ -479,22 +42,17 @@ SetBusFrequency (
IN OUT UINTN *BusClockHertz
)
{
- I2C_REGS *I2cRegs;
- UINT8 ClkId;
- UINT8 SpeedId;
+ UINTN I2cBase;
+ UINT64 I2cClock;
NXP_I2C_MASTER *I2c;
I2c = NXP_I2C_FROM_THIS (This);
- I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
+ I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
- ClkId = GetClkDivIndex (*BusClockHertz);
- SpeedId = mClkDiv[ClkId].BusClockRate;
+ I2cClock = GetBusFrequency ();
- // Store divider value
- MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
-
- MemoryFence ();
+ I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
return EFI_SUCCESS;
}
@@ -513,19 +71,6 @@ Reset (
IN CONST EFI_I2C_MASTER_PROTOCOL *This
)
{
- I2C_REGS *I2cRegs;
- NXP_I2C_MASTER *I2c;
-
- I2c = NXP_I2C_FROM_THIS (This);
-
- I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
-
- // Reset module
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
-
- MemoryFence ();
-
return EFI_SUCCESS;
}
@@ -540,62 +85,17 @@ StartRequest (
OUT EFI_STATUS *I2cStatus OPTIONAL
)
{
- NXP_I2C_MASTER *I2c;
- UINT32 Count;
- INT32 RetVal;
- UINT32 Length;
- UINT8 *Buffer;
- UINT32 Flag;
- UINT32 RegAddress;
- UINT32 OffsetLength;
-
- RegAddress = 0;
+ NXP_I2C_MASTER *I2c;
+ UINTN I2cBase;
+ EFI_STATUS Status;
I2c = NXP_I2C_FROM_THIS (This);
- if (RequestPacket->OperationCount <= 0) {
- DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
- __FUNCTION__, RequestPacket->OperationCount));
- return EFI_INVALID_PARAMETER;
- }
+ I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
- OffsetLength = RequestPacket->Operation[0].LengthInBytes;
- RegAddress = *RequestPacket->Operation[0].Buffer;
+ Status = I2cBusXfer (I2cBase, SlaveAddress, RequestPacket);
- for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
- Flag = RequestPacket->Operation[Count].Flags;
- Length = RequestPacket->Operation[Count].LengthInBytes;
- Buffer = RequestPacket->Operation[Count].Buffer;
-
- if (Length <= 0) {
- DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
- __FUNCTION__, Length));
- return EFI_INVALID_PARAMETER;
- }
-
- if (Flag == I2C_FLAG_READ) {
- RetVal = I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
- RegAddress, OffsetLength, Buffer, Length);
- if (RetVal != EFI_SUCCESS) {
- DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
- __FUNCTION__, RetVal));
- return RetVal;
- }
- } else if (Flag == I2C_FLAG_WRITE) {
- RetVal = I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
- RegAddress, OffsetLength, Buffer, Length);
- if (RetVal != EFI_SUCCESS) {
- DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
- __FUNCTION__, RetVal));
- return RetVal;
- }
- } else {
- DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n", __FUNCTION__, Flag));
- return EFI_INVALID_PARAMETER;
- }
- }
-
- return EFI_SUCCESS;
+ return Status;
}
EFI_STATUS
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
index 02a29a5cf2b9..88316f313380 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -1,7 +1,7 @@
/** I2cDxe.h
Header defining the constant, base address amd function for I2C controller
- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -16,32 +16,6 @@
#include <Protocol/I2cMaster.h>
#include <Protocol/NonDiscoverableDevice.h>
-#define I2C_CR_IIEN (1 << 6)
-#define I2C_CR_MSTA (1 << 5)
-#define I2C_CR_MTX (1 << 4)
-#define I2C_CR_TX_NO_AK (1 << 3)
-#define I2C_CR_RSTA (1 << 2)
-
-#define I2C_SR_ICF (1 << 7)
-#define I2C_SR_IBB (1 << 5)
-#define I2C_SR_IAL (1 << 4)
-#define I2C_SR_IIF (1 << 1)
-#define I2C_SR_RX_NO_AK (1 << 0)
-
-#define I2C_CR_IEN (0 << 7)
-#define I2C_CR_IDIS (1 << 7)
-#define I2C_SR_IIF_CLEAR (1 << 1)
-
-#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
-#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
-#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
-
-#define I2C_FLAG_WRITE 0x0
-
-#define I2C_STATE_RETRIES 50000
-
-#define RETRY_COUNT 3
-
#define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C')
#define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \
I2cMaster, NXP_I2C_SIGNATURE)
@@ -63,22 +37,6 @@ typedef struct {
NON_DISCOVERABLE_DEVICE *Dev;
} NXP_I2C_MASTER;
-/**
- Record defining i2c registers
-**/
-typedef struct {
- UINT8 I2cAdr;
- UINT8 I2cFdr;
- UINT8 I2cCr;
- UINT8 I2cSr;
- UINT8 I2cDr;
-} I2C_REGS;
-
-typedef struct {
- UINT16 SCLDivider;
- UINT16 BusClockRate;
-} CLK_DIV;
-
extern
UINT64
GetBusFrequency (
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 0c0bf63bb2e2..84adb837c249 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -3,7 +3,7 @@
# Component description file for I2c driver
#
# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -27,6 +27,7 @@ [LibraryClasses]
ArmLib
BaseMemoryLib
DevicePathLib
+ I2cLib
IoLib
MemoryAllocationLib
PcdLib
@@ -48,11 +49,5 @@ [Protocols]
gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
gEfiI2cMasterProtocolGuid ## BY_START
-[Pcd]
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
-
[Depex]
TRUE
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* [PATCH v2 03/28] Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
2020-03-20 14:35 ` [PATCH v2 01/28] Silicon/NXP: Add I2c lib Pankaj Bansal
2020-03-20 14:35 ` [PATCH v2 02/28] Silicon/NXP: changes to use I2clib in i2cdxe Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-03-31 11:58 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 04/28] Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib Pankaj Bansal
` (26 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
With latest edk2 codebase, sometimes i2c timeout is observed when
Network devices are being probed.
This is happening when gRT->GetTime request is ongoing.
gRT->GetTime triggers a read request to Real Time Clock which is
connected to I2c bus.
In between read request, if an event occurs, which also triggers
gRT->GetTime (i.e. RTC read), the I2c bus goes into unrecovered state.
This state is not even recovered, when rebooting the board.
We need to power off the board completely to recover i2c bus.
To prevent this, TPL level of I2c read is being raised to high, so that
no other event can preempt this. with this solution no timeout has been
observed so far.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 12 ++++++++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 3 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index 848e707c1673..a5aba47b3ed4 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -16,6 +16,7 @@
#include <Library/TimerLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeLib.h>
#include "I2cDxe.h"
@@ -88,6 +89,13 @@ StartRequest (
NXP_I2C_MASTER *I2c;
UINTN I2cBase;
EFI_STATUS Status;
+ EFI_TPL Tpl;
+ BOOLEAN AtRuntime;
+
+ AtRuntime = EfiAtRuntime ();
+ if (!AtRuntime) {
+ Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ }
I2c = NXP_I2C_FROM_THIS (This);
@@ -95,6 +103,10 @@ StartRequest (
Status = I2cBusXfer (I2cBase, SlaveAddress, RequestPacket);
+ if (!AtRuntime) {
+ gBS->RestoreTPL (Tpl);
+ }
+
return Status;
}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 84adb837c249..867376044656 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -13,7 +13,7 @@ [Defines]
INF_VERSION = 0x0001001A
BASE_NAME = I2cDxe
FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
- MODULE_TYPE = DXE_DRIVER
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = I2cDxeEntryPoint
UNLOAD = I2cDxeUnload
@@ -36,6 +36,7 @@ [LibraryClasses]
UefiBootServicesTableLib
UefiDriverEntryPoint
UefiLib
+ UefiRuntimeLib
[Guids]
gNxpNonDiscoverableI2cMasterGuid
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 03/28] Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC
2020-03-20 14:35 ` [PATCH v2 03/28] Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC Pankaj Bansal
@ 2020-03-31 11:58 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-03-31 11:58 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:18 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> With latest edk2 codebase, sometimes i2c timeout is observed when
> Network devices are being probed.
> This is happening when gRT->GetTime request is ongoing.
> gRT->GetTime triggers a read request to Real Time Clock which is
> connected to I2c bus.
> In between read request, if an event occurs, which also triggers
> gRT->GetTime (i.e. RTC read), the I2c bus goes into unrecovered state.
>
> This state is not even recovered, when rebooting the board.
> We need to power off the board completely to recover i2c bus.
>
> To prevent this, TPL level of I2c read is being raised to high, so that
> no other event can preempt this. with this solution no timeout has been
> observed so far.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 12 ++++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 3 ++-
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> index 848e707c1673..a5aba47b3ed4 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> @@ -16,6 +16,7 @@
> #include <Library/TimerLib.h>
> #include <Library/UefiBootServicesTableLib.h>
> #include <Library/UefiLib.h>
> +#include <Library/UefiRuntimeLib.h>
>
> #include "I2cDxe.h"
>
> @@ -88,6 +89,13 @@ StartRequest (
> NXP_I2C_MASTER *I2c;
> UINTN I2cBase;
> EFI_STATUS Status;
> + EFI_TPL Tpl;
> + BOOLEAN AtRuntime;
> +
> + AtRuntime = EfiAtRuntime ();
> + if (!AtRuntime) {
> + Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
> + }
>
> I2c = NXP_I2C_FROM_THIS (This);
>
> @@ -95,6 +103,10 @@ StartRequest (
>
> Status = I2cBusXfer (I2cBase, SlaveAddress, RequestPacket);
>
> + if (!AtRuntime) {
> + gBS->RestoreTPL (Tpl);
> + }
> +
> return Status;
> }
>
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> index 84adb837c249..867376044656 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -13,7 +13,7 @@ [Defines]
> INF_VERSION = 0x0001001A
> BASE_NAME = I2cDxe
> FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
> - MODULE_TYPE = DXE_DRIVER
> + MODULE_TYPE = DXE_RUNTIME_DRIVER
> VERSION_STRING = 1.0
> ENTRY_POINT = I2cDxeEntryPoint
> UNLOAD = I2cDxeUnload
> @@ -36,6 +36,7 @@ [LibraryClasses]
> UefiBootServicesTableLib
> UefiDriverEntryPoint
> UefiLib
> + UefiRuntimeLib
>
> [Guids]
> gNxpNonDiscoverableI2cMasterGuid
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 04/28] Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (2 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 03/28] Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-03-31 12:30 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 05/28] Silicon/Maxim: Add comments " Pankaj Bansal
` (25 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
There was a bug in I2C DXE implementation, which caused the Ds1307 RTC
device to issue two operation for register write, while this is a single
operation task. refer page 12 (Slave Receiver Mode (Write Mode)) on
https://datasheets.maximintegrated.com/en/ds/DS1307.pdf
Modify ds1307 RtcWrite code accordingly.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
index 88dc198ffec8..fd7a8696e405 100644
--- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -5,7 +5,7 @@
EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright 2017 NXP
+ Copyright 2017, 2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -84,16 +84,15 @@ RtcWrite (
{
RTC_I2C_REQUEST Req;
EFI_STATUS Status;
+ UINT8 Buffer[2];
- Req.OperationCount = 2;
+ Req.OperationCount = 1;
+ Buffer[0] = RtcRegAddr;
+ Buffer[1] = Val;
Req.SetAddressOp.Flags = 0;
- Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
- Req.SetAddressOp.Buffer = &RtcRegAddr;
-
- Req.GetSetDateTimeOp.Flags = 0;
- Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
- Req.GetSetDateTimeOp.Buffer = &Val;
+ Req.SetAddressOp.LengthInBytes = sizeof (Buffer);
+ Req.SetAddressOp.Buffer = Buffer;
Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
(VOID *)&Req,
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 04/28] Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib
2020-03-20 14:35 ` [PATCH v2 04/28] Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib Pankaj Bansal
@ 2020-03-31 12:30 ` Leif Lindholm
2020-04-06 6:18 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-03-31 12:30 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:19 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> There was a bug in I2C DXE implementation, which caused the Ds1307 RTC
> device to issue two operation for register write, while this is a single
> operation task. refer page 12 (Slave Receiver Mode (Write Mode)) on
>
> https://datasheets.maximintegrated.com/en/ds/DS1307.pdf
>
> Modify ds1307 RtcWrite code accordingly.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
So, I'm OK with this patch, but I'll mention that I prefer the design
in Silicon/NXP/Library/Pcf8563RealTimeClockLib which I think could
also be applied here. I think that might have avoided the confusion
that caused the bug.
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> index 88dc198ffec8..fd7a8696e405 100644
> --- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> @@ -5,7 +5,7 @@
> EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
>
> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> - Copyright 2017 NXP
> + Copyright 2017, 2020 NXP
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -84,16 +84,15 @@ RtcWrite (
> {
> RTC_I2C_REQUEST Req;
> EFI_STATUS Status;
> + UINT8 Buffer[2];
>
> - Req.OperationCount = 2;
> + Req.OperationCount = 1;
> + Buffer[0] = RtcRegAddr;
> + Buffer[1] = Val;
>
> Req.SetAddressOp.Flags = 0;
> - Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> - Req.SetAddressOp.Buffer = &RtcRegAddr;
> -
> - Req.GetSetDateTimeOp.Flags = 0;
> - Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> - Req.GetSetDateTimeOp.Buffer = &Val;
> + Req.SetAddressOp.LengthInBytes = sizeof (Buffer);
> + Req.SetAddressOp.Buffer = Buffer;
>
> Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
> (VOID *)&Req,
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 04/28] Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib
2020-03-31 12:30 ` Leif Lindholm
@ 2020-04-06 6:18 ` Pankaj Bansal
0 siblings, 0 replies; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-06 6:18 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Tuesday, March 31, 2020 6:01 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 04/28] Silicon/Maxim: Fix bug in RtcWrite in
> Ds1307RtcLib
>
> On Fri, Mar 20, 2020 at 20:05:19 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > There was a bug in I2C DXE implementation, which caused the Ds1307 RTC
> > device to issue two operation for register write, while this is a single
> > operation task. refer page 12 (Slave Receiver Mode (Write Mode)) on
> >
> > https://datasheets.maximintegrated.com/en/ds/DS1307.pdf
> >
> > Modify ds1307 RtcWrite code accordingly.
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> So, I'm OK with this patch, but I'll mention that I prefer the design
> in Silicon/NXP/Library/Pcf8563RealTimeClockLib which I think could
> also be applied here. I think that might have avoided the confusion
> that caused the bug.
Actually this bug was introduced because the Pcf2129 RTC driver was written
Based on I2cDxe driver, which assumed that all I2c transaction would be (reg, data)
Pair, i.e. always two operations.
>
> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
>
> > ---
> > Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 15 +++++++--------
> > 1 file changed, 7 insertions(+), 8 deletions(-)
> >
> > diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> > index 88dc198ffec8..fd7a8696e405 100644
> > --- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> > +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> > @@ -5,7 +5,7 @@
> > EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> >
> > Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> > - Copyright 2017 NXP
> > + Copyright 2017, 2020 NXP
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > @@ -84,16 +84,15 @@ RtcWrite (
> > {
> > RTC_I2C_REQUEST Req;
> > EFI_STATUS Status;
> > + UINT8 Buffer[2];
> >
> > - Req.OperationCount = 2;
> > + Req.OperationCount = 1;
> > + Buffer[0] = RtcRegAddr;
> > + Buffer[1] = Val;
> >
> > Req.SetAddressOp.Flags = 0;
> > - Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> > - Req.SetAddressOp.Buffer = &RtcRegAddr;
> > -
> > - Req.GetSetDateTimeOp.Flags = 0;
> > - Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> > - Req.GetSetDateTimeOp.Buffer = &Val;
> > + Req.SetAddressOp.LengthInBytes = sizeof (Buffer);
> > + Req.SetAddressOp.Buffer = Buffer;
> >
> > Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8
> (PcdI2cSlaveAddress),
> > (VOID *)&Req,
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 05/28] Silicon/Maxim: Add comments in Ds1307RtcLib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (3 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 04/28] Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-03-31 12:31 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 06/28] NXP/LS1043aRdb: Move Soc specific components to soc files Pankaj Bansal
` (24 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Add comments to explain the register read and write operation
on Ds1307. These comments have been referred from data sheet:
https://datasheets.maximintegrated.com/en/ds/DS1307.pdf
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
index fd7a8696e405..444e01124811 100644
--- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -28,6 +28,11 @@ STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
/**
Read RTC register.
+ Data Read-Slave Transmitter Mode
+
+ <Slave Address> <Word Address (n)> <Slave Address> <Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>
+
+ The first byte is received and handled as in the slave receiver mode.
@param RtcRegAddr Register offset of RTC to be read.
@@ -69,6 +74,9 @@ RtcRead (
/**
Write RTC register.
+ Data Write-Slave Receiver Mode
+
+ <Slave Address> <Word Address (n)> <Data(n)> <Data(n+1)> <Data(n+X)>
@param RtcRegAddr Register offset of RTC to write.
@param Val Value to be written
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 05/28] Silicon/Maxim: Add comments in Ds1307RtcLib
2020-03-20 14:35 ` [PATCH v2 05/28] Silicon/Maxim: Add comments " Pankaj Bansal
@ 2020-03-31 12:31 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-03-31 12:31 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:20 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Add comments to explain the register read and write operation
> on Ds1307. These comments have been referred from data sheet:
>
> https://datasheets.maximintegrated.com/en/ds/DS1307.pdf
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> index fd7a8696e405..444e01124811 100644
> --- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> @@ -28,6 +28,11 @@ STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
>
> /**
> Read RTC register.
> + Data Read-Slave Transmitter Mode
> +
> + <Slave Address> <Word Address (n)> <Slave Address> <Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>
> +
> + The first byte is received and handled as in the slave receiver mode.
>
> @param RtcRegAddr Register offset of RTC to be read.
>
> @@ -69,6 +74,9 @@ RtcRead (
>
> /**
> Write RTC register.
> + Data Write-Slave Receiver Mode
> +
> + <Slave Address> <Word Address (n)> <Data(n)> <Data(n+1)> <Data(n+X)>
>
> @param RtcRegAddr Register offset of RTC to write.
> @param Val Value to be written
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 06/28] NXP/LS1043aRdb: Move Soc specific components to soc files
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (4 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 05/28] Silicon/Maxim: Add comments " Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 9:42 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib Pankaj Bansal
` (23 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Soc specific components ought to be part of Soc files and not
platform files. move the same to SOC files
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 7 +------
Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 7 ++++++-
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index c8105593533f..802cccdce63b 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -2,7 +2,7 @@
#
# LS1043ARDB Board package.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -26,11 +26,7 @@ [Defines]
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
[LibraryClasses.common]
- SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
- ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
- SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
- IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
[PcdsFixedAtBuild.common]
@@ -46,7 +42,6 @@ [PcdsFixedAtBuild.common]
#
# Board Specific Pcds
#
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index b28e0615f7ca..94d3e53a046b 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -95,6 +95,8 @@ [LibraryClasses.common]
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index dbd680b0ad28..d2d4133428c3 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -1,12 +1,16 @@
# LS1043A.dsc
# LS1043A Soc package.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
@@ -20,6 +24,7 @@ [PcdsDynamicDefault.common]
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
#
# CCSR Address Space and other attached Memories
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 06/28] NXP/LS1043aRdb: Move Soc specific components to soc files
2020-03-20 14:35 ` [PATCH v2 06/28] NXP/LS1043aRdb: Move Soc specific components to soc files Pankaj Bansal
@ 2020-04-01 9:42 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 9:42 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:21 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Soc specific components ought to be part of Soc files and not
> platform files. move the same to SOC files
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 7 +------
> Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 7 ++++++-
> 3 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index c8105593533f..802cccdce63b 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -2,7 +2,7 @@
> #
> # LS1043ARDB Board package.
> #
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -26,11 +26,7 @@ [Defines]
> !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
>
> [LibraryClasses.common]
> - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> - ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> - SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> - IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
>
> [PcdsFixedAtBuild.common]
> @@ -46,7 +42,6 @@ [PcdsFixedAtBuild.common]
> #
> # Board Specific Pcds
> #
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
>
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> index b28e0615f7ca..94d3e53a046b 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -95,6 +95,8 @@ [LibraryClasses.common]
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
>
> I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
>
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index dbd680b0ad28..d2d4133428c3 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -1,12 +1,16 @@
> # LS1043A.dsc
> # LS1043A Soc package.
> #
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> #
>
> +[LibraryClasses.common]
> + SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> +
> ################################################################################
> #
> # Pcd Section - list of all EDK II PCD Entries defined by this Platform
> @@ -20,6 +24,7 @@ [PcdsDynamicDefault.common]
> gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
>
> [PcdsFixedAtBuild.common]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
>
> #
> # CCSR Address Space and other attached Memories
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (5 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 06/28] NXP/LS1043aRdb: Move Soc specific components to soc files Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 9:53 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 08/28] Silicon/NXP/LS1043A: Use BaseSerialPortLib16550 as SerialPortLib Pankaj Bansal
` (22 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Implement SerialUartClockLib for all NXP Layerscape Platforms.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../SerialUartClockLib/SerialUartClockLib.c | 27 +++++++++++++++++++
.../SerialUartClockLib/SerialUartClockLib.inf | 26 ++++++++++++++++++
2 files changed, 53 insertions(+)
create mode 100644 Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
create mode 100644 Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
new file mode 100644
index 000000000000..9d49d7b4748b
--- /dev/null
+++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
@@ -0,0 +1,27 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Base.h>
+
+extern
+UINT64
+GetBusFrequency (
+ VOID
+ );
+
+/**
+ Return clock in for Uart IP
+**/
+UINT32
+EFIAPI
+BaseSerialPortGetClock (
+ VOID
+ )
+{
+ return GetBusFrequency ();
+}
diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
new file mode 100644
index 000000000000..9a3e80cf521d
--- /dev/null
+++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
@@ -0,0 +1,26 @@
+# @file
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 1.27
+ BASE_NAME = SerialUartClockLib
+ FILE_GUID = fa65495e-d3c8-4ea3-9737-994e9ccbaf11
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialUartClockLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Sources.common]
+ SerialUartClockLib.c
+
+[LibraryClasses]
+ SocLib
+
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
2020-03-20 14:35 ` [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib Pankaj Bansal
@ 2020-04-01 9:53 ` Leif Lindholm
2020-04-06 6:33 ` Pankaj Bansal
2020-04-13 3:00 ` Pankaj Bansal
0 siblings, 2 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 9:53 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:22 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Implement SerialUartClockLib for all NXP Layerscape Platforms.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../SerialUartClockLib/SerialUartClockLib.c | 27 +++++++++++++++++++
> .../SerialUartClockLib/SerialUartClockLib.inf | 26 ++++++++++++++++++
I requested after the initial submission that you "either follow the
manual git setup steps from
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-git-guide-for-edk2-contributors-and-maintainers
or execute edk2/BaseTools/Scripts/SetupGit.py in each of the tianocore
repositories"
Now, neither appears to have happened, as .c still comes before .inf
and paths are still truncated.
But in addition to that, we realised that git happily ignores settings
for --stat. So, please, execute aforementioned script, but then
generate v3 with --stat=1000 --stat-graph-width=20.
For this particular patch, the side discussion on the edk2 portion may
make it redundant, so I'm deferring review.
/
Leif
> 2 files changed, 53 insertions(+)
> create mode 100644 Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> create mode 100644 Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
>
> diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> new file mode 100644
> index 000000000000..9d49d7b4748b
> --- /dev/null
> +++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> @@ -0,0 +1,27 @@
> +/** @file
> +*
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Base.h>
> +
> +extern
> +UINT64
> +GetBusFrequency (
> + VOID
> + );
> +
> +/**
> + Return clock in for Uart IP
> +**/
> +UINT32
> +EFIAPI
> +BaseSerialPortGetClock (
> + VOID
> + )
> +{
> + return GetBusFrequency ();
> +}
> diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> new file mode 100644
> index 000000000000..9a3e80cf521d
> --- /dev/null
> +++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> @@ -0,0 +1,26 @@
> +# @file
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 1.27
> + BASE_NAME = SerialUartClockLib
> + FILE_GUID = fa65495e-d3c8-4ea3-9737-994e9ccbaf11
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SerialUartClockLib
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Sources.common]
> + SerialUartClockLib.c
> +
> +[LibraryClasses]
> + SocLib
> +
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
2020-04-01 9:53 ` Leif Lindholm
@ 2020-04-06 6:33 ` Pankaj Bansal
2020-04-06 11:24 ` Leif Lindholm
2020-04-13 3:00 ` Pankaj Bansal
1 sibling, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-06 6:33 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Wednesday, April 1, 2020 3:23 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
>
> On Fri, Mar 20, 2020 at 20:05:22 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > Implement SerialUartClockLib for all NXP Layerscape Platforms.
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > .../SerialUartClockLib/SerialUartClockLib.c | 27 +++++++++++++++++++
> > .../SerialUartClockLib/SerialUartClockLib.inf | 26 ++++++++++++++++++
>
> I requested after the initial submission that you "either follow the
> manual git setup steps from
> https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-
> git-guide-for-edk2-contributors-and-maintainers
> or execute edk2/BaseTools/Scripts/SetupGit.py in each of the tianocore
> repositories"
>
> Now, neither appears to have happened, as .c still comes before .inf
> and paths are still truncated.
I had executed the SetupGit.py script, I will check again.
>
> But in addition to that, we realised that git happily ignores settings
> for --stat. So, please, execute aforementioned script, but then
> generate v3 with --stat=1000 --stat-graph-width=20.
>
Ok. I will follow these steps as well.
> For this particular patch, the side discussion on the edk2 portion may
> make it redundant, so I'm deferring review.
Right now, I am yet to work on the review comments of other edk2 patch
and since it touches other platforms as well, it requires thorough vetting from other
platform maintainers. It seems like that would take more time. If I send this patch
series without removing DuartLib (i.e. drop patches 7, 8, 9 from this series), can you
please merge. Parallelly, I will work on edk2 patch and once that is accepted, I will send
patches 7, 8, 9 after that in new series ?
>
> /
> Leif
>
> > 2 files changed, 53 insertions(+)
> > create mode 100644
> Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> > create mode 100644
> Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> >
> > diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> > new file mode 100644
> > index 000000000000..9d49d7b4748b
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> > @@ -0,0 +1,27 @@
> > +/** @file
> > +*
> > +* Copyright 2020 NXP
> > +*
> > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > +*
> > +**/
> > +
> > +#include <Base.h>
> > +
> > +extern
> > +UINT64
> > +GetBusFrequency (
> > + VOID
> > + );
> > +
> > +/**
> > + Return clock in for Uart IP
> > +**/
> > +UINT32
> > +EFIAPI
> > +BaseSerialPortGetClock (
> > + VOID
> > + )
> > +{
> > + return GetBusFrequency ();
> > +}
> > diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> > new file mode 100644
> > index 000000000000..9a3e80cf521d
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> > @@ -0,0 +1,26 @@
> > +# @file
> > +# Copyright 2020 NXP
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 1.27
> > + BASE_NAME = SerialUartClockLib
> > + FILE_GUID = fa65495e-d3c8-4ea3-9737-994e9ccbaf11
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = SerialUartClockLib
> > +
> > +[Packages]
> > + MdeModulePkg/MdeModulePkg.dec
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[Sources.common]
> > + SerialUartClockLib.c
> > +
> > +[LibraryClasses]
> > + SocLib
> > +
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
2020-04-06 6:33 ` Pankaj Bansal
@ 2020-04-06 11:24 ` Leif Lindholm
2020-04-09 7:44 ` [EXT] " Varun Sethi
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-06 11:24 UTC (permalink / raw)
To: Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
On Mon, Apr 06, 2020 at 06:33:40 +0000, Pankaj Bansal (OSS) wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Wednesday, April 1, 2020 3:23 PM
> > To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> > <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> > <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> > Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> > Subject: Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
> >
> > On Fri, Mar 20, 2020 at 20:05:22 +0530, Pankaj Bansal wrote:
> > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > >
> > > Implement SerialUartClockLib for all NXP Layerscape Platforms.
> > >
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > ---
> > > .../SerialUartClockLib/SerialUartClockLib.c | 27 +++++++++++++++++++
> > > .../SerialUartClockLib/SerialUartClockLib.inf | 26 ++++++++++++++++++
> >
> > I requested after the initial submission that you "either follow the
> > manual git setup steps from
> > https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-
> > git-guide-for-edk2-contributors-and-maintainers
> > or execute edk2/BaseTools/Scripts/SetupGit.py in each of the tianocore
> > repositories"
> >
> > Now, neither appears to have happened, as .c still comes before .inf
> > and paths are still truncated.
>
> I had executed the SetupGit.py script, I will check again.
>
> >
> > But in addition to that, we realised that git happily ignores settings
> > for --stat. So, please, execute aforementioned script, but then
> > generate v3 with --stat=1000 --stat-graph-width=20.
> >
>
> Ok. I will follow these steps as well.
>
> > For this particular patch, the side discussion on the edk2 portion may
> > make it redundant, so I'm deferring review.
>
> Right now, I am yet to work on the review comments of other edk2 patch
> and since it touches other platforms as well, it requires thorough vetting from other
> platform maintainers. It seems like that would take more time. If I send this patch
> series without removing DuartLib (i.e. drop patches 7, 8, 9 from this series), can you
> please merge. Parallelly, I will work on edk2 patch and once that is accepted, I will send
> patches 7, 8, 9 after that in new series ?
See comment in my previous email on merging code only to remove it
shortly afterwards.
As you have seen on that thread, a couple of proposals have been made
for how to fix this without affecting other platforms (the HOB variant[1]
and the separate .inf[2] variant). I will keep chasing on that
occasionally, but please also contribute to that conversation yourself.
/
Leif
[1] https://edk2.groups.io/g/devel/message/56605
[2] https://edk2.groups.io/g/devel/message/56767
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [EXT] Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
2020-04-06 11:24 ` Leif Lindholm
@ 2020-04-09 7:44 ` Varun Sethi
2020-04-09 10:46 ` Leif Lindholm
0 siblings, 1 reply; 81+ messages in thread
From: Varun Sethi @ 2020-04-09 7:44 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Samer El-Haj-Mahmoud, Jon Nettleton
Hi Leif,
Please find my comments inline.
Regards
Varun
-----Original Message-----
From: Leif Lindholm <leif@nuviainc.com>
Sent: Monday, April 6, 2020 4:55 PM
To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
Subject: [EXT] Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
Caution: EXT Email
On Mon, Apr 06, 2020 at 06:33:40 +0000, Pankaj Bansal (OSS) wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Wednesday, April 1, 2020 3:23 PM
> > To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D
> > Kinney <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun
> > Sethi <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> > Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> > Subject: Re: [PATCH v2 07/28] Silicon/NXP: Implement
> > SerialUartClockLib
> >
> > On Fri, Mar 20, 2020 at 20:05:22 +0530, Pankaj Bansal wrote:
> > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > >
> > > Implement SerialUartClockLib for all NXP Layerscape Platforms.
> > >
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > ---
> > > .../SerialUartClockLib/SerialUartClockLib.c | 27 +++++++++++++++++++
> > > .../SerialUartClockLib/SerialUartClockLib.inf | 26
> > > ++++++++++++++++++
> >
> > I requested after the initial submission that you "either follow the
> > manual git setup steps from
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgi
> > thub.com%2Ftianocore%2Ftianocore.github.io%2Fwiki%2FLaszlo%2527s-unk
> > empt-&data=02%7C01%7CV.Sethi%40nxp.com%7C147ef25a5d6e4a0c899408d
> > 7da1d2288%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6372176909755
> > 41422&sdata=6A%2Bg1jAmhpu9p%2FISIddejL0dhzQs%2FS%2BqbYCXtgPAUfk%
> > 3D&reserved=0 git-guide-for-edk2-contributors-and-maintainers
> > or execute edk2/BaseTools/Scripts/SetupGit.py in each of the
> > tianocore repositories"
> >
> > Now, neither appears to have happened, as .c still comes before .inf
> > and paths are still truncated.
>
> I had executed the SetupGit.py script, I will check again.
>
> >
> > But in addition to that, we realised that git happily ignores
> > settings for --stat. So, please, execute aforementioned script, but
> > then generate v3 with --stat=1000 --stat-graph-width=20.
> >
>
> Ok. I will follow these steps as well.
>
> > For this particular patch, the side discussion on the edk2 portion
> > may make it redundant, so I'm deferring review.
>
> Right now, I am yet to work on the review comments of other edk2 patch
> and since it touches other platforms as well, it requires thorough
> vetting from other platform maintainers. It seems like that would take
> more time. If I send this patch series without removing DuartLib (i.e.
> drop patches 7, 8, 9 from this series), can you please merge.
> Parallelly, I will work on edk2 patch and once that is accepted, I will send patches 7, 8, 9 after that in new series ?
>See comment in my previous email on merging code only to remove it shortly afterwards.
We will certainly take of this going forward.
>As you have seen on that thread, a couple of proposals have been made for how to fix this without affecting other platforms (the HOB variant[1] and the separate .inf[2] variant). I will keep chasing on that >occasionally, but please also contribute to that conversation yourself.
Pankaj would be responding to this thread and make changes accordingly. Please allow us to pursue this patchset as a separate thread. We need the base patches to be merged asap so that we can submit patches for LX2160A and LS1046A. We have urgent releases planned for these platforms.
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
2020-04-09 7:44 ` [EXT] " Varun Sethi
@ 2020-04-09 10:46 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-09 10:46 UTC (permalink / raw)
To: Varun Sethi
Cc: Pankaj Bansal (OSS), Meenakshi Aggarwal, Michael D Kinney,
devel@edk2.groups.io, Samer El-Haj-Mahmoud, Jon Nettleton
On Thu, Apr 09, 2020 at 07:44:48 +0000, Varun Sethi wrote:
> > > Now, neither appears to have happened, as .c still comes before .inf
> > > and paths are still truncated.
> >
> > I had executed the SetupGit.py script, I will check again.
> >
> > > But in addition to that, we realised that git happily ignores
> > > settings for --stat. So, please, execute aforementioned script, but
> > > then generate v3 with --stat=1000 --stat-graph-width=20.
> >
> > Ok. I will follow these steps as well.
> >
> > > For this particular patch, the side discussion on the edk2 portion
> > > may make it redundant, so I'm deferring review.
> >
> > Right now, I am yet to work on the review comments of other edk2 patch
> > and since it touches other platforms as well, it requires thorough
> > vetting from other platform maintainers. It seems like that would take
> > more time. If I send this patch series without removing DuartLib (i.e.
> > drop patches 7, 8, 9 from this series), can you please merge.
> > Parallelly, I will work on edk2 patch and once that is accepted, I
> > will send patches 7, 8, 9 after that in new series ?
>
> >See comment in my previous email on merging code only to remove it
> >shortly afterwards.
>
> We will certainly take of this going forward.
>
> >As you have seen on that thread, a couple of proposals have been
> >made for how to fix this without affecting other platforms (the HOB
> >variant[1] and the separate .inf[2] variant). I will keep chasing
> >on that >occasionally, but please also contribute to that
> >conversation yourself.
>
> Pankaj would be responding to this thread and make changes
> accordingly. Please allow us to pursue this patchset as a separate
> thread. We need the base patches to be merged asap so that we can
> submit patches for LX2160A and LS1046A. We have urgent releases
> planned for these platforms.
I (intimately) understand the situation you're in, but we cannot
compromise normal development process of the upstream project due to
project plans of individual contributors.
My suggestion is that if this is holding your release back, then drop
the console changes completely from this set and do your release based
on upstream plus specifically those patches cherry-picked on top.
I would not (for example) mind those patches being sent out to the
list with a --subject-prefix of "DO NOT MERGE edk2-platforms" instead
of "PATCH edk2-platforms". While staying close to upstream is both
laudable and more efficient, productising based *only* on upstream is
... shall we say extremely optimistic.
If you prepare to do the cherry-pick solution, then you can very
quickly revert that and use upstream only if the full solution gets
there in time.
/
Leif
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib
2020-04-01 9:53 ` Leif Lindholm
2020-04-06 6:33 ` Pankaj Bansal
@ 2020-04-13 3:00 ` Pankaj Bansal
1 sibling, 0 replies; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-13 3:00 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> > ---
> > .../SerialUartClockLib/SerialUartClockLib.c | 27 +++++++++++++++++++
> > .../SerialUartClockLib/SerialUartClockLib.inf | 26 ++++++++++++++++++
>
> I requested after the initial submission that you "either follow the
> manual git setup steps from
> https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-
> git-guide-for-edk2-contributors-and-maintainers
> or execute edk2/BaseTools/Scripts/SetupGit.py in each of the tianocore
> repositories"
>
> Now, neither appears to have happened, as .c still comes before .inf
> and paths are still truncated.
>
> But in addition to that, we realised that git happily ignores settings
> for --stat. So, please, execute aforementioned script, but then
> generate v3 with --stat=1000 --stat-graph-width=20.
>
I am preparing the v3 of patches, and I am still seeing this issue after running SetupGit.py again.
After some tinkering I figured out the problem.
The git diff is ignoring the diff.Orderfile
The reason is line ending of edk2/BaseTools/Conf/diff.order
The current line ending of diff.order is windows, while I am using Linux to prepare patches.
If I change it to unix (dos2unix), then git is able to show proper diff
I wonder if same problem is with edk2/BaseTools/Conf/gitattributes ?
Looks like SetupGit.py needs to be modified to take into account the git running environment.
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 08/28] Silicon/NXP/LS1043A: Use BaseSerialPortLib16550 as SerialPortLib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (6 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 07/28] Silicon/NXP: Implement SerialUartClockLib Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 9:54 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 09/28] Silicon/NXP: Drop DUartPortLib Pankaj Bansal
` (21 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
UART Programming model in LS1043A is compatible with PC16550D.
Therefore, BaseSerialPortLib16550 can be used instead of our own
implementation of SerialPortLib.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/NxpQoriqLs.dsc.inc | 3 +++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 5 ++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 94d3e53a046b..234a5e2707cd 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -98,6 +98,9 @@ [LibraryClasses.common]
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index d2d4133428c3..f6f15a482a85 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -8,8 +8,10 @@
#
[LibraryClasses.common]
+ PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
- SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ SerialUartClockLib|Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
+ SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
################################################################################
#
@@ -25,6 +27,7 @@ [PcdsDynamicDefault.common]
[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
#
# CCSR Address Space and other attached Memories
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 08/28] Silicon/NXP/LS1043A: Use BaseSerialPortLib16550 as SerialPortLib
2020-03-20 14:35 ` [PATCH v2 08/28] Silicon/NXP/LS1043A: Use BaseSerialPortLib16550 as SerialPortLib Pankaj Bansal
@ 2020-04-01 9:54 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 9:54 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:23 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> UART Programming model in LS1043A is compatible with PC16550D.
> Therefore, BaseSerialPortLib16550 can be used instead of our own
> implementation of SerialPortLib.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
(If the need for SerialUartClockLib goes away, that line can be
dropped without re-review being required.)
> ---
> Platform/NXP/NxpQoriqLs.dsc.inc | 3 +++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 5 ++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> index 94d3e53a046b..234a5e2707cd 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -98,6 +98,9 @@ [LibraryClasses.common]
> ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
>
> + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
> +
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index d2d4133428c3..f6f15a482a85 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -8,8 +8,10 @@
> #
>
> [LibraryClasses.common]
> + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
> SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> - SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + SerialUartClockLib|Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
>
> ################################################################################
> #
> @@ -25,6 +27,7 @@ [PcdsDynamicDefault.common]
>
> [PcdsFixedAtBuild.common]
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
>
> #
> # CCSR Address Space and other attached Memories
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 09/28] Silicon/NXP: Drop DUartPortLib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (7 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 08/28] Silicon/NXP/LS1043A: Use BaseSerialPortLib16550 as SerialPortLib Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 9:55 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 10/28] Silicon/NXP: remove print information from Soc lib Pankaj Bansal
` (20 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
DUartPortLib is for ns16550 compatible UART in LS1043A. Therefore, we can
remove it and use BaseSerialPortLib16550.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ------
.../NXP/Library/DUartPortLib/DUartPortLib.c | 364 ------------------
.../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 --
3 files changed, 520 deletions(-)
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
deleted file mode 100644
index c71e2ce55d1d..000000000000
--- a/Silicon/NXP/Library/DUartPortLib/DUart.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/** DUart.h
-* Header defining the DUART constants (Base addresses, sizes, flags)
-*
-* Based on Serial I/O Port library headers available in PL011Uart.h
-*
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef DUART_H_
-#define DUART_H_
-
-// FIFO Control Register
-#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
-#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
-#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
-#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
-#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
-#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
-#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
-#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
-#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
-
-// Modem Control Register
-#define DUART_MCR_DTR 0x01 /* Reserved */
-#define DUART_MCR_RTS 0x02 /* RTS */
-#define DUART_MCR_OUT1 0x04 /* Reserved */
-#define DUART_MCR_OUT2 0x08 /* Reserved */
-#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
-#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
-#define DUART_MCR_DMA_EN 0x04
-#define DUART_MCR_TX_DFR 0x08
-
-// Line Control Register
-/*
-* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
-* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
-*/
-#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
-#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
-#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
-#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
-#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
-#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
-#define DUART_LCR_PEN 0x08 /* Parity eneble */
-#define DUART_LCR_EPS 0x10 /* Even Parity Select */
-#define DUART_LCR_STKP 0x20 /* Stick Parity */
-#define DUART_LCR_SBRK 0x40 /* Set Break */
-#define DUART_LCR_BKSE 0x80 /* Bank select enable */
-#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
-
-// Line Status Register
-#define DUART_LSR_DR 0x01 /* Data ready */
-#define DUART_LSR_OE 0x02 /* Overrun */
-#define DUART_LSR_PE 0x04 /* Parity error */
-#define DUART_LSR_FE 0x08 /* Framing error */
-#define DUART_LSR_BI 0x10 /* Break */
-#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
-#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
-#define DUART_LSR_ERR 0x80 /* Error */
-
-// Modem Status Register
-#define DUART_MSR_DCTS 0x01 /* Delta CTS */
-#define DUART_MSR_DDSR 0x02 /* Reserved */
-#define DUART_MSR_TERI 0x04 /* Reserved */
-#define DUART_MSR_DDCD 0x08 /* Reserved */
-#define DUART_MSR_CTS 0x10 /* Clear to Send */
-#define DUART_MSR_DSR 0x20 /* Reserved */
-#define DUART_MSR_RI 0x40 /* Reserved */
-#define DUART_MSR_DCD 0x80 /* Reserved */
-
-// Interrupt Identification Register
-#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
-#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
-#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
-#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
-#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
-#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
-
-// Interrupt Enable Register
-#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
-#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
-#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
-#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
-
-// LCR defaults
-#define DUART_LCR_8N1 0x03
-#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
-#define DUART_MCRVAL (DUART_MCR_DTR | \
- DUART_MCR_RTS) /* RTS/DTR */
-#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
- DUART_FCR_RXSR | \
- DUART_FCR_TXSR) /* Clear & enable FIFOs */
-
-#define URBR 0x0
-#define UTHR 0x0
-#define UDLB 0x0
-#define UDMB 0x1
-#define UIER 0x1
-#define UIIR 0x2
-#define UFCR 0x2
-#define UAFR 0x2
-#define ULCR 0x3
-#define UMCR 0x4
-#define ULSR 0x5
-#define UMSR 0x6
-#define USCR 0x7
-#define UDSR 0x10
-
-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
-#endif /* DUART_H_ */
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
deleted file mode 100644
index c3c738d3cca8..000000000000
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/** DuartPortLib.c
- DUART (NS16550) library functions
-
- Based on Serial I/O Port library functions available in PL011SerialPortLib.c
-
- Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
- Copyright 2017 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/SerialPortLib.h>
-
-#include "DUart.h"
-
-STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
- EFI_SERIAL_DATA_TERMINAL_READY);
-
-/**
- Assert or deassert the control signals on a serial port.
- The following control signals are set according their bit settings :
- . Request to Send
- . Data Terminal Ready
-
- @param[in] Control The following bits are taken into account :
- . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
- "Request To Send" control signal if this bit is
- equal to one/zero.
- . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
- the "Data Terminal Ready" control signal if this
- bit is equal to one/zero.
- . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
- the hardware loopback if this bit is equal to
- one/zero.
- . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
- . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
- disable the hardware flow control based on CTS (Clear
- To Send) and RTS (Ready To Send) control signals.
-
- @retval EFI_SUCCESS The new control bits were set on the device.
- @retval EFI_UNSUPPORTED The device does not support this operation.
-
-**/
-EFI_STATUS
-EFIAPI
-SerialPortSetControl (
- IN UINT32 Control
- )
-{
- UINT32 McrBits;
- UINTN UartBase;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- if (Control & (mInvalidControlBits)) {
- return EFI_UNSUPPORTED;
- }
-
- McrBits = MmioRead8 (UartBase + UMCR);
-
- if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
- McrBits |= DUART_MCR_RTS;
- } else {
- McrBits &= ~DUART_MCR_RTS;
- }
-
- if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
- McrBits |= DUART_MCR_LOOP;
- } else {
- McrBits &= ~DUART_MCR_LOOP;
- }
-
- if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
- McrBits |= DUART_MCR_AFE;
- } else {
- McrBits &= ~DUART_MCR_AFE;
- }
-
- MmioWrite32 (UartBase + UMCR, McrBits);
-
- return EFI_SUCCESS;
-}
-
-/**
- Retrieve the status of the control bits on a serial device.
-
- @param[out] Control Status of the control bits on a serial device :
-
- . EFI_SERIAL_DATA_CLEAR_TO_SEND,
- EFI_SERIAL_DATA_SET_READY,
- EFI_SERIAL_RING_INDICATE,
- EFI_SERIAL_CARRIER_DETECT,
- EFI_SERIAL_REQUEST_TO_SEND,
- EFI_SERIAL_DATA_TERMINAL_READY
- are all related to the DTE (Data Terminal Equipment)
- and DCE (Data Communication Equipment) modes of
- operation of the serial device.
- . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
- receive buffer is empty, 0 otherwise.
- . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
- transmit buffer is empty, 0 otherwise.
- . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
- the hardware loopback is enabled (the ouput feeds the
- receive buffer), 0 otherwise.
- . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
- a loopback is accomplished by software, 0 otherwise.
- . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
- one if the hardware flow control based on CTS (Clear
- To Send) and RTS (Ready To Send) control signals is
- enabled, 0 otherwise.
-
- @retval EFI_SUCCESS The control bits were read from the serial device.
-
-**/
-EFI_STATUS
-EFIAPI
-SerialPortGetControl (
- OUT UINT32 *Control
- )
-{
- UINT32 MsrRegister;
- UINT32 McrRegister;
- UINT32 LsrRegister;
- UINTN UartBase;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- MsrRegister = MmioRead8 (UartBase + UMSR);
- McrRegister = MmioRead8 (UartBase + UMCR);
- LsrRegister = MmioRead8 (UartBase + ULSR);
-
- *Control = 0;
-
- if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
- *Control |= EFI_SERIAL_CLEAR_TO_SEND;
- }
-
- if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
- *Control |= EFI_SERIAL_REQUEST_TO_SEND;
- }
-
- if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
- *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
- }
-
- if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
- *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
- }
-
- if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
- *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
- }
-
- return EFI_SUCCESS;
-}
-
-/*
- * Return Baud divisor on basis of Baudrate
- */
-UINT32
-CalculateBaudDivisor (
- IN UINT64 BaudRate
- )
-{
- UINTN DUartClk;
- UINTN FreqSystemBus;
-
- FreqSystemBus = GetBusFrequency ();
- DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
-
- return ((DUartClk)/(BaudRate * 16));
-}
-
-/*
- Initialise the serial port to the specified settings.
- All unspecified settings will be set to the default values.
-
- @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
-
- **/
-VOID
-EFIAPI
-DuartInitializePort (
- IN UINT64 BaudRate
- )
-{
- UINTN UartBase;
- UINT32 BaudDivisor;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
- BaudDivisor = CalculateBaudDivisor (BaudRate);
-
-
- while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
-
- //
- // Enable and assert interrupt when new data is available on
- // external device,
- // setup data format, setup baud divisor
- //
- MmioWrite8 (UartBase + UIER, 0x1);
- MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
- MmioWrite8 (UartBase + UDLB, 0);
- MmioWrite8 (UartBase + UDMB, 0);
- MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
- MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
- MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
- MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
- MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
- MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
- MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
-
- return;
-}
-
-/**
- Programmed hardware of Serial port.
-
- @return Always return EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-SerialPortInitialize (
- VOID
- )
-{
- UINT64 BaudRate;
- BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
-
-
- DuartInitializePort (BaudRate);
-
- return EFI_SUCCESS;
-}
-
-/**
- Write data to serial device.
-
- @param Buffer Point of data buffer which need to be written.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Write data failed.
- @retval !0 Actual number of bytes written to serial device.
-
-**/
-UINTN
-EFIAPI
-SerialPortWrite (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
- )
-{
- UINT8 *Final;
- UINTN UartBase;
-
- Final = &Buffer[NumberOfBytes];
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- while (Buffer < Final) {
- while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
- MmioWrite8 (UartBase + UTHR, *Buffer++);
- }
-
- return NumberOfBytes;
-}
-
-/**
- Read data from serial device and save the data in buffer.
-
- @param Buffer Point of data buffer which need to be written.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Read data failed.
- @retval !0 Actual number of bytes read from serial device.
-
-**/
-UINTN
-EFIAPI
-SerialPortRead (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
- )
-{
- UINTN Count;
- UINTN UartBase;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
- // Loop while waiting for a new char(s) to arrive in the
- // RxFIFO
- while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
-
- *Buffer = MmioRead8 (UartBase + URBR);
- }
-
- return NumberOfBytes;
-}
-
-/**
- Check to see if any data is available to be read from the debug device.
-
- @retval EFI_SUCCESS At least one byte of data is available to be read
- @retval EFI_NOT_READY No data is available to be read
- @retval EFI_DEVICE_ERROR The serial device is not functioning properly
-
-**/
-BOOLEAN
-EFIAPI
-SerialPortPoll (
- VOID
- )
-{
- UINTN UartBase;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
-}
-
-/**
- Set new attributes to LS1043a.
-
- @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
- the speed will be reduced down to the nearest supported one and the
- variable's value will be updated accordingly.
- @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
- value is not supported, the variable's value will be reduced down to the
- nearest supported one.
- @param Timeout If applicable, the number of microseconds the device will wait
- before timing out a Read or a Write operation.
- @param Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked
- as each character is transmitted or received. If the device does not
- support parity, the value is the default parity value.
- @param DataBits The number of data bits in each character
- @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
- If the device does not support stop bits, the value is the default stop
- bit value.
-
- @retval EFI_SUCCESS All attributes were set correctly on the serial device.
-
-**/
-EFI_STATUS
-EFIAPI
-SerialPortSetAttributes (
- IN OUT UINT64 *BaudRate,
- IN OUT UINT32 *ReceiveFifoDepth,
- IN OUT UINT32 *Timeout,
- IN OUT EFI_PARITY_TYPE *Parity,
- IN OUT UINT8 *DataBits,
- IN OUT EFI_STOP_BITS_TYPE *StopBits
- )
-{
- DuartInitializePort (*BaudRate);
-
- return EFI_SUCCESS;
-}
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
deleted file mode 100644
index 7a2fa619b027..000000000000
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+++ /dev/null
@@ -1,34 +0,0 @@
-# DUartPortLib.inf
-#
-# Component description file for DUartPortLib module
-#
-# Copyright (c) 2013, Freescale Ltd. All rights reserved.
-# Copyright 2017 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = DUartPortLib
- FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SerialPortLib
-
-[Sources.common]
- DUartPortLib.c
-
-[LibraryClasses]
- PcdLib
- SocLib
-
-[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Silicon/NXP/NxpQoriqLs.dec
-
-[Pcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 09/28] Silicon/NXP: Drop DUartPortLib
2020-03-20 14:35 ` [PATCH v2 09/28] Silicon/NXP: Drop DUartPortLib Pankaj Bansal
@ 2020-04-01 9:55 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 9:55 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:24 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> DUartPortLib is for ns16550 compatible UART in LS1043A. Therefore, we can
> remove it and use BaseSerialPortLib16550.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ------
> .../NXP/Library/DUartPortLib/DUartPortLib.c | 364 ------------------
> .../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 --
> 3 files changed, 520 deletions(-)
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
>
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
> deleted file mode 100644
> index c71e2ce55d1d..000000000000
> --- a/Silicon/NXP/Library/DUartPortLib/DUart.h
> +++ /dev/null
> @@ -1,122 +0,0 @@
> -/** DUart.h
> -* Header defining the DUART constants (Base addresses, sizes, flags)
> -*
> -* Based on Serial I/O Port library headers available in PL011Uart.h
> -*
> -* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> -* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> -* Copyright 2017 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef DUART_H_
> -#define DUART_H_
> -
> -// FIFO Control Register
> -#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
> -#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
> -#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
> -#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
> -#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
> -#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
> -#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
> -#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
> -#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
> -#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
> -#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
> -
> -// Modem Control Register
> -#define DUART_MCR_DTR 0x01 /* Reserved */
> -#define DUART_MCR_RTS 0x02 /* RTS */
> -#define DUART_MCR_OUT1 0x04 /* Reserved */
> -#define DUART_MCR_OUT2 0x08 /* Reserved */
> -#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
> -#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
> -#define DUART_MCR_DMA_EN 0x04
> -#define DUART_MCR_TX_DFR 0x08
> -
> -// Line Control Register
> -/*
> -* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
> -* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
> -*/
> -#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
> -#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
> -#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
> -#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
> -#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
> -#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
> -#define DUART_LCR_PEN 0x08 /* Parity eneble */
> -#define DUART_LCR_EPS 0x10 /* Even Parity Select */
> -#define DUART_LCR_STKP 0x20 /* Stick Parity */
> -#define DUART_LCR_SBRK 0x40 /* Set Break */
> -#define DUART_LCR_BKSE 0x80 /* Bank select enable */
> -#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
> -
> -// Line Status Register
> -#define DUART_LSR_DR 0x01 /* Data ready */
> -#define DUART_LSR_OE 0x02 /* Overrun */
> -#define DUART_LSR_PE 0x04 /* Parity error */
> -#define DUART_LSR_FE 0x08 /* Framing error */
> -#define DUART_LSR_BI 0x10 /* Break */
> -#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
> -#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
> -#define DUART_LSR_ERR 0x80 /* Error */
> -
> -// Modem Status Register
> -#define DUART_MSR_DCTS 0x01 /* Delta CTS */
> -#define DUART_MSR_DDSR 0x02 /* Reserved */
> -#define DUART_MSR_TERI 0x04 /* Reserved */
> -#define DUART_MSR_DDCD 0x08 /* Reserved */
> -#define DUART_MSR_CTS 0x10 /* Clear to Send */
> -#define DUART_MSR_DSR 0x20 /* Reserved */
> -#define DUART_MSR_RI 0x40 /* Reserved */
> -#define DUART_MSR_DCD 0x80 /* Reserved */
> -
> -// Interrupt Identification Register
> -#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
> -#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
> -#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
> -#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
> -#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
> -#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
> -
> -// Interrupt Enable Register
> -#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
> -#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
> -#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
> -#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
> -
> -// LCR defaults
> -#define DUART_LCR_8N1 0x03
> -#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
> -#define DUART_MCRVAL (DUART_MCR_DTR | \
> - DUART_MCR_RTS) /* RTS/DTR */
> -#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
> - DUART_FCR_RXSR | \
> - DUART_FCR_TXSR) /* Clear & enable FIFOs */
> -
> -#define URBR 0x0
> -#define UTHR 0x0
> -#define UDLB 0x0
> -#define UDMB 0x1
> -#define UIER 0x1
> -#define UIIR 0x2
> -#define UFCR 0x2
> -#define UAFR 0x2
> -#define ULCR 0x3
> -#define UMCR 0x4
> -#define ULSR 0x5
> -#define UMSR 0x6
> -#define USCR 0x7
> -#define UDSR 0x10
> -
> -extern
> -UINT64
> -GetBusFrequency (
> - VOID
> - );
> -
> -#endif /* DUART_H_ */
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> deleted file mode 100644
> index c3c738d3cca8..000000000000
> --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> +++ /dev/null
> @@ -1,364 +0,0 @@
> -/** DuartPortLib.c
> - DUART (NS16550) library functions
> -
> - Based on Serial I/O Port library functions available in PL011SerialPortLib.c
> -
> - Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> - Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
> - Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> - Copyright 2017 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/SerialPortLib.h>
> -
> -#include "DUart.h"
> -
> -STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
> - EFI_SERIAL_DATA_TERMINAL_READY);
> -
> -/**
> - Assert or deassert the control signals on a serial port.
> - The following control signals are set according their bit settings :
> - . Request to Send
> - . Data Terminal Ready
> -
> - @param[in] Control The following bits are taken into account :
> - . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
> - "Request To Send" control signal if this bit is
> - equal to one/zero.
> - . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
> - the "Data Terminal Ready" control signal if this
> - bit is equal to one/zero.
> - . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
> - the hardware loopback if this bit is equal to
> - one/zero.
> - . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
> - . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
> - disable the hardware flow control based on CTS (Clear
> - To Send) and RTS (Ready To Send) control signals.
> -
> - @retval EFI_SUCCESS The new control bits were set on the device.
> - @retval EFI_UNSUPPORTED The device does not support this operation.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SerialPortSetControl (
> - IN UINT32 Control
> - )
> -{
> - UINT32 McrBits;
> - UINTN UartBase;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - if (Control & (mInvalidControlBits)) {
> - return EFI_UNSUPPORTED;
> - }
> -
> - McrBits = MmioRead8 (UartBase + UMCR);
> -
> - if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
> - McrBits |= DUART_MCR_RTS;
> - } else {
> - McrBits &= ~DUART_MCR_RTS;
> - }
> -
> - if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
> - McrBits |= DUART_MCR_LOOP;
> - } else {
> - McrBits &= ~DUART_MCR_LOOP;
> - }
> -
> - if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
> - McrBits |= DUART_MCR_AFE;
> - } else {
> - McrBits &= ~DUART_MCR_AFE;
> - }
> -
> - MmioWrite32 (UartBase + UMCR, McrBits);
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Retrieve the status of the control bits on a serial device.
> -
> - @param[out] Control Status of the control bits on a serial device :
> -
> - . EFI_SERIAL_DATA_CLEAR_TO_SEND,
> - EFI_SERIAL_DATA_SET_READY,
> - EFI_SERIAL_RING_INDICATE,
> - EFI_SERIAL_CARRIER_DETECT,
> - EFI_SERIAL_REQUEST_TO_SEND,
> - EFI_SERIAL_DATA_TERMINAL_READY
> - are all related to the DTE (Data Terminal Equipment)
> - and DCE (Data Communication Equipment) modes of
> - operation of the serial device.
> - . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
> - receive buffer is empty, 0 otherwise.
> - . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
> - transmit buffer is empty, 0 otherwise.
> - . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
> - the hardware loopback is enabled (the ouput feeds the
> - receive buffer), 0 otherwise.
> - . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
> - a loopback is accomplished by software, 0 otherwise.
> - . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
> - one if the hardware flow control based on CTS (Clear
> - To Send) and RTS (Ready To Send) control signals is
> - enabled, 0 otherwise.
> -
> - @retval EFI_SUCCESS The control bits were read from the serial device.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SerialPortGetControl (
> - OUT UINT32 *Control
> - )
> -{
> - UINT32 MsrRegister;
> - UINT32 McrRegister;
> - UINT32 LsrRegister;
> - UINTN UartBase;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - MsrRegister = MmioRead8 (UartBase + UMSR);
> - McrRegister = MmioRead8 (UartBase + UMCR);
> - LsrRegister = MmioRead8 (UartBase + ULSR);
> -
> - *Control = 0;
> -
> - if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
> - *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> - }
> -
> - if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
> - *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> - }
> -
> - if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
> - *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> - }
> -
> - if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
> - *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> - }
> -
> - if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
> - *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> -/*
> - * Return Baud divisor on basis of Baudrate
> - */
> -UINT32
> -CalculateBaudDivisor (
> - IN UINT64 BaudRate
> - )
> -{
> - UINTN DUartClk;
> - UINTN FreqSystemBus;
> -
> - FreqSystemBus = GetBusFrequency ();
> - DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
> -
> - return ((DUartClk)/(BaudRate * 16));
> -}
> -
> -/*
> - Initialise the serial port to the specified settings.
> - All unspecified settings will be set to the default values.
> -
> - @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
> -
> - **/
> -VOID
> -EFIAPI
> -DuartInitializePort (
> - IN UINT64 BaudRate
> - )
> -{
> - UINTN UartBase;
> - UINT32 BaudDivisor;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> - BaudDivisor = CalculateBaudDivisor (BaudRate);
> -
> -
> - while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
> -
> - //
> - // Enable and assert interrupt when new data is available on
> - // external device,
> - // setup data format, setup baud divisor
> - //
> - MmioWrite8 (UartBase + UIER, 0x1);
> - MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> - MmioWrite8 (UartBase + UDLB, 0);
> - MmioWrite8 (UartBase + UDMB, 0);
> - MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> - MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
> - MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
> - MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> - MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
> - MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
> - MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> -
> - return;
> -}
> -
> -/**
> - Programmed hardware of Serial port.
> -
> - @return Always return EFI_SUCCESS.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SerialPortInitialize (
> - VOID
> - )
> -{
> - UINT64 BaudRate;
> - BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
> -
> -
> - DuartInitializePort (BaudRate);
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Write data to serial device.
> -
> - @param Buffer Point of data buffer which need to be written.
> - @param NumberOfBytes Number of output bytes which are cached in Buffer.
> -
> - @retval 0 Write data failed.
> - @retval !0 Actual number of bytes written to serial device.
> -
> -**/
> -UINTN
> -EFIAPI
> -SerialPortWrite (
> - IN UINT8 *Buffer,
> - IN UINTN NumberOfBytes
> - )
> -{
> - UINT8 *Final;
> - UINTN UartBase;
> -
> - Final = &Buffer[NumberOfBytes];
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - while (Buffer < Final) {
> - while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
> - MmioWrite8 (UartBase + UTHR, *Buffer++);
> - }
> -
> - return NumberOfBytes;
> -}
> -
> -/**
> - Read data from serial device and save the data in buffer.
> -
> - @param Buffer Point of data buffer which need to be written.
> - @param NumberOfBytes Number of output bytes which are cached in Buffer.
> -
> - @retval 0 Read data failed.
> - @retval !0 Actual number of bytes read from serial device.
> -
> -**/
> -UINTN
> -EFIAPI
> -SerialPortRead (
> - OUT UINT8 *Buffer,
> - IN UINTN NumberOfBytes
> - )
> -{
> - UINTN Count;
> - UINTN UartBase;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
> - // Loop while waiting for a new char(s) to arrive in the
> - // RxFIFO
> - while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
> -
> - *Buffer = MmioRead8 (UartBase + URBR);
> - }
> -
> - return NumberOfBytes;
> -}
> -
> -/**
> - Check to see if any data is available to be read from the debug device.
> -
> - @retval EFI_SUCCESS At least one byte of data is available to be read
> - @retval EFI_NOT_READY No data is available to be read
> - @retval EFI_DEVICE_ERROR The serial device is not functioning properly
> -
> -**/
> -BOOLEAN
> -EFIAPI
> -SerialPortPoll (
> - VOID
> - )
> -{
> - UINTN UartBase;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
> -}
> -
> -/**
> - Set new attributes to LS1043a.
> -
> - @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
> - the speed will be reduced down to the nearest supported one and the
> - variable's value will be updated accordingly.
> - @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
> - value is not supported, the variable's value will be reduced down to the
> - nearest supported one.
> - @param Timeout If applicable, the number of microseconds the device will wait
> - before timing out a Read or a Write operation.
> - @param Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked
> - as each character is transmitted or received. If the device does not
> - support parity, the value is the default parity value.
> - @param DataBits The number of data bits in each character
> - @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
> - If the device does not support stop bits, the value is the default stop
> - bit value.
> -
> - @retval EFI_SUCCESS All attributes were set correctly on the serial device.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SerialPortSetAttributes (
> - IN OUT UINT64 *BaudRate,
> - IN OUT UINT32 *ReceiveFifoDepth,
> - IN OUT UINT32 *Timeout,
> - IN OUT EFI_PARITY_TYPE *Parity,
> - IN OUT UINT8 *DataBits,
> - IN OUT EFI_STOP_BITS_TYPE *StopBits
> - )
> -{
> - DuartInitializePort (*BaudRate);
> -
> - return EFI_SUCCESS;
> -}
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> deleted file mode 100644
> index 7a2fa619b027..000000000000
> --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -# DUartPortLib.inf
> -#
> -# Component description file for DUartPortLib module
> -#
> -# Copyright (c) 2013, Freescale Ltd. All rights reserved.
> -# Copyright 2017 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -
> -[Defines]
> - INF_VERSION = 0x0001001A
> - BASE_NAME = DUartPortLib
> - FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = SerialPortLib
> -
> -[Sources.common]
> - DUartPortLib.c
> -
> -[LibraryClasses]
> - PcdLib
> - SocLib
> -
> -[Packages]
> - MdeModulePkg/MdeModulePkg.dec
> - MdePkg/MdePkg.dec
> - Silicon/NXP/NxpQoriqLs.dec
> -
> -[Pcd]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 10/28] Silicon/NXP: remove print information from Soc lib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (8 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 09/28] Silicon/NXP: Drop DUartPortLib Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 9:59 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 11/28] Silicon/NXP: remove not needed components Pankaj Bansal
` (19 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
The Soc info being printed can be removed from SOC lib.
We are in the process of implementing PEI Phase.
After PEI phase impelmentation this info would be printed in
common PEIM based on the information retrieved from PPIs.
e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and
core info.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Library/SocLib/Chassis.c | 132 ----------------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 16 +--
Silicon/NXP/Library/SocLib/NxpChassis.h | 26 +----
3 files changed, 2 insertions(+), 172 deletions(-)
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index b8a8118c5e24..2f192e890bcf 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -216,67 +216,6 @@ CpuMaskNext (
return Cpu;
}
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
- VOID
- )
-{
- SYS_INFO SysInfo;
- UINTN CoreIndex;
- UINTN Core;
- UINT32 Type;
- UINT32 NumCpus;
- UINT32 Mask;
- CHAR8 *CoreName;
-
- GetSysInfo (&SysInfo);
- DEBUG ((DEBUG_INIT, "Clock Configuration:"));
-
- NumCpus = CpuNumCores ();
- Mask = CpuMask ();
-
- for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
- CoreIndex < NumCpus;
- CoreIndex++, Core = CpuMaskNext(Core, Mask))
- {
- if (!(CoreIndex % 3)) {
- DEBUG ((DEBUG_INIT, "\n "));
- }
-
- Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
- switch (Type) {
- case TY_ITYP_VERSION_A7:
- CoreName = "A7";
- break;
- case TY_ITYP_VERSION_A53:
- CoreName = "A53";
- break;
- case TY_ITYP_VERSION_A57:
- CoreName = "A57";
- break;
- case TY_ITYP_VERSION_A72:
- CoreName = "A72";
- break;
- default:
- CoreName = " Unknown Core ";
- }
- DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
- Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
- }
-
- DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
- DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
-
- if (SysInfo.FreqFman[0] != 0) {
- DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
- }
-
- DEBUG ((DEBUG_INIT, "\n"));
-}
-
/*
* Return system bus frequency
*/
@@ -307,77 +246,6 @@ GetSdxcFrequency (
return SocSysInfo.FreqSdhc;
}
-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
- VOID
- )
-{
- CHAR8 Buf[20];
- CCSR_GUR *GurBase;
- UINTN Count;
- //
- // Svr : System Version Register
- //
- UINTN Svr;
- UINTN Ver;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- Svr = GurRead ((UINTN)&GurBase->Svr);
- Ver = SVR_SOC_VER (Svr);
-
- for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
- if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
- AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name);
-
- if (IS_E_PROCESSOR (Svr)) {
- AsciiStrCatS (Buf, sizeof (Buf), "E");
- }
- break;
- }
- }
-
- DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
- Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
-
- return;
-}
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
- VOID
- )
-{
- CCSR_GUR *Base;
- UINTN Count;
-
- Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- /*
- * Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
-
- DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
- for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
- UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
-
- if ((Count % 4) == 0) {
- DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
- }
-
- DEBUG ((DEBUG_INIT, " %08x", Rcw));
- }
-
- DEBUG ((DEBUG_INIT, "\n"));
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index bfb8b8cb339a..687a1d940066 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -1,7 +1,7 @@
/** @Soc.c
SoC specific Library containg functions to initialize various SoC components
- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -131,10 +131,6 @@ GetSysInfo (
/**
Function to initialize SoC specific constructs
- CPU Info
- SoC Personality
- Board Personality
- RCW prints
**/
VOID
SocInit (
@@ -147,16 +143,6 @@ SocInit (
// Early init serial Port to get board information.
//
SerialPortInitialize ();
- DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
- (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
-
- PrintCpuInfo ();
-
- //
- // Print Reset control Word
- //
- PrintRCW ();
- PrintSoc ();
return;
}
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
index 99f6439d8f35..a11acf71563e 100644
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
@@ -1,7 +1,7 @@
/** @file
* Header defining the Base addresses, sizes, flags etc for chassis 1
*
-* Copyright 2017-2019 NXP
+* Copyright 2017-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -54,14 +54,6 @@ typedef struct {
UINTN SdhcClk;
} SOC_CLOCK_INFO;
-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
- VOID
- );
-
/*
* Initialize Clock structure
*/
@@ -79,22 +71,6 @@ SmmuInit (
VOID
);
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
- VOID
- );
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
- VOID
- );
-
UINT32
InitiatorType (
IN UINT32 Cluster,
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 10/28] Silicon/NXP: remove print information from Soc lib
2020-03-20 14:35 ` [PATCH v2 10/28] Silicon/NXP: remove print information from Soc lib Pankaj Bansal
@ 2020-04-01 9:59 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 9:59 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:25 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> The Soc info being printed can be removed from SOC lib.
> We are in the process of implementing PEI Phase.
> After PEI phase impelmentation this info would be printed in
implementation
> common PEIM based on the information retrieved from PPIs.
> e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and
cluster
> core info.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
With the commit message typos fixed:
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/NXP/Library/SocLib/Chassis.c | 132 ----------------------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 16 +--
> Silicon/NXP/Library/SocLib/NxpChassis.h | 26 +----
> 3 files changed, 2 insertions(+), 172 deletions(-)
>
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index b8a8118c5e24..2f192e890bcf 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -216,67 +216,6 @@ CpuMaskNext (
> return Cpu;
> }
>
> -/*
> - * Print CPU information
> - */
> -VOID
> -PrintCpuInfo (
> - VOID
> - )
> -{
> - SYS_INFO SysInfo;
> - UINTN CoreIndex;
> - UINTN Core;
> - UINT32 Type;
> - UINT32 NumCpus;
> - UINT32 Mask;
> - CHAR8 *CoreName;
> -
> - GetSysInfo (&SysInfo);
> - DEBUG ((DEBUG_INIT, "Clock Configuration:"));
> -
> - NumCpus = CpuNumCores ();
> - Mask = CpuMask ();
> -
> - for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
> - CoreIndex < NumCpus;
> - CoreIndex++, Core = CpuMaskNext(Core, Mask))
> - {
> - if (!(CoreIndex % 3)) {
> - DEBUG ((DEBUG_INIT, "\n "));
> - }
> -
> - Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
> - switch (Type) {
> - case TY_ITYP_VERSION_A7:
> - CoreName = "A7";
> - break;
> - case TY_ITYP_VERSION_A53:
> - CoreName = "A53";
> - break;
> - case TY_ITYP_VERSION_A57:
> - CoreName = "A57";
> - break;
> - case TY_ITYP_VERSION_A72:
> - CoreName = "A72";
> - break;
> - default:
> - CoreName = " Unknown Core ";
> - }
> - DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
> - Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
> - }
> -
> - DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
> - DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
> -
> - if (SysInfo.FreqFman[0] != 0) {
> - DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
> - }
> -
> - DEBUG ((DEBUG_INIT, "\n"));
> -}
> -
> /*
> * Return system bus frequency
> */
> @@ -307,77 +246,6 @@ GetSdxcFrequency (
> return SocSysInfo.FreqSdhc;
> }
>
> -/*
> - * Print Soc information
> - */
> -VOID
> -PrintSoc (
> - VOID
> - )
> -{
> - CHAR8 Buf[20];
> - CCSR_GUR *GurBase;
> - UINTN Count;
> - //
> - // Svr : System Version Register
> - //
> - UINTN Svr;
> - UINTN Ver;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> -
> - Svr = GurRead ((UINTN)&GurBase->Svr);
> - Ver = SVR_SOC_VER (Svr);
> -
> - for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
> - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> - AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name);
> -
> - if (IS_E_PROCESSOR (Svr)) {
> - AsciiStrCatS (Buf, sizeof (Buf), "E");
> - }
> - break;
> - }
> - }
> -
> - DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
> - Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
> -
> - return;
> -}
> -
> -/*
> - * Dump RCW (Reset Control Word) on console
> - */
> -VOID
> -PrintRCW (
> - VOID
> - )
> -{
> - CCSR_GUR *Base;
> - UINTN Count;
> -
> - Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> -
> - /*
> - * Display the RCW, so that no one gets confused as to what RCW
> - * we're actually using for this boot.
> - */
> -
> - DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
> - for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
> - UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
> -
> - if ((Count % 4) == 0) {
> - DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
> - }
> -
> - DEBUG ((DEBUG_INIT, " %08x", Rcw));
> - }
> -
> - DEBUG ((DEBUG_INIT, "\n"));
> -}
> -
> /*
> * Setup SMMU in bypass mode
> * and also set its pagesize
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index bfb8b8cb339a..687a1d940066 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -1,7 +1,7 @@
> /** @Soc.c
> SoC specific Library containg functions to initialize various SoC components
>
> - Copyright 2017-2019 NXP
> + Copyright 2017-2020 NXP
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -131,10 +131,6 @@ GetSysInfo (
>
> /**
> Function to initialize SoC specific constructs
> - CPU Info
> - SoC Personality
> - Board Personality
> - RCW prints
> **/
> VOID
> SocInit (
> @@ -147,16 +143,6 @@ SocInit (
> // Early init serial Port to get board information.
> //
> SerialPortInitialize ();
> - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
> - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
> -
> - PrintCpuInfo ();
> -
> - //
> - // Print Reset control Word
> - //
> - PrintRCW ();
> - PrintSoc ();
>
> return;
> }
> diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
> index 99f6439d8f35..a11acf71563e 100644
> --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
> @@ -1,7 +1,7 @@
> /** @file
> * Header defining the Base addresses, sizes, flags etc for chassis 1
> *
> -* Copyright 2017-2019 NXP
> +* Copyright 2017-2020 NXP
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -54,14 +54,6 @@ typedef struct {
> UINTN SdhcClk;
> } SOC_CLOCK_INFO;
>
> -/*
> - * Print Soc information
> - */
> -VOID
> -PrintSoc (
> - VOID
> - );
> -
> /*
> * Initialize Clock structure
> */
> @@ -79,22 +71,6 @@ SmmuInit (
> VOID
> );
>
> -/*
> - * Print CPU information
> - */
> -VOID
> -PrintCpuInfo (
> - VOID
> - );
> -
> -/*
> - * Dump RCW (Reset Control Word) on console
> - */
> -VOID
> -PrintRCW (
> - VOID
> - );
> -
> UINT32
> InitiatorType (
> IN UINT32 Cluster,
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 11/28] Silicon/NXP: remove not needed components
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (9 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 10/28] Silicon/NXP: remove print information from Soc lib Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 10:07 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 12/28] Silicon/NXP: Remove unnecessary PCDs Pankaj Bansal
` (18 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
The structures elements and functions that are not necessary for booting
for now are being deleted.
Once the directory structure has been changed (i.e. we have clear
distinction between chassis code and header files and SOC code and header
files), we will put back the code and
structure components back at their appropriate respective place.
Also right now all the elements are being defined in structures, which are
not being used right now. So to simplify the code restructuring, I have
removed those for now. When we need to use those elements, we can define
those one by one.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 4 -
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ----
Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +------------------
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ---
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 6 -
Silicon/NXP/Library/SocLib/Chassis.c | 220 -------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 -----
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 7 +-
Silicon/NXP/Library/SocLib/NxpChassis.h | 90 ------
Silicon/NXP/Library/SocLib/SerDes.c | 268 ----------------
Silicon/NXP/NxpQoriqLs.dec | 27 --
11 files changed, 3 insertions(+), 1125 deletions(-)
delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
delete mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 802cccdce63b..385b6e067e26 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -39,10 +39,6 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
- #
- # Board Specific Pcds
- #
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
#
diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
deleted file mode 100644
index 9afbc522398a..000000000000
--- a/Silicon/NXP/Include/Chassis2/LsSerDes.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/** LsSerDes.h
- The Header file of SerDes Module for Chassis 2
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef LS_SERDES_H_
-#define LS_SERDES_H_
-
-#include <Uefi/UefiBaseType.h>
-
-#define SRDS_MAX_LANES 4
-
-typedef enum {
- None = 0,
- Pcie1,
- Pcie2,
- Pcie3,
- Sata,
- SgmiiFm1Dtsec1,
- SgmiiFm1Dtsec2,
- SgmiiFm1Dtsec5,
- SgmiiFm1Dtsec6,
- SgmiiFm1Dtsec9,
- SgmiiFm1Dtsec10,
- QsgmiiFm1A,
- XfiFm1Mac9,
- XfiFm1Mac10,
- Sgmii2500Fm1Dtsec2,
- Sgmii2500Fm1Dtsec5,
- Sgmii2500Fm1Dtsec9,
- Sgmii2500Fm1Dtsec10,
- SerdesPrtclCount
-} SERDES_PROTOCOL;
-
-typedef enum {
- Srds1 = 0,
- Srds2,
- SrdsMaxNum
-} SERDES_NUMBER;
-
-typedef struct {
- UINT16 Protocol;
- UINT8 SrdsLane[SRDS_MAX_LANES];
-} SERDES_CONFIG;
-
-typedef VOID
-(*SERDES_PROBE_LANES_CALLBACK) (
- IN SERDES_PROTOCOL LaneProtocol,
- IN VOID *Arg
- );
-
-VOID
-SerDesProbeLanes(
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- );
-
-#endif /* LS_SERDES_H_ */
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index f05a813750e8..74330b6205e7 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -1,7 +1,7 @@
/** Soc.h
* Header defining the Base addresses, sizes, flags etc for chassis 1
*
-* Copyright 2017-2019 NXP
+* Copyright 2017-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -10,22 +10,7 @@
#ifndef NXP_SOC_H_
#define NXP_SOC_H_
-#define HWA_CGA_M1_CLK_SEL 0xe0000000
-#define HWA_CGA_M1_CLK_SHIFT 29
-
-#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
-#define NUM_CC_PLLS 2
#define CLK_FREQ 100000000
-#define MAX_CPUS 4
-#define NUM_FMAN 1
-#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
-
-/* RCW SERDES MACRO */
-#define RCWSR_INDEX 4
-#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
-#define RCWSR_SRDS1_PRTCL_SHIFT 16
-#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
-#define RCWSR_SRDS2_PRTCL_SHIFT 0
/* SMMU Defintions */
#define SMMU_BASE_ADDR 0x09000000
@@ -41,312 +26,17 @@
#define IDR1_PAGESIZE_MASK 0x80000000
typedef struct {
- UINTN FreqProcessor[MAX_CPUS];
UINTN FreqSystemBus;
- UINTN FreqDdrBus;
- UINTN FreqLocalBus;
- UINTN FreqSdhc;
- UINTN FreqFman[NUM_FMAN];
- UINTN FreqQman;
} SYS_INFO;
/* Device Configuration and Pin Control */
typedef struct {
- UINT32 PorSr1; /* POR status 1 */
-#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
- UINT32 PorSr2; /* POR status 2 */
- UINT8 Res008[0x20-0x8];
- UINT32 GppOrCr1; /* General-purpose POR configuration */
- UINT32 GppOrCr2;
- UINT32 DcfgFuseSr; /* Fuse status register */
- UINT8 Res02c[0x70-0x2c];
- UINT32 DevDisr; /* Device disable control */
- UINT32 DevDisr2; /* Device disable control 2 */
- UINT32 DevDisr3; /* Device disable control 3 */
- UINT32 DevDisr4; /* Device disable control 4 */
- UINT32 DevDisr5; /* Device disable control 5 */
- UINT32 DevDisr6; /* Device disable control 6 */
- UINT32 DevDisr7; /* Device disable control 7 */
- UINT8 Res08c[0x94-0x8c];
- UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
- UINT32 CoreDisrL; /* lower portion for support of 64 cores */
- UINT8 Res09c[0xa0-0x9c];
- UINT32 Pvr; /* Processor version */
- UINT32 Svr; /* System version */
- UINT32 Mvr; /* Manufacturing version */
- UINT8 Res0ac[0xb0-0xac];
- UINT32 RstCr; /* Reset control */
- UINT32 RstRqPblSr; /* Reset request preboot loader status */
- UINT8 Res0b8[0xc0-0xb8];
- UINT32 RstRqMr1; /* Reset request mask */
- UINT8 Res0c4[0xc8-0xc4];
- UINT32 RstRqSr1; /* Reset request status */
- UINT8 Res0cc[0xd4-0xcc];
- UINT32 RstRqWdTmrL; /* Reset request WDT mask */
- UINT8 Res0d8[0xdc-0xd8];
- UINT32 RstRqWdtSrL; /* Reset request WDT status */
- UINT8 Res0e0[0xe4-0xe0];
- UINT32 BrrL; /* Boot release */
- UINT8 Res0e8[0x100-0xe8];
+ UINT8 Res0[0x100-0x00];
UINT32 RcwSr[16]; /* Reset control word status */
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
-#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
-#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
- UINT8 Res140[0x200-0x140];
- UINT32 ScratchRw[4]; /* Scratch Read/Write */
- UINT8 Res210[0x300-0x210];
- UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
- UINT8 Res310[0x400-0x310];
- UINT32 CrstSr[12];
- UINT8 Res430[0x500-0x430];
- /* PCI Express n Logical I/O Device Number register */
- UINT32 DcfgCcsrPex1LiodNr;
- UINT32 DcfgCcsrPex2LiodNr;
- UINT32 DcfgCcsrPex3LiodNr;
- UINT32 DcfgCcsrPex4LiodNr;
- /* RIO n Logical I/O Device Number register */
- UINT32 DcfgCcsrRio1LiodNr;
- UINT32 DcfgCcsrRio2LiodNr;
- UINT32 DcfgCcsrRio3LiodNr;
- UINT32 DcfgCcsrRio4LiodNr;
- /* USB Logical I/O Device Number register */
- UINT32 DcfgCcsrUsb1LiodNr;
- UINT32 DcfgCcsrUsb2LiodNr;
- UINT32 DcfgCcsrUsb3LiodNr;
- UINT32 DcfgCcsrUsb4LiodNr;
- /* SD/MMC Logical I/O Device Number register */
- UINT32 DcfgCcsrSdMmc1LiodNr;
- UINT32 DcfgCcsrSdMmc2LiodNr;
- UINT32 DcfgCcsrSdMmc3LiodNr;
- UINT32 DcfgCcsrSdMmc4LiodNr;
- /* RIO Message Unit Logical I/O Device Number register */
- UINT32 DcfgCcsrRiomaintLiodNr;
- UINT8 Res544[0x550-0x544];
- UINT32 SataLiodNr[4];
- UINT8 Res560[0x570-0x560];
- UINT32 DcfgCcsrMisc1LiodNr;
- UINT32 DcfgCcsrMisc2LiodNr;
- UINT32 DcfgCcsrMisc3LiodNr;
- UINT32 DcfgCcsrMisc4LiodNr;
- UINT32 DcfgCcsrDma1LiodNr;
- UINT32 DcfgCcsrDma2LiodNr;
- UINT32 DcfgCcsrDma3LiodNr;
- UINT32 DcfgCcsrDma4LiodNr;
- UINT32 DcfgCcsrSpare1LiodNr;
- UINT32 DcfgCcsrSpare2LiodNr;
- UINT32 DcfgCcsrSpare3LiodNr;
- UINT32 DcfgCcsrSpare4LiodNr;
- UINT8 Res5a0[0x600-0x5a0];
- UINT32 DcfgCcsrPblSr;
- UINT32 PamuBypENr;
- UINT32 DmaCr1;
- UINT8 Res60c[0x610-0x60c];
- UINT32 DcfgCcsrGenSr1;
- UINT32 DcfgCcsrGenSr2;
- UINT32 DcfgCcsrGenSr3;
- UINT32 DcfgCcsrGenSr4;
- UINT32 DcfgCcsrGenCr1;
- UINT32 DcfgCcsrGenCr2;
- UINT32 DcfgCcsrGenCr3;
- UINT32 DcfgCcsrGenCr4;
- UINT32 DcfgCcsrGenCr5;
- UINT32 DcfgCcsrGenCr6;
- UINT32 DcfgCcsrGenCr7;
- UINT8 Res63c[0x658-0x63c];
- UINT32 DcfgCcsrcGenSr1;
- UINT32 DcfgCcsrcGenSr0;
- UINT8 Res660[0x678-0x660];
- UINT32 DcfgCcsrcGenCr1;
- UINT32 DcfgCcsrcGenCr0;
- UINT8 Res680[0x700-0x680];
- UINT32 DcfgCcsrSrIoPstecr;
- UINT32 DcfgCcsrDcsrCr;
- UINT8 Res708[0x740-0x708]; /* add more registers when needed */
- UINT32 TpItyp[64]; /* Topology Initiator Type Register */
- struct {
- UINT32 Upper;
- UINT32 Lower;
- } TpCluster[16];
- UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
- UINT32 DcfgCcsrQmBmWarmRst;
- UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
- UINT32 DcfgCcsrReserved0;
- UINT32 DcfgCcsrReserved1;
} CCSR_GUR;
-/* Supplemental Configuration Unit */
-typedef struct {
- UINT8 Res000[0x070-0x000];
- UINT32 Usb1Prm1Cr;
- UINT32 Usb1Prm2Cr;
- UINT32 Usb1Prm3Cr;
- UINT32 Usb2Prm1Cr;
- UINT32 Usb2Prm2Cr;
- UINT32 Usb2Prm3Cr;
- UINT32 Usb3Prm1Cr;
- UINT32 Usb3Prm2Cr;
- UINT32 Usb3Prm3Cr;
- UINT8 Res094[0x100-0x094];
- UINT32 Usb2Icid;
- UINT32 Usb3Icid;
- UINT8 Res108[0x114-0x108];
- UINT32 DmaIcid;
- UINT32 SataIcid;
- UINT32 Usb1Icid;
- UINT32 QeIcid;
- UINT32 SdhcIcid;
- UINT32 EdmaIcid;
- UINT32 EtrIcid;
- UINT32 Core0SftRst;
- UINT32 Core1SftRst;
- UINT32 Core2SftRst;
- UINT32 Core3SftRst;
- UINT8 Res140[0x158-0x140];
- UINT32 AltCBar;
- UINT32 QspiCfg;
- UINT8 Res160[0x180-0x160];
- UINT32 DmaMcr;
- UINT8 Res184[0x188-0x184];
- UINT32 GicAlign;
- UINT32 DebugIcid;
- UINT8 Res190[0x1a4-0x190];
- UINT32 SnpCnfGcr;
-#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
-#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
-#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
-#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
-#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
-#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
-#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
-#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
-#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
-#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
- UINT8 Res1a8[0x1ac-0x1a8];
- UINT32 IntpCr;
- UINT8 Res1b0[0x204-0x1b0];
- UINT32 CoreSrEnCr;
- UINT8 Res208[0x220-0x208];
- UINT32 RvBar00;
- UINT32 RvBar01;
- UINT32 RvBar10;
- UINT32 RvBar11;
- UINT32 RvBar20;
- UINT32 RvBar21;
- UINT32 RvBar30;
- UINT32 RvBar31;
- UINT32 LpmCsr;
- UINT8 Res244[0x400-0x244];
- UINT32 QspIdQScr;
- UINT32 EcgTxcMcr;
- UINT32 SdhcIoVSelCr;
- UINT32 RcwPMuxCr0;
- /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
- *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
- *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
- Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
-#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
- /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
- *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
- *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
- Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
-#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
- UINT32 UsbDrvVBusSelCr;
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
- UINT32 UsbPwrFaultSelCr;
-#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
-#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
-#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
-#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
-#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
-#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
- UINT32 UsbRefclkSelcr1;
- UINT32 UsbRefclkSelcr2;
- UINT32 UsbRefclkSelcr3;
- UINT8 Res424[0x600-0x424];
- UINT32 ScratchRw[4];
- UINT8 Res610[0x680-0x610];
- UINT32 CoreBCr;
- UINT8 Res684[0x1000-0x684];
- UINT32 Pex1MsiIr;
- UINT32 Pex1MsiR;
- UINT8 Res1008[0x2000-0x1008];
- UINT32 Pex2;
- UINT32 Pex2MsiR;
- UINT8 Res2008[0x3000-0x2008];
- UINT32 Pex3MsiIr;
- UINT32 Pex3MsiR;
-} CCSR_SCFG;
-
-#define USB_TXVREFTUNE 0x9
-#define USB_SQRXTUNE 0xFC7FFFFF
-#define USB_PCSTXSWINGFULL 0x47
-#define USB_PHY_RX_EQ_VAL_1 0x0000
-#define USB_PHY_RX_EQ_VAL_2 0x8000
-#define USB_PHY_RX_EQ_VAL_3 0x8003
-#define USB_PHY_RX_EQ_VAL_4 0x800b
-
-/*USB_PHY_SS memory map*/
-typedef struct {
- UINT16 IpIdcodeLo;
- UINT16 SupIdcodeHi;
- UINT8 Res4[0x0006-0x0004];
- UINT16 RtuneDebug;
- UINT16 RtuneStat;
- UINT16 SupSsPhase;
- UINT16 SsFreq;
- UINT8 ResE[0x0020-0x000e];
- UINT16 Ateovrd;
- UINT16 MpllOvrdInLo;
- UINT8 Res24[0x0026-0x0024];
- UINT16 SscOvrdIn;
- UINT8 Res28[0x002A-0x0028];
- UINT16 LevelOvrdIn;
- UINT8 Res2C[0x0044-0x002C];
- UINT16 ScopeCount;
- UINT8 Res46[0x0060-0x0046];
- UINT16 MpllLoopCtl;
- UINT8 Res62[0x006C-0x0062];
- UINT16 SscClkCntrl;
- UINT8 Res6E[0x2002-0x006E];
- UINT16 Lane0TxOvrdInHi;
- UINT16 Lane0TxOvrdDrvLo;
- UINT8 Res2006[0x200C-0x2006];
- UINT16 Lane0RxOvrdInHi;
- UINT8 Res200E[0x2022-0x200E];
- UINT16 Lane0TxCmWaitTimeOvrd;
- UINT8 Res2024[0x202A-0x2024];
- UINT16 Lane0TxLbertCtl;
- UINT16 Lane0RxLbertCtl;
- UINT16 Lane0RxLbertErr;
- UINT8 Res2030[0x205A-0x2030];
- UINT16 Lane0TxAltBlock;
-} CCSR_USB_PHY;
-
-/* Clocking */
-typedef struct {
- struct {
- UINT32 ClkCnCSr; /* core cluster n clock control status */
- UINT8 Res004[0x0c];
- UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
- UINT8 Res014[0x0c];
- } ClkcSr[4];
- UINT8 Res040[0x780]; /* 0x100 */
- struct {
- UINT32 PllCnGSr;
- UINT8 Res804[0x1c];
- } PllCgSr[NUM_CC_PLLS];
- UINT8 Res840[0x1c0];
- UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
- UINT8 Resa04[0x1fc];
- UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
- UINT8 Resc04[0x1c];
- UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
- UINT8 Resc24[0x3dc];
-} CCSR_CLOCK;
-
VOID
GetSysInfo (
OUT SYS_INFO *
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
deleted file mode 100644
index 2d1c6f10f932..000000000000
--- a/Silicon/NXP/LS1043A/Include/SocSerDes.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file
- The Header file of SerDes Module for LS1043A
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef SOC_SERDES_H_
-#define SOC_SERDES_H_
-
-#ifdef CHASSIS2
-#include <Chassis2/LsSerDes.h>
-#endif
-
-SERDES_CONFIG SerDes1ConfigTbl[] = {
- /* SerDes 1 */
- {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
- {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
- {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
- {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
- {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
- {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
- {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
- {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
- {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
- {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
- {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
- {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
- {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
- {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
- {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
- {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
- {}
-};
-
-SERDES_CONFIG *SerDesConfigTbl[] = {
- SerDes1ConfigTbl
-};
-
-#endif /* SOC_SERDES_H_ */
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index f6f15a482a85..f57a0d95b8e1 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -34,12 +34,10 @@ [PcdsFixedAtBuild.common]
#
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
@@ -50,10 +48,7 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
- gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
@@ -64,6 +59,5 @@ [PcdsFixedAtBuild.common]
# Big Endian IPs
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
##
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 2f192e890bcf..847331a63152 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -25,16 +25,6 @@
#include <DramInfo.h>
#include "NxpChassis.h"
-/*
- * Structure to list available SOCs.
- * Name, Soc Version, Number of Cores
- */
-STATIC CPU_TYPE mCpuTypeList[] = {
- CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
- CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
- CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
-};
-
UINT32
EFIAPI
GurRead (
@@ -48,174 +38,6 @@ GurRead (
}
}
-/*
- * Return the type of initiator (core or hardware accelerator)
- */
-UINT32
-InitiatorType (
- IN UINT32 Cluster,
- IN UINTN InitId
- )
-{
- CCSR_GUR *GurBase;
- UINT32 Idx;
- UINT32 Type;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
- Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
-
- if (Type & TP_ITYP_AV_MASK) {
- return Type;
- }
-
- return 0;
-}
-
-/*
- * Return the mask for number of cores on this SOC.
- */
-UINT32
-CpuMask (
- VOID
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINT32 Mask;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
- Mask = 0;
-
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
- Mask |= 1 << Count;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return Mask;
-}
-
-/*
- * Return the number of cores on this SOC.
- */
-UINTN
-CpuNumCores (
- VOID
- )
-{
- UINTN Count;
- UINTN Num;
-
- Count = 0;
- Num = CpuMask ();
-
- while (Num) {
- Count += Num & 1;
- Num >>= 1;
- }
-
- return Count;
-}
-
-/*
- * Return core's cluster
- */
-INT32
-QoriqCoreToCluster (
- IN UINTN Core
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (Count == Core) {
- return ClusterIndex;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return -1; // cannot identify the cluster
-}
-
-/*
- * Return the type of core i.e. A53, A57 etc of inputted
- * core number.
- */
-UINTN
-QoriqCoreToType (
- IN UINTN Core
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
-
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (Count == Core) {
- return Type;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return EFI_NOT_FOUND; /* cannot identify the cluster */
-}
-
-STATIC
-UINTN
-CpuMaskNext (
- IN UINTN Cpu,
- IN UINTN Mask
- )
-{
- for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
-
- return Cpu;
-}
-
/*
* Return system bus frequency
*/
@@ -231,21 +53,6 @@ GetBusFrequency (
return SocSysInfo.FreqSystemBus;
}
-/*
- * Return SDXC bus frequency
- */
-UINT64
-GetSdxcFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSdhc;
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
@@ -268,33 +75,6 @@ SmmuInit (
MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
}
-/*
- * Return current Soc Name form mCpuTypeList
- */
-CHAR8 *
-GetSocName (
- VOID
- )
-{
- UINT8 Count;
- UINTN Svr;
- UINTN Ver;
- CCSR_GUR *GurBase;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- Svr = GurRead ((UINTN)&GurBase->Svr);
- Ver = SVR_SOC_VER (Svr);
-
- for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
- if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
- return (CHAR8 *)mCpuTypeList[Count].Name;
- }
- }
-
- return NULL;
-}
-
UINTN
GetDramSize (
IN VOID
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 687a1d940066..d992e53546f4 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -32,38 +32,14 @@ GetSysInfo (
)
{
CCSR_GUR *GurBase;
- CCSR_CLOCK *ClkBase;
- UINTN CpuIndex;
- UINT32 TempRcw;
- UINT32 CPllSel;
- UINT32 CplxPll;
- CONST UINT8 CoreCplxPll[8] = {
- [0] = 0, /* CC1 PPL / 1 */
- [1] = 0, /* CC1 PPL / 2 */
- [4] = 1, /* CC2 PPL / 1 */
- [5] = 1, /* CC2 PPL / 2 */
- };
-
- CONST UINT8 CoreCplxPllDivisor[8] = {
- [0] = 1, /* CC1 PPL / 1 */
- [1] = 2, /* CC1 PPL / 2 */
- [4] = 1, /* CC2 PPL / 1 */
- [5] = 2, /* CC2 PPL / 2 */
- };
-
- UINTN PllCount;
- UINTN FreqCPll[NUM_CC_PLLS];
- UINTN PllRatio[NUM_CC_PLLS];
UINTN SysClk;
GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
SysClk = CLK_FREQ;
SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
PtrSysInfo->FreqSystemBus = SysClk;
- PtrSysInfo->FreqDdrBus = SysClk;
//
// selects the platform clock:SYSCLK ratio and calculate
@@ -72,61 +48,6 @@ GetSysInfo (
PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
- //
- // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
- //
- PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
-
- for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
- PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
- if (PllRatio[PllCount] > 4) {
- FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
- } else {
- FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
- }
- }
-
- //
- // Calculate Core frequency
- //
- for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
- CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
- CplxPll = CoreCplxPll[CPllSel];
-
- PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
- }
-
- //
- // Calculate FMAN frequency
- //
- TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
- switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
- case 2:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
- break;
- case 3:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
- break;
- case 4:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
- break;
- case 5:
- PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
- break;
- case 6:
- PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
- break;
- case 7:
- PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
- break;
- default:
- DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
- break;
- }
- PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
- PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
}
/**
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index cb670a12797e..f75a8d19f5a5 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -1,6 +1,6 @@
# @file
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -18,7 +18,6 @@ [Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
- Silicon/NXP/LS1043A/LS1043A.dec
[LibraryClasses]
ArmSmcLib
@@ -30,16 +29,12 @@ [LibraryClasses]
[Sources.common]
Chassis.c
Chassis2/Soc.c
- SerDes.c
[BuildOptions]
GCC:*_*_*_CC_FLAGS = -DCHASSIS2
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
index a11acf71563e..836df103f80f 100644
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
@@ -10,58 +10,6 @@
#ifndef NXP_CHASSIS_H_
#define NXP_CHASSIS_H_
-#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
-#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
-#define TP_ITYP_TYPE_ARM 0x0
-#define TP_ITYP_TYPE_PPC 0x1
-#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
-#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
-#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
-#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
-#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
-#define TP_INIT_PER_CLUSTER 4
-
-#define TY_ITYP_VERSION_A7 0x1
-#define TY_ITYP_VERSION_A53 0x2
-#define TY_ITYP_VERSION_A57 0x3
-#define TY_ITYP_VERSION_A72 0x4
-
-#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
-
-#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1043A 0x879200
-#define SVR_LS1046A 0x870700
-#define SVR_LS2088A 0x870901
-
-#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
-#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
-#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
-#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
-
-#define MHZ 1000000
-
-typedef struct {
- CHAR8 *Name;
- UINT32 SocVer;
- UINT32 NumCores;
-} CPU_TYPE;
-
-typedef struct {
- UINTN CpuClk; /* CPU clock in Hz! */
- UINTN BusClk;
- UINTN MemClk;
- UINTN PciClk;
- UINTN SdhcClk;
-} SOC_CLOCK_INFO;
-
-/*
- * Initialize Clock structure
- */
-VOID
-ClockInit (
- VOID
- );
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
@@ -71,42 +19,4 @@ SmmuInit (
VOID
);
-UINT32
-InitiatorType (
- IN UINT32 Cluster,
- IN UINTN InitId
- );
-
-/*
- * Return the mask for number of cores on this SOC.
- */
-UINT32
-CpuMask (
- VOID
- );
-
-/*
- * Return the number of cores on this SOC.
- */
-UINTN
-CpuNumCores (
- VOID
- );
-
-/*
- * Return the type of initiator for core/hardware accelerator for given core index.
- */
-UINTN
-QoriqCoreToType (
- IN UINTN Core
- );
-
-/*
- * Return the cluster of initiator for core/hardware accelerator for given core index.
- */
-INT32
-QoriqCoreToCluster (
- IN UINTN Core
- );
-
#endif /* NXP_CHASSIS_H_ */
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
deleted file mode 100644
index b9909d922138..000000000000
--- a/Silicon/NXP/Library/SocLib/SerDes.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/** SerDes.c
- Provides the basic interfaces for SerDes Module
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifdef CHASSIS2
-#include <Chassis2/LsSerDes.h>
-#include <Chassis2/NxpSoc.h>
-#elif CHASSIS3
-#include <Chassis3/LsSerDes.h>
-#include <Chassis3/NxpSoc.h>
-#endif
-#include <Library/DebugLib.h>
-#include <SocSerDes.h>
-#include <Uefi.h>
-
-/**
- Function to get serdes Lane protocol corresponding to
- serdes protocol.
-
- @param SerDes Serdes number.
- @param Cfg Serdes Protocol.
- @param Lane Serdes Lane number.
-
- @return Serdes Lane protocol.
-
-**/
-STATIC
-SERDES_PROTOCOL
-GetSerDesPrtcl (
- IN INTN SerDes,
- IN INTN Cfg,
- IN INTN Lane
- )
-{
- SERDES_CONFIG *Config;
-
- if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
- return 0;
- }
-
- Config = SerDesConfigTbl[SerDes];
- while (Config->Protocol) {
- if (Config->Protocol == Cfg) {
- return Config->SrdsLane[Lane];
- }
- Config++;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Function to check if inputted protocol is a valid serdes protocol.
-
- @param SerDes Serdes number.
- @param Prtcl Serdes Protocol to be verified.
-
- @return EFI_INVALID_PARAMETER Input parameter in invalid.
- @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
- @return EFI_SUCCESS Serdes Protocol is a valid protocol.
-
-**/
-STATIC
-EFI_STATUS
-CheckSerDesPrtclValid (
- IN INTN SerDes,
- IN UINT32 Prtcl
- )
-{
- SERDES_CONFIG *Config;
- INTN Cnt;
-
- if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
- return EFI_INVALID_PARAMETER;
- }
-
- Config = SerDesConfigTbl[SerDes];
- while (Config->Protocol) {
- if (Config->Protocol == Prtcl) {
- DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
- break;
- }
- Config++;
- }
-
- if (!Config->Protocol) {
- return EFI_NOT_FOUND;
- }
-
- for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
- if (Config->SrdsLane[Cnt] != None) {
- return EFI_SUCCESS;
- }
- }
-
- return EFI_NOT_FOUND;
-}
-
-/**
- Function to fill serdes map information.
-
- @param Srds Serdes number.
- @param SerdesProtocolMask Serdes Protocol Mask.
- @param SerdesProtocolShift Serdes Protocol shift value.
- @param SerDesPrtclMap Pointer to Serdes Protocol map.
-
-**/
-STATIC
-VOID
-LSSerDesMap (
- IN UINT32 Srds,
- IN UINT32 SerdesProtocolMask,
- IN UINT32 SerdesProtocolShift,
- OUT UINT64 *SerDesPrtclMap
- )
-{
- CCSR_GUR *Gur;
- UINT32 SrdsProt;
- INTN Lane;
- UINT32 Flag;
-
- Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- *SerDesPrtclMap = 0x0;
- Flag = 0;
-
- SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
- SrdsProt >>= SerdesProtocolShift;
-
- DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
- Srds + 1, SrdsProt, SrdsProt));
-
- if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
- DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
- Srds + 1, SrdsProt));
- Flag++;
- }
-
- for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
- SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
- if (LanePrtcl >= SerdesPrtclCount) {
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
- Flag++;
- } else {
- *SerDesPrtclMap |= (1u << LanePrtcl);
- }
- }
-
- if (Flag) {
- DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
- } else {
- DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
- }
-}
-
-/**
- Get lane protocol on provided serdes lane and execute callback function.
-
- @param Srds Serdes number.
- @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
- @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
- @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
- @param Arg Pointer to Arguments to be passed to callback function.
-
-**/
-STATIC
-VOID
-SerDesInstanceProbeLanes (
- IN UINT32 Srds,
- IN UINT32 SerdesProtocolMask,
- IN UINT32 SerdesProtocolShift,
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- )
-{
-
- CCSR_GUR *Gur;
- UINT32 SrdsProt;
- INTN Lane;
-
- Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
-
- SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
- SrdsProt >>= SerdesProtocolShift;
-
- /*
- * Invoke callback for all lanes in the SerDes instance:
- */
- for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
- SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
- if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
- } else if (LanePrtcl != None) {
- SerDesLaneProbeCallback (LanePrtcl, Arg);
- }
- }
-}
-
-/**
- Probe all serdes lanes for lane protocol and execute provided callback function.
-
- @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
- @param Arg Pointer to Arguments to be passed to callback function.
-
-**/
-VOID
-SerDesProbeLanes (
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- )
-{
- SerDesInstanceProbeLanes (Srds1,
- RCWSR_SRDS1_PRTCL_MASK,
- RCWSR_SRDS1_PRTCL_SHIFT,
- SerDesLaneProbeCallback,
- Arg);
-
- if (PcdGetBool (PcdSerdes2Enabled)) {
- SerDesInstanceProbeLanes (Srds2,
- RCWSR_SRDS2_PRTCL_MASK,
- RCWSR_SRDS2_PRTCL_SHIFT,
- SerDesLaneProbeCallback,
- Arg);
- }
-}
-
-/**
- Function to return Serdes protocol map for all serdes available on board.
-
- @param SerDesPrtclMap Pointer to Serdes protocl map.
-
-**/
-VOID
-GetSerdesProtocolMaps (
- OUT UINT64 *SerDesPrtclMap
- )
-{
- LSSerDesMap (Srds1,
- RCWSR_SRDS1_PRTCL_MASK,
- RCWSR_SRDS1_PRTCL_SHIFT,
- SerDesPrtclMap);
-
- if (PcdGetBool (PcdSerdes2Enabled)) {
- LSSerDesMap (Srds2,
- RCWSR_SRDS2_PRTCL_MASK,
- RCWSR_SRDS2_PRTCL_SHIFT,
- SerDesPrtclMap);
- }
-
-}
-
-BOOLEAN
-IsSerDesLaneProtocolConfigured (
- IN UINT64 SerDesPrtclMap,
- IN SERDES_PROTOCOL Device
- )
-{
- if ((Device >= SerdesPrtclCount) || (Device < None)) {
- ASSERT ((Device > None) && (Device < SerdesPrtclCount));
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
- }
-
- return (SerDesPrtclMap & (1u << Device)) != 0 ;
-}
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 4a1cfb3e278e..943dbac81013 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -32,10 +32,7 @@ [PcdsFixedAtBuild.common]
# Pcds for base address and size
#
gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
- gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
- gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104
gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
@@ -61,10 +58,6 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
- gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E
- gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F
- gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
- gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
@@ -75,36 +68,16 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
- gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
- gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
- gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
-
- #
- # NV Pcd
- #
- gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
- gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
#
# Platform PCDs
#
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
-
- #
- # Clock PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
- gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
#
# Pcds to support Big Endian IPs
#
- gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
- gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
- gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 11/28] Silicon/NXP: remove not needed components
2020-03-20 14:35 ` [PATCH v2 11/28] Silicon/NXP: remove not needed components Pankaj Bansal
@ 2020-04-01 10:07 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 10:07 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:26 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> The structures elements and functions that are not necessary for booting
> for now are being deleted.
> Once the directory structure has been changed (i.e. we have clear
> distinction between chassis code and header files and SOC code and header
> files), we will put back the code and
> structure components back at their appropriate respective place.
>
> Also right now all the elements are being defined in structures, which are
> not being used right now. So to simplify the code restructuring, I have
> removed those for now. When we need to use those elements, we can define
> those one by one.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 4 -
> Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ----
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +------------------
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ---
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 6 -
> Silicon/NXP/Library/SocLib/Chassis.c | 220 -------------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 -----
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 7 +-
> Silicon/NXP/Library/SocLib/NxpChassis.h | 90 ------
> Silicon/NXP/Library/SocLib/SerDes.c | 268 ----------------
> Silicon/NXP/NxpQoriqLs.dec | 27 --
> 11 files changed, 3 insertions(+), 1125 deletions(-)
> delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
> delete mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 802cccdce63b..385b6e067e26 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -39,10 +39,6 @@ [PcdsFixedAtBuild.common]
> gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
> gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
>
> - #
> - # Board Specific Pcds
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
>
> #
> diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
> deleted file mode 100644
> index 9afbc522398a..000000000000
> --- a/Silicon/NXP/Include/Chassis2/LsSerDes.h
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -/** LsSerDes.h
> - The Header file of SerDes Module for Chassis 2
> -
> - Copyright 2017-2019 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef LS_SERDES_H_
> -#define LS_SERDES_H_
> -
> -#include <Uefi/UefiBaseType.h>
> -
> -#define SRDS_MAX_LANES 4
> -
> -typedef enum {
> - None = 0,
> - Pcie1,
> - Pcie2,
> - Pcie3,
> - Sata,
> - SgmiiFm1Dtsec1,
> - SgmiiFm1Dtsec2,
> - SgmiiFm1Dtsec5,
> - SgmiiFm1Dtsec6,
> - SgmiiFm1Dtsec9,
> - SgmiiFm1Dtsec10,
> - QsgmiiFm1A,
> - XfiFm1Mac9,
> - XfiFm1Mac10,
> - Sgmii2500Fm1Dtsec2,
> - Sgmii2500Fm1Dtsec5,
> - Sgmii2500Fm1Dtsec9,
> - Sgmii2500Fm1Dtsec10,
> - SerdesPrtclCount
> -} SERDES_PROTOCOL;
> -
> -typedef enum {
> - Srds1 = 0,
> - Srds2,
> - SrdsMaxNum
> -} SERDES_NUMBER;
> -
> -typedef struct {
> - UINT16 Protocol;
> - UINT8 SrdsLane[SRDS_MAX_LANES];
> -} SERDES_CONFIG;
> -
> -typedef VOID
> -(*SERDES_PROBE_LANES_CALLBACK) (
> - IN SERDES_PROTOCOL LaneProtocol,
> - IN VOID *Arg
> - );
> -
> -VOID
> -SerDesProbeLanes(
> - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> - IN VOID *Arg
> - );
> -
> -#endif /* LS_SERDES_H_ */
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> index f05a813750e8..74330b6205e7 100644
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> @@ -1,7 +1,7 @@
> /** Soc.h
> * Header defining the Base addresses, sizes, flags etc for chassis 1
> *
> -* Copyright 2017-2019 NXP
> +* Copyright 2017-2020 NXP
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -10,22 +10,7 @@
> #ifndef NXP_SOC_H_
> #define NXP_SOC_H_
>
> -#define HWA_CGA_M1_CLK_SEL 0xe0000000
> -#define HWA_CGA_M1_CLK_SHIFT 29
> -
> -#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
> -#define NUM_CC_PLLS 2
> #define CLK_FREQ 100000000
> -#define MAX_CPUS 4
> -#define NUM_FMAN 1
> -#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
> -
> -/* RCW SERDES MACRO */
> -#define RCWSR_INDEX 4
> -#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
> -#define RCWSR_SRDS1_PRTCL_SHIFT 16
> -#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
> -#define RCWSR_SRDS2_PRTCL_SHIFT 0
>
> /* SMMU Defintions */
> #define SMMU_BASE_ADDR 0x09000000
> @@ -41,312 +26,17 @@
> #define IDR1_PAGESIZE_MASK 0x80000000
>
> typedef struct {
> - UINTN FreqProcessor[MAX_CPUS];
> UINTN FreqSystemBus;
> - UINTN FreqDdrBus;
> - UINTN FreqLocalBus;
> - UINTN FreqSdhc;
> - UINTN FreqFman[NUM_FMAN];
> - UINTN FreqQman;
> } SYS_INFO;
>
> /* Device Configuration and Pin Control */
> typedef struct {
> - UINT32 PorSr1; /* POR status 1 */
> -#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
> - UINT32 PorSr2; /* POR status 2 */
> - UINT8 Res008[0x20-0x8];
> - UINT32 GppOrCr1; /* General-purpose POR configuration */
> - UINT32 GppOrCr2;
> - UINT32 DcfgFuseSr; /* Fuse status register */
> - UINT8 Res02c[0x70-0x2c];
> - UINT32 DevDisr; /* Device disable control */
> - UINT32 DevDisr2; /* Device disable control 2 */
> - UINT32 DevDisr3; /* Device disable control 3 */
> - UINT32 DevDisr4; /* Device disable control 4 */
> - UINT32 DevDisr5; /* Device disable control 5 */
> - UINT32 DevDisr6; /* Device disable control 6 */
> - UINT32 DevDisr7; /* Device disable control 7 */
> - UINT8 Res08c[0x94-0x8c];
> - UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
> - UINT32 CoreDisrL; /* lower portion for support of 64 cores */
> - UINT8 Res09c[0xa0-0x9c];
> - UINT32 Pvr; /* Processor version */
> - UINT32 Svr; /* System version */
> - UINT32 Mvr; /* Manufacturing version */
> - UINT8 Res0ac[0xb0-0xac];
> - UINT32 RstCr; /* Reset control */
> - UINT32 RstRqPblSr; /* Reset request preboot loader status */
> - UINT8 Res0b8[0xc0-0xb8];
> - UINT32 RstRqMr1; /* Reset request mask */
> - UINT8 Res0c4[0xc8-0xc4];
> - UINT32 RstRqSr1; /* Reset request status */
> - UINT8 Res0cc[0xd4-0xcc];
> - UINT32 RstRqWdTmrL; /* Reset request WDT mask */
> - UINT8 Res0d8[0xdc-0xd8];
> - UINT32 RstRqWdtSrL; /* Reset request WDT status */
> - UINT8 Res0e0[0xe4-0xe0];
> - UINT32 BrrL; /* Boot release */
> - UINT8 Res0e8[0x100-0xe8];
> + UINT8 Res0[0x100-0x00];
> UINT32 RcwSr[16]; /* Reset control word status */
> #define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> #define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> -#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
> -#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> - UINT8 Res140[0x200-0x140];
> - UINT32 ScratchRw[4]; /* Scratch Read/Write */
> - UINT8 Res210[0x300-0x210];
> - UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
> - UINT8 Res310[0x400-0x310];
> - UINT32 CrstSr[12];
> - UINT8 Res430[0x500-0x430];
> - /* PCI Express n Logical I/O Device Number register */
> - UINT32 DcfgCcsrPex1LiodNr;
> - UINT32 DcfgCcsrPex2LiodNr;
> - UINT32 DcfgCcsrPex3LiodNr;
> - UINT32 DcfgCcsrPex4LiodNr;
> - /* RIO n Logical I/O Device Number register */
> - UINT32 DcfgCcsrRio1LiodNr;
> - UINT32 DcfgCcsrRio2LiodNr;
> - UINT32 DcfgCcsrRio3LiodNr;
> - UINT32 DcfgCcsrRio4LiodNr;
> - /* USB Logical I/O Device Number register */
> - UINT32 DcfgCcsrUsb1LiodNr;
> - UINT32 DcfgCcsrUsb2LiodNr;
> - UINT32 DcfgCcsrUsb3LiodNr;
> - UINT32 DcfgCcsrUsb4LiodNr;
> - /* SD/MMC Logical I/O Device Number register */
> - UINT32 DcfgCcsrSdMmc1LiodNr;
> - UINT32 DcfgCcsrSdMmc2LiodNr;
> - UINT32 DcfgCcsrSdMmc3LiodNr;
> - UINT32 DcfgCcsrSdMmc4LiodNr;
> - /* RIO Message Unit Logical I/O Device Number register */
> - UINT32 DcfgCcsrRiomaintLiodNr;
> - UINT8 Res544[0x550-0x544];
> - UINT32 SataLiodNr[4];
> - UINT8 Res560[0x570-0x560];
> - UINT32 DcfgCcsrMisc1LiodNr;
> - UINT32 DcfgCcsrMisc2LiodNr;
> - UINT32 DcfgCcsrMisc3LiodNr;
> - UINT32 DcfgCcsrMisc4LiodNr;
> - UINT32 DcfgCcsrDma1LiodNr;
> - UINT32 DcfgCcsrDma2LiodNr;
> - UINT32 DcfgCcsrDma3LiodNr;
> - UINT32 DcfgCcsrDma4LiodNr;
> - UINT32 DcfgCcsrSpare1LiodNr;
> - UINT32 DcfgCcsrSpare2LiodNr;
> - UINT32 DcfgCcsrSpare3LiodNr;
> - UINT32 DcfgCcsrSpare4LiodNr;
> - UINT8 Res5a0[0x600-0x5a0];
> - UINT32 DcfgCcsrPblSr;
> - UINT32 PamuBypENr;
> - UINT32 DmaCr1;
> - UINT8 Res60c[0x610-0x60c];
> - UINT32 DcfgCcsrGenSr1;
> - UINT32 DcfgCcsrGenSr2;
> - UINT32 DcfgCcsrGenSr3;
> - UINT32 DcfgCcsrGenSr4;
> - UINT32 DcfgCcsrGenCr1;
> - UINT32 DcfgCcsrGenCr2;
> - UINT32 DcfgCcsrGenCr3;
> - UINT32 DcfgCcsrGenCr4;
> - UINT32 DcfgCcsrGenCr5;
> - UINT32 DcfgCcsrGenCr6;
> - UINT32 DcfgCcsrGenCr7;
> - UINT8 Res63c[0x658-0x63c];
> - UINT32 DcfgCcsrcGenSr1;
> - UINT32 DcfgCcsrcGenSr0;
> - UINT8 Res660[0x678-0x660];
> - UINT32 DcfgCcsrcGenCr1;
> - UINT32 DcfgCcsrcGenCr0;
> - UINT8 Res680[0x700-0x680];
> - UINT32 DcfgCcsrSrIoPstecr;
> - UINT32 DcfgCcsrDcsrCr;
> - UINT8 Res708[0x740-0x708]; /* add more registers when needed */
> - UINT32 TpItyp[64]; /* Topology Initiator Type Register */
> - struct {
> - UINT32 Upper;
> - UINT32 Lower;
> - } TpCluster[16];
> - UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
> - UINT32 DcfgCcsrQmBmWarmRst;
> - UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
> - UINT32 DcfgCcsrReserved0;
> - UINT32 DcfgCcsrReserved1;
> } CCSR_GUR;
>
> -/* Supplemental Configuration Unit */
> -typedef struct {
> - UINT8 Res000[0x070-0x000];
> - UINT32 Usb1Prm1Cr;
> - UINT32 Usb1Prm2Cr;
> - UINT32 Usb1Prm3Cr;
> - UINT32 Usb2Prm1Cr;
> - UINT32 Usb2Prm2Cr;
> - UINT32 Usb2Prm3Cr;
> - UINT32 Usb3Prm1Cr;
> - UINT32 Usb3Prm2Cr;
> - UINT32 Usb3Prm3Cr;
> - UINT8 Res094[0x100-0x094];
> - UINT32 Usb2Icid;
> - UINT32 Usb3Icid;
> - UINT8 Res108[0x114-0x108];
> - UINT32 DmaIcid;
> - UINT32 SataIcid;
> - UINT32 Usb1Icid;
> - UINT32 QeIcid;
> - UINT32 SdhcIcid;
> - UINT32 EdmaIcid;
> - UINT32 EtrIcid;
> - UINT32 Core0SftRst;
> - UINT32 Core1SftRst;
> - UINT32 Core2SftRst;
> - UINT32 Core3SftRst;
> - UINT8 Res140[0x158-0x140];
> - UINT32 AltCBar;
> - UINT32 QspiCfg;
> - UINT8 Res160[0x180-0x160];
> - UINT32 DmaMcr;
> - UINT8 Res184[0x188-0x184];
> - UINT32 GicAlign;
> - UINT32 DebugIcid;
> - UINT8 Res190[0x1a4-0x190];
> - UINT32 SnpCnfGcr;
> -#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
> -#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
> -#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
> -#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
> -#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
> -#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
> -#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
> -#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
> -#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
> -#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
> - UINT8 Res1a8[0x1ac-0x1a8];
> - UINT32 IntpCr;
> - UINT8 Res1b0[0x204-0x1b0];
> - UINT32 CoreSrEnCr;
> - UINT8 Res208[0x220-0x208];
> - UINT32 RvBar00;
> - UINT32 RvBar01;
> - UINT32 RvBar10;
> - UINT32 RvBar11;
> - UINT32 RvBar20;
> - UINT32 RvBar21;
> - UINT32 RvBar30;
> - UINT32 RvBar31;
> - UINT32 LpmCsr;
> - UINT8 Res244[0x400-0x244];
> - UINT32 QspIdQScr;
> - UINT32 EcgTxcMcr;
> - UINT32 SdhcIoVSelCr;
> - UINT32 RcwPMuxCr0;
> - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> - *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> - Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
> -#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> - *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> - Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
> -#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> - UINT32 UsbDrvVBusSelCr;
> -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> - UINT32 UsbPwrFaultSelCr;
> -#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
> -#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
> -#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
> -#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
> -#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
> -#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
> - UINT32 UsbRefclkSelcr1;
> - UINT32 UsbRefclkSelcr2;
> - UINT32 UsbRefclkSelcr3;
> - UINT8 Res424[0x600-0x424];
> - UINT32 ScratchRw[4];
> - UINT8 Res610[0x680-0x610];
> - UINT32 CoreBCr;
> - UINT8 Res684[0x1000-0x684];
> - UINT32 Pex1MsiIr;
> - UINT32 Pex1MsiR;
> - UINT8 Res1008[0x2000-0x1008];
> - UINT32 Pex2;
> - UINT32 Pex2MsiR;
> - UINT8 Res2008[0x3000-0x2008];
> - UINT32 Pex3MsiIr;
> - UINT32 Pex3MsiR;
> -} CCSR_SCFG;
> -
> -#define USB_TXVREFTUNE 0x9
> -#define USB_SQRXTUNE 0xFC7FFFFF
> -#define USB_PCSTXSWINGFULL 0x47
> -#define USB_PHY_RX_EQ_VAL_1 0x0000
> -#define USB_PHY_RX_EQ_VAL_2 0x8000
> -#define USB_PHY_RX_EQ_VAL_3 0x8003
> -#define USB_PHY_RX_EQ_VAL_4 0x800b
> -
> -/*USB_PHY_SS memory map*/
> -typedef struct {
> - UINT16 IpIdcodeLo;
> - UINT16 SupIdcodeHi;
> - UINT8 Res4[0x0006-0x0004];
> - UINT16 RtuneDebug;
> - UINT16 RtuneStat;
> - UINT16 SupSsPhase;
> - UINT16 SsFreq;
> - UINT8 ResE[0x0020-0x000e];
> - UINT16 Ateovrd;
> - UINT16 MpllOvrdInLo;
> - UINT8 Res24[0x0026-0x0024];
> - UINT16 SscOvrdIn;
> - UINT8 Res28[0x002A-0x0028];
> - UINT16 LevelOvrdIn;
> - UINT8 Res2C[0x0044-0x002C];
> - UINT16 ScopeCount;
> - UINT8 Res46[0x0060-0x0046];
> - UINT16 MpllLoopCtl;
> - UINT8 Res62[0x006C-0x0062];
> - UINT16 SscClkCntrl;
> - UINT8 Res6E[0x2002-0x006E];
> - UINT16 Lane0TxOvrdInHi;
> - UINT16 Lane0TxOvrdDrvLo;
> - UINT8 Res2006[0x200C-0x2006];
> - UINT16 Lane0RxOvrdInHi;
> - UINT8 Res200E[0x2022-0x200E];
> - UINT16 Lane0TxCmWaitTimeOvrd;
> - UINT8 Res2024[0x202A-0x2024];
> - UINT16 Lane0TxLbertCtl;
> - UINT16 Lane0RxLbertCtl;
> - UINT16 Lane0RxLbertErr;
> - UINT8 Res2030[0x205A-0x2030];
> - UINT16 Lane0TxAltBlock;
> -} CCSR_USB_PHY;
> -
> -/* Clocking */
> -typedef struct {
> - struct {
> - UINT32 ClkCnCSr; /* core cluster n clock control status */
> - UINT8 Res004[0x0c];
> - UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
> - UINT8 Res014[0x0c];
> - } ClkcSr[4];
> - UINT8 Res040[0x780]; /* 0x100 */
> - struct {
> - UINT32 PllCnGSr;
> - UINT8 Res804[0x1c];
> - } PllCgSr[NUM_CC_PLLS];
> - UINT8 Res840[0x1c0];
> - UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
> - UINT8 Resa04[0x1fc];
> - UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
> - UINT8 Resc04[0x1c];
> - UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
> - UINT8 Resc24[0x3dc];
> -} CCSR_CLOCK;
> -
> VOID
> GetSysInfo (
> OUT SYS_INFO *
> diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> deleted file mode 100644
> index 2d1c6f10f932..000000000000
> --- a/Silicon/NXP/LS1043A/Include/SocSerDes.h
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -/** @file
> - The Header file of SerDes Module for LS1043A
> -
> - Copyright 2017-2019 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef SOC_SERDES_H_
> -#define SOC_SERDES_H_
> -
> -#ifdef CHASSIS2
> -#include <Chassis2/LsSerDes.h>
> -#endif
> -
> -SERDES_CONFIG SerDes1ConfigTbl[] = {
> - /* SerDes 1 */
> - {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
> - {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
> - {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
> - {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
> - {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> - {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> - {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
> - {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> - {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
> - {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
> - {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
> - {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
> - {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
> - {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
> - {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
> - {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
> - {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
> - {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
> - {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
> - {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
> - {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
> - {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
> - {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
> - {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
> - {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
> - {}
> -};
> -
> -SERDES_CONFIG *SerDesConfigTbl[] = {
> - SerDes1ConfigTbl
> -};
> -
> -#endif /* SOC_SERDES_H_ */
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index f6f15a482a85..f57a0d95b8e1 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -34,12 +34,10 @@ [PcdsFixedAtBuild.common]
> #
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> @@ -50,10 +48,7 @@ [PcdsFixedAtBuild.common]
> gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> - gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
> - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> @@ -64,6 +59,5 @@ [PcdsFixedAtBuild.common]
> # Big Endian IPs
> #
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> - gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
>
> ##
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index 2f192e890bcf..847331a63152 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -25,16 +25,6 @@
> #include <DramInfo.h>
> #include "NxpChassis.h"
>
> -/*
> - * Structure to list available SOCs.
> - * Name, Soc Version, Number of Cores
> - */
> -STATIC CPU_TYPE mCpuTypeList[] = {
> - CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> - CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> - CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
> -};
> -
> UINT32
> EFIAPI
> GurRead (
> @@ -48,174 +38,6 @@ GurRead (
> }
> }
>
> -/*
> - * Return the type of initiator (core or hardware accelerator)
> - */
> -UINT32
> -InitiatorType (
> - IN UINT32 Cluster,
> - IN UINTN InitId
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINT32 Idx;
> - UINT32 Type;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
> - Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
> -
> - if (Type & TP_ITYP_AV_MASK) {
> - return Type;
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * Return the mask for number of cores on this SOC.
> - */
> -UINT32
> -CpuMask (
> - VOID
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN ClusterIndex;
> - UINTN Count;
> - UINT32 Cluster;
> - UINT32 Type;
> - UINT32 Mask;
> - UINTN InitiatorIndex;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - ClusterIndex = 0;
> - Count = 0;
> - Mask = 0;
> -
> - do {
> - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> - Type = InitiatorType (Cluster, InitiatorIndex);
> - if (Type) {
> - if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
> - Mask |= 1 << Count;
> - }
> - Count++;
> - }
> - }
> - ClusterIndex++;
> - } while (CHECK_CLUSTER (Cluster));
> -
> - return Mask;
> -}
> -
> -/*
> - * Return the number of cores on this SOC.
> - */
> -UINTN
> -CpuNumCores (
> - VOID
> - )
> -{
> - UINTN Count;
> - UINTN Num;
> -
> - Count = 0;
> - Num = CpuMask ();
> -
> - while (Num) {
> - Count += Num & 1;
> - Num >>= 1;
> - }
> -
> - return Count;
> -}
> -
> -/*
> - * Return core's cluster
> - */
> -INT32
> -QoriqCoreToCluster (
> - IN UINTN Core
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN ClusterIndex;
> - UINTN Count;
> - UINT32 Cluster;
> - UINT32 Type;
> - UINTN InitiatorIndex;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - ClusterIndex = 0;
> - Count = 0;
> - do {
> - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> - Type = InitiatorType (Cluster, InitiatorIndex);
> - if (Type) {
> - if (Count == Core) {
> - return ClusterIndex;
> - }
> - Count++;
> - }
> - }
> - ClusterIndex++;
> - } while (CHECK_CLUSTER (Cluster));
> -
> - return -1; // cannot identify the cluster
> -}
> -
> -/*
> - * Return the type of core i.e. A53, A57 etc of inputted
> - * core number.
> - */
> -UINTN
> -QoriqCoreToType (
> - IN UINTN Core
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN ClusterIndex;
> - UINTN Count;
> - UINT32 Cluster;
> - UINT32 Type;
> - UINTN InitiatorIndex;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - ClusterIndex = 0;
> - Count = 0;
> -
> - do {
> - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> - Type = InitiatorType (Cluster, InitiatorIndex);
> - if (Type) {
> - if (Count == Core) {
> - return Type;
> - }
> - Count++;
> - }
> - }
> - ClusterIndex++;
> - } while (CHECK_CLUSTER (Cluster));
> -
> - return EFI_NOT_FOUND; /* cannot identify the cluster */
> -}
> -
> -STATIC
> -UINTN
> -CpuMaskNext (
> - IN UINTN Cpu,
> - IN UINTN Mask
> - )
> -{
> - for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
> -
> - return Cpu;
> -}
> -
> /*
> * Return system bus frequency
> */
> @@ -231,21 +53,6 @@ GetBusFrequency (
> return SocSysInfo.FreqSystemBus;
> }
>
> -/*
> - * Return SDXC bus frequency
> - */
> -UINT64
> -GetSdxcFrequency (
> - VOID
> - )
> -{
> - SYS_INFO SocSysInfo;
> -
> - GetSysInfo (&SocSysInfo);
> -
> - return SocSysInfo.FreqSdhc;
> -}
> -
> /*
> * Setup SMMU in bypass mode
> * and also set its pagesize
> @@ -268,33 +75,6 @@ SmmuInit (
> MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> }
>
> -/*
> - * Return current Soc Name form mCpuTypeList
> - */
> -CHAR8 *
> -GetSocName (
> - VOID
> - )
> -{
> - UINT8 Count;
> - UINTN Svr;
> - UINTN Ver;
> - CCSR_GUR *GurBase;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> -
> - Svr = GurRead ((UINTN)&GurBase->Svr);
> - Ver = SVR_SOC_VER (Svr);
> -
> - for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
> - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> - return (CHAR8 *)mCpuTypeList[Count].Name;
> - }
> - }
> -
> - return NULL;
> -}
> -
> UINTN
> GetDramSize (
> IN VOID
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index 687a1d940066..d992e53546f4 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -32,38 +32,14 @@ GetSysInfo (
> )
> {
> CCSR_GUR *GurBase;
> - CCSR_CLOCK *ClkBase;
> - UINTN CpuIndex;
> - UINT32 TempRcw;
> - UINT32 CPllSel;
> - UINT32 CplxPll;
> - CONST UINT8 CoreCplxPll[8] = {
> - [0] = 0, /* CC1 PPL / 1 */
> - [1] = 0, /* CC1 PPL / 2 */
> - [4] = 1, /* CC2 PPL / 1 */
> - [5] = 1, /* CC2 PPL / 2 */
> - };
> -
> - CONST UINT8 CoreCplxPllDivisor[8] = {
> - [0] = 1, /* CC1 PPL / 1 */
> - [1] = 2, /* CC1 PPL / 2 */
> - [4] = 1, /* CC2 PPL / 1 */
> - [5] = 2, /* CC2 PPL / 2 */
> - };
> -
> - UINTN PllCount;
> - UINTN FreqCPll[NUM_CC_PLLS];
> - UINTN PllRatio[NUM_CC_PLLS];
> UINTN SysClk;
>
> GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> SysClk = CLK_FREQ;
>
> SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
>
> PtrSysInfo->FreqSystemBus = SysClk;
> - PtrSysInfo->FreqDdrBus = SysClk;
>
> //
> // selects the platform clock:SYSCLK ratio and calculate
> @@ -72,61 +48,6 @@ GetSysInfo (
> PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> - //
> - // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> - //
> - PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> - CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> - CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> -
> - for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> - PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
> - if (PllRatio[PllCount] > 4) {
> - FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> - } else {
> - FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
> - }
> - }
> -
> - //
> - // Calculate Core frequency
> - //
> - for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
> - CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
> - CplxPll = CoreCplxPll[CPllSel];
> -
> - PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
> - }
> -
> - //
> - // Calculate FMAN frequency
> - //
> - TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
> - switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
> - case 2:
> - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
> - break;
> - case 3:
> - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
> - break;
> - case 4:
> - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
> - break;
> - case 5:
> - PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
> - break;
> - case 6:
> - PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
> - break;
> - case 7:
> - PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
> - break;
> - default:
> - DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
> - break;
> - }
> - PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> - PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> }
>
> /**
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index cb670a12797e..f75a8d19f5a5 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -1,6 +1,6 @@
> # @file
> #
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -18,7 +18,6 @@ [Packages]
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> Silicon/NXP/NxpQoriqLs.dec
> - Silicon/NXP/LS1043A/LS1043A.dec
>
> [LibraryClasses]
> ArmSmcLib
> @@ -30,16 +29,12 @@ [LibraryClasses]
> [Sources.common]
> Chassis.c
> Chassis2/Soc.c
> - SerDes.c
>
> [BuildOptions]
> GCC:*_*_*_CC_FLAGS = -DCHASSIS2
>
> [FixedPcd]
> gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
> index a11acf71563e..836df103f80f 100644
> --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
> @@ -10,58 +10,6 @@
> #ifndef NXP_CHASSIS_H_
> #define NXP_CHASSIS_H_
>
> -#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> -#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> -#define TP_ITYP_TYPE_ARM 0x0
> -#define TP_ITYP_TYPE_PPC 0x1
> -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> -#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> -#define TP_INIT_PER_CLUSTER 4
> -
> -#define TY_ITYP_VERSION_A7 0x1
> -#define TY_ITYP_VERSION_A53 0x2
> -#define TY_ITYP_VERSION_A57 0x3
> -#define TY_ITYP_VERSION_A72 0x4
> -
> -#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
> -
> -#define SVR_WO_E 0xFFFFFE
> -#define SVR_LS1043A 0x879200
> -#define SVR_LS1046A 0x870700
> -#define SVR_LS2088A 0x870901
> -
> -#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> -#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> -
> -#define MHZ 1000000
> -
> -typedef struct {
> - CHAR8 *Name;
> - UINT32 SocVer;
> - UINT32 NumCores;
> -} CPU_TYPE;
> -
> -typedef struct {
> - UINTN CpuClk; /* CPU clock in Hz! */
> - UINTN BusClk;
> - UINTN MemClk;
> - UINTN PciClk;
> - UINTN SdhcClk;
> -} SOC_CLOCK_INFO;
> -
> -/*
> - * Initialize Clock structure
> - */
> -VOID
> -ClockInit (
> - VOID
> - );
> -
> /*
> * Setup SMMU in bypass mode
> * and also set its pagesize
> @@ -71,42 +19,4 @@ SmmuInit (
> VOID
> );
>
> -UINT32
> -InitiatorType (
> - IN UINT32 Cluster,
> - IN UINTN InitId
> - );
> -
> -/*
> - * Return the mask for number of cores on this SOC.
> - */
> -UINT32
> -CpuMask (
> - VOID
> - );
> -
> -/*
> - * Return the number of cores on this SOC.
> - */
> -UINTN
> -CpuNumCores (
> - VOID
> - );
> -
> -/*
> - * Return the type of initiator for core/hardware accelerator for given core index.
> - */
> -UINTN
> -QoriqCoreToType (
> - IN UINTN Core
> - );
> -
> -/*
> - * Return the cluster of initiator for core/hardware accelerator for given core index.
> - */
> -INT32
> -QoriqCoreToCluster (
> - IN UINTN Core
> - );
> -
> #endif /* NXP_CHASSIS_H_ */
> diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
> deleted file mode 100644
> index b9909d922138..000000000000
> --- a/Silicon/NXP/Library/SocLib/SerDes.c
> +++ /dev/null
> @@ -1,268 +0,0 @@
> -/** SerDes.c
> - Provides the basic interfaces for SerDes Module
> -
> - Copyright 2017-2019 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifdef CHASSIS2
> -#include <Chassis2/LsSerDes.h>
> -#include <Chassis2/NxpSoc.h>
> -#elif CHASSIS3
> -#include <Chassis3/LsSerDes.h>
> -#include <Chassis3/NxpSoc.h>
> -#endif
> -#include <Library/DebugLib.h>
> -#include <SocSerDes.h>
> -#include <Uefi.h>
> -
> -/**
> - Function to get serdes Lane protocol corresponding to
> - serdes protocol.
> -
> - @param SerDes Serdes number.
> - @param Cfg Serdes Protocol.
> - @param Lane Serdes Lane number.
> -
> - @return Serdes Lane protocol.
> -
> -**/
> -STATIC
> -SERDES_PROTOCOL
> -GetSerDesPrtcl (
> - IN INTN SerDes,
> - IN INTN Cfg,
> - IN INTN Lane
> - )
> -{
> - SERDES_CONFIG *Config;
> -
> - if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> - return 0;
> - }
> -
> - Config = SerDesConfigTbl[SerDes];
> - while (Config->Protocol) {
> - if (Config->Protocol == Cfg) {
> - return Config->SrdsLane[Lane];
> - }
> - Config++;
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Function to check if inputted protocol is a valid serdes protocol.
> -
> - @param SerDes Serdes number.
> - @param Prtcl Serdes Protocol to be verified.
> -
> - @return EFI_INVALID_PARAMETER Input parameter in invalid.
> - @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
> - @return EFI_SUCCESS Serdes Protocol is a valid protocol.
> -
> -**/
> -STATIC
> -EFI_STATUS
> -CheckSerDesPrtclValid (
> - IN INTN SerDes,
> - IN UINT32 Prtcl
> - )
> -{
> - SERDES_CONFIG *Config;
> - INTN Cnt;
> -
> - if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> - return EFI_INVALID_PARAMETER;
> - }
> -
> - Config = SerDesConfigTbl[SerDes];
> - while (Config->Protocol) {
> - if (Config->Protocol == Prtcl) {
> - DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
> - break;
> - }
> - Config++;
> - }
> -
> - if (!Config->Protocol) {
> - return EFI_NOT_FOUND;
> - }
> -
> - for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
> - if (Config->SrdsLane[Cnt] != None) {
> - return EFI_SUCCESS;
> - }
> - }
> -
> - return EFI_NOT_FOUND;
> -}
> -
> -/**
> - Function to fill serdes map information.
> -
> - @param Srds Serdes number.
> - @param SerdesProtocolMask Serdes Protocol Mask.
> - @param SerdesProtocolShift Serdes Protocol shift value.
> - @param SerDesPrtclMap Pointer to Serdes Protocol map.
> -
> -**/
> -STATIC
> -VOID
> -LSSerDesMap (
> - IN UINT32 Srds,
> - IN UINT32 SerdesProtocolMask,
> - IN UINT32 SerdesProtocolShift,
> - OUT UINT64 *SerDesPrtclMap
> - )
> -{
> - CCSR_GUR *Gur;
> - UINT32 SrdsProt;
> - INTN Lane;
> - UINT32 Flag;
> -
> - Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - *SerDesPrtclMap = 0x0;
> - Flag = 0;
> -
> - SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
> - SrdsProt >>= SerdesProtocolShift;
> -
> - DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
> - Srds + 1, SrdsProt, SrdsProt));
> -
> - if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
> - DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
> - Srds + 1, SrdsProt));
> - Flag++;
> - }
> -
> - for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> - SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> - if (LanePrtcl >= SerdesPrtclCount) {
> - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
> - Flag++;
> - } else {
> - *SerDesPrtclMap |= (1u << LanePrtcl);
> - }
> - }
> -
> - if (Flag) {
> - DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
> - } else {
> - DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
> - }
> -}
> -
> -/**
> - Get lane protocol on provided serdes lane and execute callback function.
> -
> - @param Srds Serdes number.
> - @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
> - @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
> - @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
> - @param Arg Pointer to Arguments to be passed to callback function.
> -
> -**/
> -STATIC
> -VOID
> -SerDesInstanceProbeLanes (
> - IN UINT32 Srds,
> - IN UINT32 SerdesProtocolMask,
> - IN UINT32 SerdesProtocolShift,
> - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> - IN VOID *Arg
> - )
> -{
> -
> - CCSR_GUR *Gur;
> - UINT32 SrdsProt;
> - INTN Lane;
> -
> - Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
> -
> - SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
> - SrdsProt >>= SerdesProtocolShift;
> -
> - /*
> - * Invoke callback for all lanes in the SerDes instance:
> - */
> - for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> - SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> - if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
> - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
> - } else if (LanePrtcl != None) {
> - SerDesLaneProbeCallback (LanePrtcl, Arg);
> - }
> - }
> -}
> -
> -/**
> - Probe all serdes lanes for lane protocol and execute provided callback function.
> -
> - @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
> - @param Arg Pointer to Arguments to be passed to callback function.
> -
> -**/
> -VOID
> -SerDesProbeLanes (
> - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> - IN VOID *Arg
> - )
> -{
> - SerDesInstanceProbeLanes (Srds1,
> - RCWSR_SRDS1_PRTCL_MASK,
> - RCWSR_SRDS1_PRTCL_SHIFT,
> - SerDesLaneProbeCallback,
> - Arg);
> -
> - if (PcdGetBool (PcdSerdes2Enabled)) {
> - SerDesInstanceProbeLanes (Srds2,
> - RCWSR_SRDS2_PRTCL_MASK,
> - RCWSR_SRDS2_PRTCL_SHIFT,
> - SerDesLaneProbeCallback,
> - Arg);
> - }
> -}
> -
> -/**
> - Function to return Serdes protocol map for all serdes available on board.
> -
> - @param SerDesPrtclMap Pointer to Serdes protocl map.
> -
> -**/
> -VOID
> -GetSerdesProtocolMaps (
> - OUT UINT64 *SerDesPrtclMap
> - )
> -{
> - LSSerDesMap (Srds1,
> - RCWSR_SRDS1_PRTCL_MASK,
> - RCWSR_SRDS1_PRTCL_SHIFT,
> - SerDesPrtclMap);
> -
> - if (PcdGetBool (PcdSerdes2Enabled)) {
> - LSSerDesMap (Srds2,
> - RCWSR_SRDS2_PRTCL_MASK,
> - RCWSR_SRDS2_PRTCL_SHIFT,
> - SerDesPrtclMap);
> - }
> -
> -}
> -
> -BOOLEAN
> -IsSerDesLaneProtocolConfigured (
> - IN UINT64 SerDesPrtclMap,
> - IN SERDES_PROTOCOL Device
> - )
> -{
> - if ((Device >= SerdesPrtclCount) || (Device < None)) {
> - ASSERT ((Device > None) && (Device < SerdesPrtclCount));
> - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
> - }
> -
> - return (SerDesPrtclMap & (1u << Device)) != 0 ;
> -}
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 4a1cfb3e278e..943dbac81013 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -32,10 +32,7 @@ [PcdsFixedAtBuild.common]
> # Pcds for base address and size
> #
> gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
> - gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
> - gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
> gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
> - gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104
> gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
> gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
> gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
> @@ -61,10 +58,6 @@ [PcdsFixedAtBuild.common]
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
> - gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E
> - gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F
> - gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
> - gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
>
> @@ -75,36 +68,16 @@ [PcdsFixedAtBuild.common]
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
> - gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
> - gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
> -
> - #
> - # NV Pcd
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> - gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
>
> #
> # Platform PCDs
> #
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> -
> - #
> - # Clock PCDs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
> - gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
>
> #
> # Pcds to support Big Endian IPs
> #
> - gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> - gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
> - gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
>
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 12/28] Silicon/NXP: Remove unnecessary PCDs
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (10 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 11/28] Silicon/NXP: remove not needed components Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 10:08 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 13/28] Silicon/NXP: Move dsc file Pankaj Bansal
` (17 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
The memory map of an SOC is fixed in hardware. it doesn't change with
platform that uses SOC. So, there is no need to keep PCDs for these values
and we can use macros for these in SOC header file.
Any Platform using the SOC, can make use of the SOC header file.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../Drivers/PlatformDxe/PlatformDxe.c | 15 ++--
.../Drivers/PlatformDxe/PlatformDxe.inf | 10 +--
.../Library/PlatformLib/ArmPlatformLib.inf | 21 +----
.../Library/PlatformLib/NxpQoriqLsMem.c | 79 +++++++++----------
Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 +
Silicon/NXP/LS1043A/Include/Soc.h | 44 +++++++++++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 26 ------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +-
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
Silicon/NXP/NxpQoriqLs.dec | 47 -----------
10 files changed, 97 insertions(+), 150 deletions(-)
create mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
index f89dcdeff3c1..62c400eb1a58 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -1,7 +1,7 @@
/** @file
LS1043 DXE platform driver.
- Copyright 2018-2019 NXP
+ Copyright 2018-2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -14,6 +14,7 @@
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
+#include <Soc.h>
#include <Protocol/NonDiscoverableDevice.h>
@@ -22,7 +23,7 @@ typedef struct {
UINT8 EndDesc;
} ADDRESS_SPACE_DESCRIPTOR;
-STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];
STATIC
EFI_STATUS
@@ -65,19 +66,19 @@ PopulateI2cInformation (
{
UINT32 Index;
- for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+ for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
mI2cDesc[Index].StartDesc.GenFlag = 0;
mI2cDesc[Index].StartDesc.SpecificFlag = 0;
mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
- mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
- (Index * FixedPcdGet32 (PcdI2cSize));
+ mI2cDesc[Index].StartDesc.AddrRangeMin = LS1043A_I2C0_PHYS_ADDRESS +
+ (Index * LS1043A_I2C_SIZE);
mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
- FixedPcdGet32 (PcdI2cSize) - 1;
+ LS1043A_I2C_SIZE - 1;
mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
- mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+ mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;
mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
}
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index d689cf4db58e..038d48949a39 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -2,7 +2,7 @@
#
# Component description file for LS1043 DXE platform driver.
#
-# Copyright 2018-2019 NXP
+# Copyright 2018-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -21,9 +21,10 @@ [Sources]
[Packages]
ArmPkg/ArmPkg.dec
- MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec
[LibraryClasses]
@@ -43,10 +44,5 @@ [Protocols]
gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
-[FixedPcd]
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
-
[Depex]
TRUE
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index f7ae74afc6ca..7563a1c43630 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -1,7 +1,7 @@
# @file
#
# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-# Copyright 2017, 2019 NXP
+# Copyright 2017, 2019-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -19,6 +19,7 @@ [Packages]
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec
[LibraryClasses]
@@ -35,21 +36,3 @@ [Ppis]
[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index c6c256da0727..f5fa308551aa 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -6,7 +6,7 @@
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017, 2019 NXP
+* Copyright 2017, 2019-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -16,7 +16,7 @@
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/MemoryAllocationLib.h>
-#include <DramInfo.h>
+#include <Soc.h>
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
@@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap (
{
UINTN Index;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
- DRAM_INFO DramInfo;
Index = 0;
@@ -51,24 +50,20 @@ ArmPlatformGetVirtualMemoryMap (
return;
}
- if (GetDramBankInfo (&DramInfo)) {
- DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
- return;
- }
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
-
- for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
- // DRAM1 (Must be 1st entry)
- VirtualMemoryTable[Index].PhysicalBase = DramInfo.DramRegion[Index].BaseAddress;
- VirtualMemoryTable[Index].VirtualBase = DramInfo.DramRegion[Index].BaseAddress;
- VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
- }
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
// CCSR Space
- VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// IFC region 1
@@ -85,51 +80,51 @@ ArmPlatformGetVirtualMemoryMap (
// For write transactions from non-core masters (like system DMA), the address
// should be 16 byte aligned and the data size should be multiple of 16 bytes.
//
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// QMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
// BMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
// IFC region 2
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// PCIe1
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// PCIe2
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// PCIe3
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// QSPI region
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
// End of Table
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index 74330b6205e7..6812beafe447 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -12,6 +12,8 @@
#define CLK_FREQ 100000000
+#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
+
/* SMMU Defintions */
#define SMMU_BASE_ADDR 0x09000000
#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
new file mode 100644
index 000000000000..441871757d67
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -0,0 +1,44 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+/**
+ Soc Memory Map
+**/
+#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LS1043A_DRAM0_SIZE SIZE_2GB
+#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
+#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
+
+#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
+#define LS1043A_CCSR_SIZE 0xF000000
+
+#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
+#define LS1043A_IFC0_SIZE SIZE_512MB
+#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
+#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
+
+#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
+#define LS1043A_QSPI_SIZE SIZE_512MB
+
+#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
+#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
+#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
+#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
+
+#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
+#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
+#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
+#define LS1043A_PCI_SIZE SIZE_32GB
+
+#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
+#define LS1043A_I2C_SIZE 0x10000
+#define LS1043A_I2C_NUM_CONTROLLERS 4
+
+#endif // SOC_H__
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index f57a0d95b8e1..6239cfe761e6 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -29,32 +29,6 @@ [PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
- #
- # CCSR Address Space and other attached Memories
- #
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
-
#
# Big Endian IPs
#
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index d992e53546f4..98ca2e162f7b 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -34,7 +34,7 @@ GetSysInfo (
CCSR_GUR *GurBase;
UINTN SysClk;
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
SysClk = CLK_FREQ;
SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index f75a8d19f5a5..b7c7fc78cc8f 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -36,5 +36,4 @@ [BuildOptions]
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 943dbac81013..b478560450b3 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,53 +22,6 @@ [Guids.common]
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
[PcdsFixedAtBuild.common]
- #
- # Pcds for I2C Controller
- #
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
-
- #
- # Pcds for base address and size
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
- gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
- gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
- gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
- gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
- gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
- gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
-
- #
- # IFC PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
-
#
# Platform PCDs
#
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 12/28] Silicon/NXP: Remove unnecessary PCDs
2020-03-20 14:35 ` [PATCH v2 12/28] Silicon/NXP: Remove unnecessary PCDs Pankaj Bansal
@ 2020-04-01 10:08 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 10:08 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:27 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> The memory map of an SOC is fixed in hardware. it doesn't change with
> platform that uses SOC. So, there is no need to keep PCDs for these values
> and we can use macros for these in SOC header file.
>
> Any Platform using the SOC, can make use of the SOC header file.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.c | 15 ++--
> .../Drivers/PlatformDxe/PlatformDxe.inf | 10 +--
> .../Library/PlatformLib/ArmPlatformLib.inf | 21 +----
> .../Library/PlatformLib/NxpQoriqLsMem.c | 79 +++++++++----------
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 +
> Silicon/NXP/LS1043A/Include/Soc.h | 44 +++++++++++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 26 ------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +-
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
> Silicon/NXP/NxpQoriqLs.dec | 47 -----------
> 10 files changed, 97 insertions(+), 150 deletions(-)
> create mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> index f89dcdeff3c1..62c400eb1a58 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> @@ -1,7 +1,7 @@
> /** @file
> LS1043 DXE platform driver.
>
> - Copyright 2018-2019 NXP
> + Copyright 2018-2020 NXP
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -14,6 +14,7 @@
> #include <Library/PcdLib.h>
> #include <Library/UefiBootServicesTableLib.h>
> #include <Library/UefiLib.h>
> +#include <Soc.h>
>
> #include <Protocol/NonDiscoverableDevice.h>
>
> @@ -22,7 +23,7 @@ typedef struct {
> UINT8 EndDesc;
> } ADDRESS_SPACE_DESCRIPTOR;
>
> -STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
> +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];
>
> STATIC
> EFI_STATUS
> @@ -65,19 +66,19 @@ PopulateI2cInformation (
> {
> UINT32 Index;
>
> - for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
> + for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
> mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
> mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
> mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
> mI2cDesc[Index].StartDesc.GenFlag = 0;
> mI2cDesc[Index].StartDesc.SpecificFlag = 0;
> mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
> - mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
> - (Index * FixedPcdGet32 (PcdI2cSize));
> + mI2cDesc[Index].StartDesc.AddrRangeMin = LS1043A_I2C0_PHYS_ADDRESS +
> + (Index * LS1043A_I2C_SIZE);
> mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
> - FixedPcdGet32 (PcdI2cSize) - 1;
> + LS1043A_I2C_SIZE - 1;
> mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
> - mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
> + mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;
>
> mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
> }
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> index d689cf4db58e..038d48949a39 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -2,7 +2,7 @@
> #
> # Component description file for LS1043 DXE platform driver.
> #
> -# Copyright 2018-2019 NXP
> +# Copyright 2018-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -21,9 +21,10 @@ [Sources]
>
> [Packages]
> ArmPkg/ArmPkg.dec
> - MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> + Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> @@ -43,10 +44,5 @@ [Protocols]
> gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
> gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
>
> -[FixedPcd]
> - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> -
> [Depex]
> TRUE
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> index f7ae74afc6ca..7563a1c43630 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -1,7 +1,7 @@
> # @file
> #
> # Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> -# Copyright 2017, 2019 NXP
> +# Copyright 2017, 2019-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -19,6 +19,7 @@ [Packages]
> ArmPlatformPkg/ArmPlatformPkg.dec
> EmbeddedPkg/EmbeddedPkg.dec
> MdePkg/MdePkg.dec
> + Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> @@ -35,21 +36,3 @@ [Ppis]
>
> [FixedPcd]
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> index c6c256da0727..f5fa308551aa 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -6,7 +6,7 @@
> *
> * Copyright (c) 2011, ARM Limited. All rights reserved.
> * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> -* Copyright 2017, 2019 NXP
> +* Copyright 2017, 2019-2020 NXP
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -16,7 +16,7 @@
> #include <Library/DebugLib.h>
> #include <Library/PcdLib.h>
> #include <Library/MemoryAllocationLib.h>
> -#include <DramInfo.h>
> +#include <Soc.h>
>
> #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
>
> @@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap (
> {
> UINTN Index;
> ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> - DRAM_INFO DramInfo;
>
> Index = 0;
>
> @@ -51,24 +50,20 @@ ArmPlatformGetVirtualMemoryMap (
> return;
> }
>
> - if (GetDramBankInfo (&DramInfo)) {
> - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> - return;
> - }
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>
> -
> - for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
> - // DRAM1 (Must be 1st entry)
> - VirtualMemoryTable[Index].PhysicalBase = DramInfo.DramRegion[Index].BaseAddress;
> - VirtualMemoryTable[Index].VirtualBase = DramInfo.DramRegion[Index].BaseAddress;
> - VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> - }
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>
> // CCSR Space
> - VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> // IFC region 1
> @@ -85,51 +80,51 @@ ArmPlatformGetVirtualMemoryMap (
> // For write transactions from non-core masters (like system DMA), the address
> // should be 16 byte aligned and the data size should be multiple of 16 bytes.
> //
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> // QMAN SWP
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
> + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
>
> // BMAN SWP
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
> + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
>
> // IFC region 2
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> // PCIe1
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
> + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> // PCIe2
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
> + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> // PCIe3
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
> + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> // QSPI region
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
>
> // End of Table
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> index 74330b6205e7..6812beafe447 100644
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> @@ -12,6 +12,8 @@
>
> #define CLK_FREQ 100000000
>
> +#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> +
> /* SMMU Defintions */
> #define SMMU_BASE_ADDR 0x09000000
> #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
> new file mode 100644
> index 000000000000..441871757d67
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> @@ -0,0 +1,44 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef SOC_H__
> +#define SOC_H__
> +
> +/**
> + Soc Memory Map
> +**/
> +#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> +#define LS1043A_DRAM0_SIZE SIZE_2GB
> +#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> +#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> +
> +#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> +#define LS1043A_CCSR_SIZE 0xF000000
> +
> +#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> +#define LS1043A_IFC0_SIZE SIZE_512MB
> +#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> +#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> +
> +#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> +#define LS1043A_QSPI_SIZE SIZE_512MB
> +
> +#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> +#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> +#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> +#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> +
> +#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> +#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> +#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> +#define LS1043A_PCI_SIZE SIZE_32GB
> +
> +#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> +#define LS1043A_I2C_SIZE 0x10000
> +#define LS1043A_I2C_NUM_CONTROLLERS 4
> +
> +#endif // SOC_H__
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index f57a0d95b8e1..6239cfe761e6 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -29,32 +29,6 @@ [PcdsFixedAtBuild.common]
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
>
> - #
> - # CCSR Address Space and other attached Memories
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> -
> #
> # Big Endian IPs
> #
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index d992e53546f4..98ca2e162f7b 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -34,7 +34,7 @@ GetSysInfo (
> CCSR_GUR *GurBase;
> UINTN SysClk;
>
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> SysClk = CLK_FREQ;
>
> SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index f75a8d19f5a5..b7c7fc78cc8f 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -36,5 +36,4 @@ [BuildOptions]
> [FixedPcd]
> gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 943dbac81013..b478560450b3 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -22,53 +22,6 @@ [Guids.common]
> gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
>
> [PcdsFixedAtBuild.common]
> - #
> - # Pcds for I2C Controller
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
> - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
> -
> - #
> - # Pcds for base address and size
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
> - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
> - gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
> - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
> - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
> - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
> - gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
> - gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
> - gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
> - gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
> -
> - #
> - # IFC PCDs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
> -
> #
> # Platform PCDs
> #
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 13/28] Silicon/NXP: Move dsc file
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (11 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 12/28] Silicon/NXP: Remove unnecessary PCDs Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 10:10 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 14/28] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Pankaj Bansal
` (16 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
As per convention being followed in edk2-platforms, keep the dec
file and dsc file together.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
{Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc (100%)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 385b6e067e26..1975f2c4c52c 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -22,7 +22,7 @@ [Defines]
OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
-!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
[LibraryClasses.common]
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
similarity index 100%
rename from Platform/NXP/NxpQoriqLs.dsc.inc
rename to Silicon/NXP/NxpQoriqLs.dsc.inc
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 13/28] Silicon/NXP: Move dsc file
2020-03-20 14:35 ` [PATCH v2 13/28] Silicon/NXP: Move dsc file Pankaj Bansal
@ 2020-04-01 10:10 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 10:10 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:28 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> As per convention being followed in edk2-platforms, keep the dec
> file and dsc file together.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
> {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 0
> 2 files changed, 1 insertion(+), 1 deletion(-)
> rename {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc (100%)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 385b6e067e26..1975f2c4c52c 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -22,7 +22,7 @@ [Defines]
> OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
> FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>
> -!include Platform/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/NxpQoriqLs.dsc.inc
> !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
>
> [LibraryClasses.common]
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> similarity index 100%
> rename from Platform/NXP/NxpQoriqLs.dsc.inc
> rename to Silicon/NXP/NxpQoriqLs.dsc.inc
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 14/28] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (12 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 13/28] Silicon/NXP: Move dsc file Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 10:14 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib Pankaj Bansal
` (15 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Keep the names and location of files as mentioned in ArmPlatformPkg.
This helps in porting the common changes (if any in future) easily.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
.../AArch64/ArmPlatformHelper.S} | 2 +-
.../Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c | 2 +-
.../{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf | 4 ++--
.../NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} | 0
5 files changed, 5 insertions(+), 5 deletions(-)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsHelper.S => ArmPlatformLib/AArch64/ArmPlatformHelper.S} (88%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c (93%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf (89%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} (100%)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 1975f2c4c52c..e5383aaf0cc5 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -26,7 +26,7 @@ [Defines]
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
[LibraryClasses.common]
- ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
[PcdsFixedAtBuild.common]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
similarity index 88%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
index 84ee8c9f9700..dfbf73675a2d 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -1,7 +1,7 @@
# @file
#
# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-# Copyright 2017 NXP
+# Copyright 2017, 2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
similarity index 93%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index eac7d4aa4e47..718c71bf02eb 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -6,7 +6,7 @@
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017 NXP
+* Copyright 2017, 2020 NXP
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
similarity index 89%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7563a1c43630..7a43ad86d183 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -27,8 +27,8 @@ [LibraryClasses]
SocLib
[Sources.common]
- NxpQoriqLsHelper.S | GCC
- NxpQoriqLsMem.c
+ AArch64/ArmPlatformHelper.S | GCC
+ ArmPlatformLibMem.c
ArmPlatformLib.c
[Ppis]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
similarity index 100%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 14/28] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg
2020-03-20 14:35 ` [PATCH v2 14/28] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Pankaj Bansal
@ 2020-04-01 10:14 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 10:14 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:29 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Keep the names and location of files as mentioned in ArmPlatformPkg.
> This helps in porting the common changes (if any in future) easily.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
> .../AArch64/ArmPlatformHelper.S} | 2 +-
> .../Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c | 2 +-
> .../{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf | 4 ++--
> .../NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} | 0
> 5 files changed, 5 insertions(+), 5 deletions(-)
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsHelper.S => ArmPlatformLib/AArch64/ArmPlatformHelper.S} (88%)
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c (93%)
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf (89%)
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} (100%)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 1975f2c4c52c..e5383aaf0cc5 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -26,7 +26,7 @@ [Defines]
> !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
>
> [LibraryClasses.common]
> - ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
>
> [PcdsFixedAtBuild.common]
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> similarity index 88%
> rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> index 84ee8c9f9700..dfbf73675a2d 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> @@ -1,7 +1,7 @@
> # @file
> #
> # Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> -# Copyright 2017 NXP
> +# Copyright 2017, 2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> similarity index 93%
> rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index eac7d4aa4e47..718c71bf02eb 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -6,7 +6,7 @@
> *
> * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> -* Copyright 2017 NXP
> +* Copyright 2017, 2020 NXP
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> **/
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> similarity index 89%
> rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 7563a1c43630..7a43ad86d183 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -27,8 +27,8 @@ [LibraryClasses]
> SocLib
>
> [Sources.common]
> - NxpQoriqLsHelper.S | GCC
> - NxpQoriqLsMem.c
> + AArch64/ArmPlatformHelper.S | GCC
> + ArmPlatformLibMem.c
> ArmPlatformLib.c
>
> [Ppis]
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> similarity index 100%
> rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (13 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 14/28] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 12:42 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 16/28] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs Pankaj Bansal
` (14 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
RAM retrieval using SMC commands is common to all Layerscape SOCs.
Therefore, move it to commom MemoryInit Pei Lib.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Include/DramInfo.h | 38 -----
.../Library/MemoryInitPei/MemoryInitPeiLib.c | 137 ++++++++++++++----
.../Library/MemoryInitPei/MemoryInitPeiLib.h | 25 ++++
.../MemoryInitPei/MemoryInitPeiLib.inf | 7 +-
Silicon/NXP/Library/SocLib/Chassis.c | 67 ---------
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
6 files changed, 140 insertions(+), 135 deletions(-)
delete mode 100644 Silicon/NXP/Include/DramInfo.h
create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
deleted file mode 100644
index a934aaeff1f5..000000000000
--- a/Silicon/NXP/Include/DramInfo.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @file
-* Header defining the structure for Dram Information
-*
-* Copyright 2019 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef DRAM_INFO_H_
-#define DRAM_INFO_H_
-
-#include <Uefi/UefiBaseType.h>
-
-#define SMC_DRAM_BANK_INFO (0xC200FF12)
-
-typedef struct {
- UINTN BaseAddress;
- UINTN Size;
-} DRAM_REGION_INFO;
-
-typedef struct {
- UINT32 NumOfDrams;
- UINT32 Reserved;
- DRAM_REGION_INFO DramRegion[3];
-} DRAM_INFO;
-
-EFI_STATUS
-GetDramBankInfo (
- IN OUT DRAM_INFO *DramInfo
- );
-
-VOID
-UpdateDpaaDram (
- IN OUT DRAM_INFO *DramInfo
- );
-
-#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
index 3ea773678667..54d026ef1270 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
@@ -17,8 +17,10 @@
#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
+#include <Library/ArmSmcLib.h>
+
+#include "MemoryInitPeiLib.h"
-#include <DramInfo.h>
VOID
BuildMemoryTypeInformationHob (
@@ -68,10 +70,17 @@ MemoryPeim (
)
{
ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ ARM_SMC_ARGS ArmSmcArgs;
+ INT32 Index;
+ UINTN DramSize;
+ UINTN BaseAddress;
+ UINTN Size;
+ UINTN Top;
+ DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS];
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
- EFI_PEI_HOB_POINTERS NextHob;
- BOOLEAN Found;
- DRAM_INFO DramInfo;
+ UINTN FdBase;
+ UINTN FdTop;
+ BOOLEAN FoundSystemMem;
// Get Virtual Memory Map from the Platform Library
ArmPlatformGetVirtualMemoryMap (&MemoryTable);
@@ -94,40 +103,112 @@ MemoryPeim (
EFI_RESOURCE_ATTRIBUTE_TESTED
);
- if (GetDramBankInfo (&DramInfo)) {
- DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
- return EFI_UNSUPPORTED;
- }
-
- while (DramInfo.NumOfDrams--) {
- //
- // Check if the resource for the main system memory has been declared
- //
- Found = FALSE;
- NextHob.Raw = GetHobList ();
- while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
- if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
- (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
- (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
- DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
- {
- Found = TRUE;
- break;
+ FoundSystemMem = FALSE;
+ ZeroMem (DramRegions, sizeof (DramRegions));
+
+ Index = -1;
+ do {
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = Index++;
+
+ ArmCallSmc (&ArmSmcArgs);
+ ASSERT (!(ArmSmcArgs.Arg0 && !Index));
+ if (!Index) {
+ DramSize = ArmSmcArgs.Arg1;
+ } else {
+ if (!ArmSmcArgs.Arg0) {
+ BaseAddress = ArmSmcArgs.Arg1;
+ Size = ArmSmcArgs.Arg2;
+ ASSERT (BaseAddress && Size);
+
+ DramRegions[Index - 1].BaseAddress = BaseAddress;
+ DramRegions[Index - 1].Size = Size;
+ DramSize -= Size;
+
+ DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
+ Index, BaseAddress, Size));
}
- NextHob.Raw = GET_NEXT_HOB (NextHob);
+ }
+ } while (DramSize && Index < MAX_DRAM_REGIONS);
+
+ ASSERT (!DramSize);
+
+ FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+
+ // Declare memory regios to system
+ for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
+ if (!DramRegions[Index].Size) {
+ continue;
}
- if (!Found) {
- // Reserved the memory space occupied by the firmware volume
+ BaseAddress = DramRegions[Index].BaseAddress;
+ Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
+
+ // EDK2 does not have the concept of boot firmware copied into DRAM.
+ // To avoid the DXE core to overwrite this area we must create a memory
+ // allocation HOB for the region, but this only works if we split off the
+ // underlying resource descriptor as well.
+ if (FdBase >= BaseAddress && FdTop <= Top) {
+ // Update Size
+ Size = FdBase - BaseAddress;
+ if (Size) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ BaseAddress,
+ Size
+ );
+ }
+ // create the System Memory HOB for the firmware
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
- DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
- DramInfo.DramRegion[DramInfo.NumOfDrams].Size
+ FdBase,
+ PcdGet32 (PcdFdSize)
);
+ // Create the System Memory HOB for the remaining region (top of the FD)s
+ Size = Top - FdTop;
+ if (Size) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FdTop,
+ Size
+ );
+ };
+ // Mark the memory covering the Firmware Device as boot services data
+ BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
+ FixedPcdGet32 (PcdFdSize),
+ EfiBootServicesData);
+ } else {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ DramRegions[Index].BaseAddress,
+ DramRegions[Index].Size
+ );
+ }
+
+ if (FoundSystemMem) {
+ continue;
+ }
+
+ BaseAddress = DramRegions[Index].BaseAddress;
+ Size = DramRegions[Index].Size;
+ Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
+
+ if (FdBase >= BaseAddress && FdTop <= Top) {
+ Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ }
+
+ if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
+ FoundSystemMem = TRUE;
}
}
+ ASSERT (FoundSystemMem);
+
// Build Memory Allocation Hob
InitMmu (MemoryTable);
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
new file mode 100644
index 000000000000..edbf0ceaf638
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
@@ -0,0 +1,25 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef MEMORY_INIT_PEI_LIB_H_
+#define MEMORY_INIT_PEI_LIB_H_
+
+#include <Uefi.h>
+
+// Specifies the Maximum regions onto which DDR memory can be mapped in
+// a Platform
+#define MAX_DRAM_REGIONS 3
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+typedef struct {
+ UINTN BaseAddress;
+ UINTN Size;
+} DRAM_REGION_INFO;
+
+#endif // MEMORY_INIT_PEI_LIB_H_
+
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
index a5bd39415def..ad2371115b17 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -18,7 +18,6 @@ [Defines]
[Sources]
MemoryInitPeiLib.c
-
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
@@ -30,6 +29,7 @@ [Packages]
[LibraryClasses]
ArmMmuLib
ArmPlatformLib
+ ArmSmcLib
DebugLib
HobLib
PcdLib
@@ -40,6 +40,11 @@ [Guids]
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 847331a63152..1ef99e8de25f 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -22,7 +22,6 @@
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
-#include <DramInfo.h>
#include "NxpChassis.h"
UINT32
@@ -75,69 +74,3 @@ SmmuInit (
MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
}
-UINTN
-GetDramSize (
- IN VOID
- )
-{
- ARM_SMC_ARGS ArmSmcArgs;
-
- ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
- ArmSmcArgs.Arg1 = -1;
-
- ArmCallSmc (&ArmSmcArgs);
-
- if (ArmSmcArgs.Arg0) {
- return 0;
- } else {
- return ArmSmcArgs.Arg1;
- }
-}
-
-EFI_STATUS
-GetDramBankInfo (
- IN OUT DRAM_INFO *DramInfo
- )
-{
- ARM_SMC_ARGS ArmSmcArgs;
- UINT32 I;
- UINTN DramSize;
-
- DramSize = GetDramSize ();
- DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
-
- // Ensure DramSize has been set
- ASSERT (DramSize != 0);
-
- I = 0;
-
- do {
- ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
- ArmSmcArgs.Arg1 = I;
-
- ArmCallSmc (&ArmSmcArgs);
- if (ArmSmcArgs.Arg0) {
- if (I > 0) {
- break;
- } else {
- ASSERT (ArmSmcArgs.Arg0 == 0);
- }
- }
-
- DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
- DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
-
- DramSize -= DramInfo->DramRegion[I].Size;
-
- DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
- I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
-
- I++;
- } while (DramSize);
-
- DramInfo->NumOfDrams = I;
-
- DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
-
- return EFI_SUCCESS;
-}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index b7c7fc78cc8f..99d89498e0e2 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -20,7 +20,6 @@ [Packages]
Silicon/NXP/NxpQoriqLs.dec
[LibraryClasses]
- ArmSmcLib
BaseLib
DebugLib
IoAccessLib
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib
2020-03-20 14:35 ` [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib Pankaj Bansal
@ 2020-04-01 12:42 ` Leif Lindholm
2020-04-06 10:08 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 12:42 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:30 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> RAM retrieval using SMC commands is common to all Layerscape SOCs.
> Therefore, move it to commom MemoryInit Pei Lib.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/Include/DramInfo.h | 38 -----
> .../Library/MemoryInitPei/MemoryInitPeiLib.c | 137 ++++++++++++++----
> .../Library/MemoryInitPei/MemoryInitPeiLib.h | 25 ++++
> .../MemoryInitPei/MemoryInitPeiLib.inf | 7 +-
> Silicon/NXP/Library/SocLib/Chassis.c | 67 ---------
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
> 6 files changed, 140 insertions(+), 135 deletions(-)
> delete mode 100644 Silicon/NXP/Include/DramInfo.h
> create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
>
> diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
> deleted file mode 100644
> index a934aaeff1f5..000000000000
> --- a/Silicon/NXP/Include/DramInfo.h
> +++ /dev/null
> @@ -1,38 +0,0 @@
> -/** @file
> -* Header defining the structure for Dram Information
> -*
> -* Copyright 2019 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef DRAM_INFO_H_
> -#define DRAM_INFO_H_
> -
> -#include <Uefi/UefiBaseType.h>
> -
> -#define SMC_DRAM_BANK_INFO (0xC200FF12)
> -
> -typedef struct {
> - UINTN BaseAddress;
> - UINTN Size;
> -} DRAM_REGION_INFO;
> -
> -typedef struct {
> - UINT32 NumOfDrams;
> - UINT32 Reserved;
> - DRAM_REGION_INFO DramRegion[3];
> -} DRAM_INFO;
> -
> -EFI_STATUS
> -GetDramBankInfo (
> - IN OUT DRAM_INFO *DramInfo
> - );
> -
> -VOID
> -UpdateDpaaDram (
> - IN OUT DRAM_INFO *DramInfo
> - );
> -
> -#endif /* DRAM_INFO_H_ */
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> index 3ea773678667..54d026ef1270 100644
> --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> @@ -17,8 +17,10 @@
> #include <Library/HobLib.h>
> #include <Library/MemoryAllocationLib.h>
> #include <Library/PcdLib.h>
> +#include <Library/ArmSmcLib.h>
Please insert alpabetically sorted.
> +
> +#include "MemoryInitPeiLib.h"
>
> -#include <DramInfo.h>
>
> VOID
> BuildMemoryTypeInformationHob (
> @@ -68,10 +70,17 @@ MemoryPeim (
> )
> {
> ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> + ARM_SMC_ARGS ArmSmcArgs;
> + INT32 Index;
> + UINTN DramSize;
> + UINTN BaseAddress;
> + UINTN Size;
> + UINTN Top;
> + DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS];
> EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> - EFI_PEI_HOB_POINTERS NextHob;
> - BOOLEAN Found;
> - DRAM_INFO DramInfo;
> + UINTN FdBase;
> + UINTN FdTop;
> + BOOLEAN FoundSystemMem;
>
> // Get Virtual Memory Map from the Platform Library
> ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> @@ -94,40 +103,112 @@ MemoryPeim (
> EFI_RESOURCE_ATTRIBUTE_TESTED
> );
>
> - if (GetDramBankInfo (&DramInfo)) {
> - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> - return EFI_UNSUPPORTED;
> - }
> -
> - while (DramInfo.NumOfDrams--) {
> - //
> - // Check if the resource for the main system memory has been declared
> - //
> - Found = FALSE;
> - NextHob.Raw = GetHobList ();
> - while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
> - if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
> - (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
> - (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
> - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
> - {
> - Found = TRUE;
> - break;
> + FoundSystemMem = FALSE;
> + ZeroMem (DramRegions, sizeof (DramRegions));
> +
> + Index = -1;
> + do {
> + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> + ArmSmcArgs.Arg1 = Index++;
> +
> + ArmCallSmc (&ArmSmcArgs);
> + ASSERT (!(ArmSmcArgs.Arg0 && !Index));
This is being a bit too clever for its own good.
We're verifying that if one of the inputs to the function we just
called is zero (i.e. is the first time around the loop), the value
returned in the struct must also be zero?
Is this equivalent to
if (Index == 0) {
ASSERT (ArmSmcArgs.Arg0 == SMC_WHATEVER_OK);
}
?
If so, please use that form.
Don't use !Index when you mean Index == 0.
Regardless, a short explanation of the protocol and expected responses
are needed unless the code can be made more self-explanatory.
> + if (!Index) {
> + DramSize = ArmSmcArgs.Arg1;
> + } else {
> + if (!ArmSmcArgs.Arg0) {
> + BaseAddress = ArmSmcArgs.Arg1;
> + Size = ArmSmcArgs.Arg2;
> + ASSERT (BaseAddress && Size);
> +
> + DramRegions[Index - 1].BaseAddress = BaseAddress;
> + DramRegions[Index - 1].Size = Size;
There's a lot of "-1" going on in this function, which should be
possible to avoid by incrementing Index at the end of the loop and
initializing it to 0. The compiler *will* do a better job at
optimizing code for you in all but the most exceptional cases, so try
to avoid optimising C.
> + DramSize -= Size;
> +
> + DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
> + Index, BaseAddress, Size));
> }
> - NextHob.Raw = GET_NEXT_HOB (NextHob);
> + }
> + } while (DramSize && Index < MAX_DRAM_REGIONS);
> +
> + ASSERT (!DramSize);
And this (human language) semantically says "throw an exception if we
have RAM".
I can sort of start to make educated guesses at this point, but I
shouldn't have to. If making the ArmCallSmc with .Arg1 == 0 is a
special request to report the total amount of RAM in the system, that
shouldn't be part of the same loop as the calls extracting the size of
individual regions.
> +
> + FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
> + FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
> +
> + // Declare memory regios to system
regions
> + for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
I guess what confuses me about this loop is the combination of:
- Iterating over the DRAM regions backwards (optimization?)
- Not terminating the iteration once all of the Fd region has been
covered (the opposite of optimization).
Could something be done about that?
/
Leif
> + if (!DramRegions[Index].Size) {
> + continue;
> }
>
> - if (!Found) {
> - // Reserved the memory space occupied by the firmware volume
> + BaseAddress = DramRegions[Index].BaseAddress;
> + Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
> +
> + // EDK2 does not have the concept of boot firmware copied into DRAM.
> + // To avoid the DXE core to overwrite this area we must create a memory
> + // allocation HOB for the region, but this only works if we split off the
> + // underlying resource descriptor as well.
> + if (FdBase >= BaseAddress && FdTop <= Top) {
> + // Update Size
> + Size = FdBase - BaseAddress;
> + if (Size) {
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + BaseAddress,
> + Size
> + );
> + }
> + // create the System Memory HOB for the firmware
> BuildResourceDescriptorHob (
> EFI_RESOURCE_SYSTEM_MEMORY,
> ResourceAttributes,
> - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
> - DramInfo.DramRegion[DramInfo.NumOfDrams].Size
> + FdBase,
> + PcdGet32 (PcdFdSize)
> );
> + // Create the System Memory HOB for the remaining region (top of the FD)s
> + Size = Top - FdTop;
> + if (Size) {
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + FdTop,
> + Size
> + );
> + };
> + // Mark the memory covering the Firmware Device as boot services data
> + BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
> + FixedPcdGet32 (PcdFdSize),
> + EfiBootServicesData);
> + } else {
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + DramRegions[Index].BaseAddress,
> + DramRegions[Index].Size
> + );
> + }
> +
> + if (FoundSystemMem) {
> + continue;
> + }
> +
> + BaseAddress = DramRegions[Index].BaseAddress;
> + Size = DramRegions[Index].Size;
> + Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
> +
> + if (FdBase >= BaseAddress && FdTop <= Top) {
> + Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
> + }
> +
> + if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
> + FoundSystemMem = TRUE;
> }
> }
>
> + ASSERT (FoundSystemMem);
> +
> // Build Memory Allocation Hob
> InitMmu (MemoryTable);
>
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> new file mode 100644
> index 000000000000..edbf0ceaf638
> --- /dev/null
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> @@ -0,0 +1,25 @@
> +/** @file
> +*
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef MEMORY_INIT_PEI_LIB_H_
> +#define MEMORY_INIT_PEI_LIB_H_
> +
> +#include <Uefi.h>
> +
> +// Specifies the Maximum regions onto which DDR memory can be mapped in
> +// a Platform
> +#define MAX_DRAM_REGIONS 3
> +#define SMC_DRAM_BANK_INFO (0xC200FF12)
> +
> +typedef struct {
> + UINTN BaseAddress;
> + UINTN Size;
> +} DRAM_REGION_INFO;
> +
> +#endif // MEMORY_INIT_PEI_LIB_H_
> +
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> index a5bd39415def..ad2371115b17 100644
> --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> @@ -18,7 +18,6 @@ [Defines]
> [Sources]
> MemoryInitPeiLib.c
>
> -
> [Packages]
> ArmPkg/ArmPkg.dec
> ArmPlatformPkg/ArmPlatformPkg.dec
> @@ -30,6 +29,7 @@ [Packages]
> [LibraryClasses]
> ArmMmuLib
> ArmPlatformLib
> + ArmSmcLib
> DebugLib
> HobLib
> PcdLib
> @@ -40,6 +40,11 @@ [Guids]
> [FeaturePcd]
> gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
>
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFdBaseAddress
> + gArmTokenSpaceGuid.PcdFdSize
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
> +
> [Pcd]
> gArmTokenSpaceGuid.PcdSystemMemoryBase
> gArmTokenSpaceGuid.PcdSystemMemorySize
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index 847331a63152..1ef99e8de25f 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -22,7 +22,6 @@
> #include <Library/PrintLib.h>
> #include <Library/SerialPortLib.h>
>
> -#include <DramInfo.h>
> #include "NxpChassis.h"
>
> UINT32
> @@ -75,69 +74,3 @@ SmmuInit (
> MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> }
>
> -UINTN
> -GetDramSize (
> - IN VOID
> - )
> -{
> - ARM_SMC_ARGS ArmSmcArgs;
> -
> - ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> - ArmSmcArgs.Arg1 = -1;
> -
> - ArmCallSmc (&ArmSmcArgs);
> -
> - if (ArmSmcArgs.Arg0) {
> - return 0;
> - } else {
> - return ArmSmcArgs.Arg1;
> - }
> -}
> -
> -EFI_STATUS
> -GetDramBankInfo (
> - IN OUT DRAM_INFO *DramInfo
> - )
> -{
> - ARM_SMC_ARGS ArmSmcArgs;
> - UINT32 I;
> - UINTN DramSize;
> -
> - DramSize = GetDramSize ();
> - DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
> -
> - // Ensure DramSize has been set
> - ASSERT (DramSize != 0);
> -
> - I = 0;
> -
> - do {
> - ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> - ArmSmcArgs.Arg1 = I;
> -
> - ArmCallSmc (&ArmSmcArgs);
> - if (ArmSmcArgs.Arg0) {
> - if (I > 0) {
> - break;
> - } else {
> - ASSERT (ArmSmcArgs.Arg0 == 0);
> - }
> - }
> -
> - DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
> - DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
> -
> - DramSize -= DramInfo->DramRegion[I].Size;
> -
> - DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
> - I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
> -
> - I++;
> - } while (DramSize);
> -
> - DramInfo->NumOfDrams = I;
> -
> - DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
> -
> - return EFI_SUCCESS;
> -}
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index b7c7fc78cc8f..99d89498e0e2 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -20,7 +20,6 @@ [Packages]
> Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> - ArmSmcLib
> BaseLib
> DebugLib
> IoAccessLib
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib
2020-04-01 12:42 ` Leif Lindholm
@ 2020-04-06 10:08 ` Pankaj Bansal
2020-04-06 11:48 ` Leif Lindholm
0 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-06 10:08 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Wednesday, April 1, 2020 6:13 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib
>
> On Fri, Mar 20, 2020 at 20:05:30 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > RAM retrieval using SMC commands is common to all Layerscape SOCs.
> > Therefore, move it to commom MemoryInit Pei Lib.
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > Silicon/NXP/Include/DramInfo.h | 38 -----
> > .../Library/MemoryInitPei/MemoryInitPeiLib.c | 137 ++++++++++++++----
> > .../Library/MemoryInitPei/MemoryInitPeiLib.h | 25 ++++
> > .../MemoryInitPei/MemoryInitPeiLib.inf | 7 +-
> > Silicon/NXP/Library/SocLib/Chassis.c | 67 ---------
> > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
> > 6 files changed, 140 insertions(+), 135 deletions(-)
> > delete mode 100644 Silicon/NXP/Include/DramInfo.h
> > create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> >
> > diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
> > deleted file mode 100644
> > index a934aaeff1f5..000000000000
> > --- a/Silicon/NXP/Include/DramInfo.h
> > +++ /dev/null
> > @@ -1,38 +0,0 @@
> > -/** @file
> > -* Header defining the structure for Dram Information
> > -*
> > -* Copyright 2019 NXP
> > -*
> > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > -*
> > -**/
> > -
> > -#ifndef DRAM_INFO_H_
> > -#define DRAM_INFO_H_
> > -
> > -#include <Uefi/UefiBaseType.h>
> > -
> > -#define SMC_DRAM_BANK_INFO (0xC200FF12)
> > -
> > -typedef struct {
> > - UINTN BaseAddress;
> > - UINTN Size;
> > -} DRAM_REGION_INFO;
> > -
> > -typedef struct {
> > - UINT32 NumOfDrams;
> > - UINT32 Reserved;
> > - DRAM_REGION_INFO DramRegion[3];
> > -} DRAM_INFO;
> > -
> > -EFI_STATUS
> > -GetDramBankInfo (
> > - IN OUT DRAM_INFO *DramInfo
> > - );
> > -
> > -VOID
> > -UpdateDpaaDram (
> > - IN OUT DRAM_INFO *DramInfo
> > - );
> > -
> > -#endif /* DRAM_INFO_H_ */
> > diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> > index 3ea773678667..54d026ef1270 100644
> > --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> > +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> > @@ -17,8 +17,10 @@
> > #include <Library/HobLib.h>
> > #include <Library/MemoryAllocationLib.h>
> > #include <Library/PcdLib.h>
> > +#include <Library/ArmSmcLib.h>
>
> Please insert alpabetically sorted.
Ok.
>
> > +
> > +#include "MemoryInitPeiLib.h"
> >
> > -#include <DramInfo.h>
> >
> > VOID
> > BuildMemoryTypeInformationHob (
> > @@ -68,10 +70,17 @@ MemoryPeim (
> > )
> > {
> > ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> > + ARM_SMC_ARGS ArmSmcArgs;
> > + INT32 Index;
> > + UINTN DramSize;
> > + UINTN BaseAddress;
> > + UINTN Size;
> > + UINTN Top;
> > + DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS];
> > EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> > - EFI_PEI_HOB_POINTERS NextHob;
> > - BOOLEAN Found;
> > - DRAM_INFO DramInfo;
> > + UINTN FdBase;
> > + UINTN FdTop;
> > + BOOLEAN FoundSystemMem;
> >
> > // Get Virtual Memory Map from the Platform Library
> > ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> > @@ -94,40 +103,112 @@ MemoryPeim (
> > EFI_RESOURCE_ATTRIBUTE_TESTED
> > );
> >
> > - if (GetDramBankInfo (&DramInfo)) {
> > - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> > - return EFI_UNSUPPORTED;
> > - }
> > -
> > - while (DramInfo.NumOfDrams--) {
> > - //
> > - // Check if the resource for the main system memory has been declared
> > - //
> > - Found = FALSE;
> > - NextHob.Raw = GetHobList ();
> > - while ((NextHob.Raw = GetNextHob
> (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
> > - if ((NextHob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_SYSTEM_MEMORY) &&
> > - (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >=
> NextHob.ResourceDescriptor->PhysicalStart) &&
> > - (NextHob.ResourceDescriptor->PhysicalStart +
> NextHob.ResourceDescriptor->ResourceLength <=
> > - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress +
> DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
> > - {
> > - Found = TRUE;
> > - break;
> > + FoundSystemMem = FALSE;
> > + ZeroMem (DramRegions, sizeof (DramRegions));
> > +
> > + Index = -1;
> > + do {
> > + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> > + ArmSmcArgs.Arg1 = Index++;
> > +
> > + ArmCallSmc (&ArmSmcArgs);
> > + ASSERT (!(ArmSmcArgs.Arg0 && !Index));
>
> This is being a bit too clever for its own good.
> We're verifying that if one of the inputs to the function we just
> called is zero (i.e. is the first time around the loop), the value
> returned in the struct must also be zero?
>
> Is this equivalent to
> if (Index == 0) {
> ASSERT (ArmSmcArgs.Arg0 == SMC_WHATEVER_OK);
> }
> ?
>
> If so, please use that form.
>
> Don't use !Index when you mean Index == 0.
>
> Regardless, a short explanation of the protocol and expected responses
> are needed unless the code can be made more self-explanatory.
Ok. I will provide more detailed comments and try to simplify the code accordingly.
>
> > + if (!Index) {
> > + DramSize = ArmSmcArgs.Arg1;
> > + } else {
> > + if (!ArmSmcArgs.Arg0) {
> > + BaseAddress = ArmSmcArgs.Arg1;
> > + Size = ArmSmcArgs.Arg2;
> > + ASSERT (BaseAddress && Size);
> > +
> > + DramRegions[Index - 1].BaseAddress = BaseAddress;
> > + DramRegions[Index - 1].Size = Size;
>
> There's a lot of "-1" going on in this function, which should be
> possible to avoid by incrementing Index at the end of the loop and
> initializing it to 0. The compiler *will* do a better job at
> optimizing code for you in all but the most exceptional cases, so try
> to avoid optimising C.
Ok.
>
> > + DramSize -= Size;
> > +
> > + DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
> > + Index, BaseAddress, Size));
> > }
> > - NextHob.Raw = GET_NEXT_HOB (NextHob);
> > + }
> > + } while (DramSize && Index < MAX_DRAM_REGIONS);
> > +
> > + ASSERT (!DramSize);
>
> And this (human language) semantically says "throw an exception if we
> have RAM".
>
> I can sort of start to make educated guesses at this point, but I
> shouldn't have to. If making the ArmCallSmc with .Arg1 == 0 is a
> special request to report the total amount of RAM in the system, that
> shouldn't be part of the same loop as the calls extracting the size of
> individual regions.
OK.
>
> > +
> > + FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
> > + FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
> > +
> > + // Declare memory regios to system
>
> regions
OK
>
> > + for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
>
> I guess what confuses me about this loop is the combination of:
> - Iterating over the DRAM regions backwards (optimization?)
> - Not terminating the iteration once all of the Fd region has been
> covered (the opposite of optimization).
>
> Could something be done about that?
>
The DRAM region info is sorted based on the RAM address is SOC memory map.
i.e. region0 is at lower address, as compared to region1.
The goal to start from last region is to find the topmost RAM region that can contain UEFI DXE region i.e. PcdSystemMemoryUefiRegionSize.
In the upcoming patches I would update the PcdSystemMemoryBase dynamically from that region.
If UEFI were to allocate any reserved or runtime region, it would be allocated from topmost RAM region.
This ensures that maximum amount of lower RAM (32 bit addresses) are left for OS to allocate to devices that can only
work with 32bit physical addresses. E.g. legacy devices that need to DMA to 32bit addresses.
> /
> Leif
>
> > + if (!DramRegions[Index].Size) {
> > + continue;
> > }
> >
> > - if (!Found) {
> > - // Reserved the memory space occupied by the firmware volume
> > + BaseAddress = DramRegions[Index].BaseAddress;
> > + Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
> > +
> > + // EDK2 does not have the concept of boot firmware copied into DRAM.
> > + // To avoid the DXE core to overwrite this area we must create a memory
> > + // allocation HOB for the region, but this only works if we split off the
> > + // underlying resource descriptor as well.
> > + if (FdBase >= BaseAddress && FdTop <= Top) {
> > + // Update Size
> > + Size = FdBase - BaseAddress;
> > + if (Size) {
> > + BuildResourceDescriptorHob (
> > + EFI_RESOURCE_SYSTEM_MEMORY,
> > + ResourceAttributes,
> > + BaseAddress,
> > + Size
> > + );
> > + }
> > + // create the System Memory HOB for the firmware
> > BuildResourceDescriptorHob (
> > EFI_RESOURCE_SYSTEM_MEMORY,
> > ResourceAttributes,
> > - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
> > - DramInfo.DramRegion[DramInfo.NumOfDrams].Size
> > + FdBase,
> > + PcdGet32 (PcdFdSize)
> > );
> > + // Create the System Memory HOB for the remaining region (top of the
> FD)s
> > + Size = Top - FdTop;
> > + if (Size) {
> > + BuildResourceDescriptorHob (
> > + EFI_RESOURCE_SYSTEM_MEMORY,
> > + ResourceAttributes,
> > + FdTop,
> > + Size
> > + );
> > + };
> > + // Mark the memory covering the Firmware Device as boot services data
> > + BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
> > + FixedPcdGet32 (PcdFdSize),
> > + EfiBootServicesData);
> > + } else {
> > + BuildResourceDescriptorHob (
> > + EFI_RESOURCE_SYSTEM_MEMORY,
> > + ResourceAttributes,
> > + DramRegions[Index].BaseAddress,
> > + DramRegions[Index].Size
> > + );
> > + }
> > +
> > + if (FoundSystemMem) {
> > + continue;
> > + }
> > +
> > + BaseAddress = DramRegions[Index].BaseAddress;
> > + Size = DramRegions[Index].Size;
> > + Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
> > +
> > + if (FdBase >= BaseAddress && FdTop <= Top) {
> > + Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
> > + }
> > +
> > + if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
> > + FoundSystemMem = TRUE;
> > }
> > }
> >
> > + ASSERT (FoundSystemMem);
> > +
> > // Build Memory Allocation Hob
> > InitMmu (MemoryTable);
> >
> > diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> > new file mode 100644
> > index 000000000000..edbf0ceaf638
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> > @@ -0,0 +1,25 @@
> > +/** @file
> > +*
> > +* Copyright 2020 NXP
> > +*
> > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > +*
> > +**/
> > +
> > +#ifndef MEMORY_INIT_PEI_LIB_H_
> > +#define MEMORY_INIT_PEI_LIB_H_
> > +
> > +#include <Uefi.h>
> > +
> > +// Specifies the Maximum regions onto which DDR memory can be mapped in
> > +// a Platform
> > +#define MAX_DRAM_REGIONS 3
> > +#define SMC_DRAM_BANK_INFO (0xC200FF12)
> > +
> > +typedef struct {
> > + UINTN BaseAddress;
> > + UINTN Size;
> > +} DRAM_REGION_INFO;
> > +
> > +#endif // MEMORY_INIT_PEI_LIB_H_
> > +
> > diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> > index a5bd39415def..ad2371115b17 100644
> > --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> > +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> > @@ -18,7 +18,6 @@ [Defines]
> > [Sources]
> > MemoryInitPeiLib.c
> >
> > -
> > [Packages]
> > ArmPkg/ArmPkg.dec
> > ArmPlatformPkg/ArmPlatformPkg.dec
> > @@ -30,6 +29,7 @@ [Packages]
> > [LibraryClasses]
> > ArmMmuLib
> > ArmPlatformLib
> > + ArmSmcLib
> > DebugLib
> > HobLib
> > PcdLib
> > @@ -40,6 +40,11 @@ [Guids]
> > [FeaturePcd]
> > gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
> >
> > +[FixedPcd]
> > + gArmTokenSpaceGuid.PcdFdBaseAddress
> > + gArmTokenSpaceGuid.PcdFdSize
> > + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
> > +
> > [Pcd]
> > gArmTokenSpaceGuid.PcdSystemMemoryBase
> > gArmTokenSpaceGuid.PcdSystemMemorySize
> > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c
> b/Silicon/NXP/Library/SocLib/Chassis.c
> > index 847331a63152..1ef99e8de25f 100644
> > --- a/Silicon/NXP/Library/SocLib/Chassis.c
> > +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> > @@ -22,7 +22,6 @@
> > #include <Library/PrintLib.h>
> > #include <Library/SerialPortLib.h>
> >
> > -#include <DramInfo.h>
> > #include "NxpChassis.h"
> >
> > UINT32
> > @@ -75,69 +74,3 @@ SmmuInit (
> > MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> > }
> >
> > -UINTN
> > -GetDramSize (
> > - IN VOID
> > - )
> > -{
> > - ARM_SMC_ARGS ArmSmcArgs;
> > -
> > - ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> > - ArmSmcArgs.Arg1 = -1;
> > -
> > - ArmCallSmc (&ArmSmcArgs);
> > -
> > - if (ArmSmcArgs.Arg0) {
> > - return 0;
> > - } else {
> > - return ArmSmcArgs.Arg1;
> > - }
> > -}
> > -
> > -EFI_STATUS
> > -GetDramBankInfo (
> > - IN OUT DRAM_INFO *DramInfo
> > - )
> > -{
> > - ARM_SMC_ARGS ArmSmcArgs;
> > - UINT32 I;
> > - UINTN DramSize;
> > -
> > - DramSize = GetDramSize ();
> > - DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
> > -
> > - // Ensure DramSize has been set
> > - ASSERT (DramSize != 0);
> > -
> > - I = 0;
> > -
> > - do {
> > - ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> > - ArmSmcArgs.Arg1 = I;
> > -
> > - ArmCallSmc (&ArmSmcArgs);
> > - if (ArmSmcArgs.Arg0) {
> > - if (I > 0) {
> > - break;
> > - } else {
> > - ASSERT (ArmSmcArgs.Arg0 == 0);
> > - }
> > - }
> > -
> > - DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
> > - DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
> > -
> > - DramSize -= DramInfo->DramRegion[I].Size;
> > -
> > - DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
> > - I, DramInfo->DramRegion[I].BaseAddress, DramInfo-
> >DramRegion[I].Size));
> > -
> > - I++;
> > - } while (DramSize);
> > -
> > - DramInfo->NumOfDrams = I;
> > -
> > - DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo-
> >NumOfDrams));
> > -
> > - return EFI_SUCCESS;
> > -}
> > diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > index b7c7fc78cc8f..99d89498e0e2 100644
> > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > @@ -20,7 +20,6 @@ [Packages]
> > Silicon/NXP/NxpQoriqLs.dec
> >
> > [LibraryClasses]
> > - ArmSmcLib
> > BaseLib
> > DebugLib
> > IoAccessLib
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib
2020-04-06 10:08 ` Pankaj Bansal
@ 2020-04-06 11:48 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-06 11:48 UTC (permalink / raw)
To: Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
On Mon, Apr 06, 2020 at 10:08:43 +0000, Pankaj Bansal (OSS) wrote:
>
> > > +
> > > + FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
> > > + FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
> > > +
> > > + // Declare memory regios to system
> >
> > regions
>
> OK
>
> >
> > > + for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
> >
> > I guess what confuses me about this loop is the combination of:
> > - Iterating over the DRAM regions backwards (optimization?)
> > - Not terminating the iteration once all of the Fd region has been
> > covered (the opposite of optimization).
> >
> > Could something be done about that?
> >
>
> The DRAM region info is sorted based on the RAM address is SOC memory map.
> i.e. region0 is at lower address, as compared to region1.
> The goal to start from last region is to find the topmost RAM region that can contain UEFI DXE region i.e. PcdSystemMemoryUefiRegionSize.
> In the upcoming patches I would update the PcdSystemMemoryBase dynamically from that region.
> If UEFI were to allocate any reserved or runtime region, it would be allocated from topmost RAM region.
> This ensures that maximum amount of lower RAM (32 bit addresses) are left for OS to allocate to devices that can only
> work with 32bit physical addresses. E.g. legacy devices that need to DMA to 32bit addresses.
OK, that's (sadly) a good reason. Can it be explained in a comment?
/
Leif
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 16/28] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (14 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 12:46 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 17/28] Silicon/NXP: Use Clock retrieval PPI in modules Pankaj Bansal
` (13 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
The SOC takes primary clocking input from the external signal (a clock
generator on board). The input (frequency) is multiplied using multiple
phase locked loops (PLL) to create a variety of frequencies which can
then be passed to a variety of internal logic, including cores and
peripheral IP modules.
Therefore, move the clock retrieval APIs to Platform Lib.
The Input clock is retrieved from board components in Platform Lib, and
passed on to SOC Lib APIs to get the correct clock for an IP (after PLL
multiplication).
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../Library/ArmPlatformLib/ArmPlatformLib.c | 51 ++++++++++++++++++
Silicon/NXP/Include/Library/SocLib.h | 44 +++++++++++++++
Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 53 +++++++++++++++++++
Silicon/NXP/LS1043A/Include/Soc.h | 11 ++++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 52 ++++++++++++++++++
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 +
6 files changed, 212 insertions(+)
create mode 100644 Silicon/NXP/Include/Library/SocLib.h
create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 718c71bf02eb..7f5872a78cfc 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -12,10 +12,60 @@
**/
#include <Library/ArmPlatformLib.h>
+#include <Library/SocLib.h>
#include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/NxpPlatformGetClock.h>
extern VOID SocInit (VOID);
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] ... Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number.
+ if ClockType is NXP_CORE_CLOCK, then second argument
+ is interpreted as cluster number and third argument is
+ interpreted as core number (within the cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+ IN UINT32 ClockType,
+ ...
+ )
+{
+ UINT64 Clock;
+ VA_LIST Args;
+
+ Clock = 0;
+
+ VA_START (Args, ClockType);
+
+ switch (ClockType) {
+ case NXP_SYSTEM_CLOCK:
+ Clock = 100 * 1000 * 1000; // 100 MHz
+ break;
+ case NXP_I2C_CLOCK:
+ case NXP_UART_CLOCK:
+ Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
+ break;
+ default:
+ break;
+ }
+
+ VA_END (Args);
+
+ return Clock;
+}
+
/**
Return the current Boot Mode
@@ -69,6 +119,7 @@ PrePeiCoreGetMpCoreInfo (
}
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi = { NxpPlatformGetClock };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
new file mode 100644
index 000000000000..749aa230dec5
--- /dev/null
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -0,0 +1,44 @@
+/** @file
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SOC_LIB_H__
+#define SOC_LIB_H__
+
+#include <Uefi.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider
+ values to be applied to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is
+ to be applied.
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] Args Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN NXP_IP_CLOCK ClockType,
+ IN VA_LIST Args
+ );
+
+#endif // SOC_LIB_H__
diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
new file mode 100644
index 000000000000..6b553d36ce5b
--- /dev/null
+++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
@@ -0,0 +1,53 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_PLATFORM_PPI_H__
+#define NXP_PLATFORM_PPI_H__
+
+#include <Uefi.h>
+
+typedef enum _NXP_IP_CLOCK {
+ NXP_SYSTEM_CLOCK,
+ NXP_CORE_CLOCK,
+ NXP_UART_CLOCK,
+ NXP_I2C_CLOCK
+} NXP_IP_CLOCK;
+
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] ... Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+typedef
+UINT64
+(EFIAPI * NXP_PLATFORM_GET_CLOCK)(
+ IN NXP_IP_CLOCK ClockType,
+ ...
+ );
+
+typedef struct {
+ NXP_PLATFORM_GET_CLOCK PlatformGetClock;
+} NXP_PLATFORM_GET_CLOCK_PPI;
+
+extern NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi;
+
+#endif // NXP_PLATFORM_PPI_H__
+
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index 441871757d67..e62de570da8a 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -8,6 +8,8 @@
#ifndef SOC_H__
#define SOC_H__
+#include <Chassis2/NxpSoc.h>
+
/**
Soc Memory Map
**/
@@ -41,4 +43,13 @@
#define LS1043A_I2C_SIZE 0x10000
#define LS1043A_I2C_NUM_CONTROLLERS 4
+#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS
+
+/**
+ Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef CCSR_GUR LS1043A_DEVICE_CONFIG;
+
#endif // SOC_H__
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 98ca2e162f7b..480d8d18fb9f 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -18,6 +18,8 @@
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
+#include <Library/SocLib.h>
+#include <Soc.h>
/**
Calculate the frequency of various controllers and
@@ -50,6 +52,56 @@ GetSysInfo (
CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
}
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider
+ values to be applied to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is
+ to be applied.
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] Args Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN NXP_IP_CLOCK ClockType,
+ IN VA_LIST Args
+ )
+{
+ LS1043A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ case NXP_I2C_CLOCK:
+ RcwSr = GurRead ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
/**
Function to initialize SoC specific constructs
**/
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 99d89498e0e2..3d38a7e58b91 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -17,6 +17,7 @@ [Packages]
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec
[LibraryClasses]
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 16/28] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs
2020-03-20 14:35 ` [PATCH v2 16/28] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs Pankaj Bansal
@ 2020-04-01 12:46 ` Leif Lindholm
2020-04-06 10:15 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 12:46 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:31 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> The SOC takes primary clocking input from the external signal (a clock
> generator on board). The input (frequency) is multiplied using multiple
> phase locked loops (PLL) to create a variety of frequencies which can
> then be passed to a variety of internal logic, including cores and
> peripheral IP modules.
>
> Therefore, move the clock retrieval APIs to Platform Lib.
> The Input clock is retrieved from board components in Platform Lib, and
> passed on to SOC Lib APIs to get the correct clock for an IP (after PLL
> multiplication).
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../Library/ArmPlatformLib/ArmPlatformLib.c | 51 ++++++++++++++++++
> Silicon/NXP/Include/Library/SocLib.h | 44 +++++++++++++++
> Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 53 +++++++++++++++++++
> Silicon/NXP/LS1043A/Include/Soc.h | 11 ++++
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 52 ++++++++++++++++++
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 +
> 6 files changed, 212 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/SocLib.h
> create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index 718c71bf02eb..7f5872a78cfc 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -12,10 +12,60 @@
> **/
>
> #include <Library/ArmPlatformLib.h>
> +#include <Library/SocLib.h>
> #include <Ppi/ArmMpCoreInfo.h>
> +#include <Ppi/NxpPlatformGetClock.h>
>
> extern VOID SocInit (VOID);
>
> +/**
> + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
> +
> + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
> + is to be retrieved.
> + @param[in] ... Variable argument list which is parsed based on
> + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> + the second argument will be interpreted as controller
> + number.
> + if ClockType is NXP_CORE_CLOCK, then second argument
> + is interpreted as cluster number and third argument is
> + interpreted as core number (within the cluster)
> +
> + @return Actual Clock Frequency. Return value 0 should be
> + interpreted as clock not being provided to IP.
> +**/
> +UINT64
> +EFIAPI
> +NxpPlatformGetClock(
> + IN UINT32 ClockType,
> + ...
> + )
> +{
> + UINT64 Clock;
> + VA_LIST Args;
> +
> + Clock = 0;
> +
> + VA_START (Args, ClockType);
> +
> + switch (ClockType) {
> + case NXP_SYSTEM_CLOCK:
> + Clock = 100 * 1000 * 1000; // 100 MHz
> + break;
> + case NXP_I2C_CLOCK:
> + case NXP_UART_CLOCK:
> + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> + Clock = SocGetClock (Clock, ClockType, Args);
> + break;
> + default:
> + break;
> + }
> +
> + VA_END (Args);
> +
> + return Clock;
> +}
> +
> /**
> Return the current Boot Mode
>
> @@ -69,6 +119,7 @@ PrePeiCoreGetMpCoreInfo (
> }
>
> ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi = { NxpPlatformGetClock };
>
> EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> {
> diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
> new file mode 100644
> index 000000000000..749aa230dec5
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/SocLib.h
> @@ -0,0 +1,44 @@
> +/** @file
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef SOC_LIB_H__
> +#define SOC_LIB_H__
> +
> +#include <Uefi.h>
> +#include <Ppi/NxpPlatformGetClock.h>
> +
> +/**
> + Return the input clock frequency to an IP Module.
> + This function reads the RCW bits and calculates the PLL multipler/divider
> + values to be applied to various IP modules.
> + If a module is disabled or doesn't exist on platform, then return zero.
> +
> + @param[in] BaseClock Base clock to which PLL multipler/divider values is
> + to be applied.
> + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
> + is to be retrieved.
> + @param[in] Args Variable argument list which is parsed based on
> + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> + the second argument will be interpreted as controller
> + number. e.g. if there are four i2c controllers in SOC,
> + then this value can be 0, 1, 2, 3
> + e.g. if ClockType is NXP_CORE_CLOCK, then second
> + argument is interpreted as cluster number and third
> + argument is interpreted as core number (within the
> + cluster)
> +
> + @return Actual Clock Frequency. Return value 0 should be
> + interpreted as clock not being provided to IP.
> +**/
> +UINT64
> +SocGetClock (
> + IN UINT64 BaseClock,
> + IN NXP_IP_CLOCK ClockType,
> + IN VA_LIST Args
> + );
> +
> +#endif // SOC_LIB_H__
> diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> new file mode 100644
> index 000000000000..6b553d36ce5b
> --- /dev/null
> +++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> @@ -0,0 +1,53 @@
> +/** @file
> +*
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef NXP_PLATFORM_PPI_H__
> +#define NXP_PLATFORM_PPI_H__
> +
> +#include <Uefi.h>
> +
> +typedef enum _NXP_IP_CLOCK {
> + NXP_SYSTEM_CLOCK,
> + NXP_CORE_CLOCK,
> + NXP_UART_CLOCK,
> + NXP_I2C_CLOCK
Will this enum be used by standalone drivers/applications?
If not, could the members be sorted alphabetically?
/
Leif
> +} NXP_IP_CLOCK;
> +
> +/**
> + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
> +
> + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
> + is to be retrieved.
> + @param[in] ... Variable argument list which is parsed based on
> + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> + the second argument will be interpreted as controller
> + number. e.g. if there are four i2c controllers in SOC,
> + then this value can be 0, 1, 2, 3
> + e.g. if ClockType is NXP_CORE_CLOCK, then second
> + argument is interpreted as cluster number and third
> + argument is interpreted as core number (within the
> + cluster)
> +
> + @return Actual Clock Frequency. Return value 0 should be
> + interpreted as clock not being provided to IP.
> +**/
> +typedef
> +UINT64
> +(EFIAPI * NXP_PLATFORM_GET_CLOCK)(
> + IN NXP_IP_CLOCK ClockType,
> + ...
> + );
> +
> +typedef struct {
> + NXP_PLATFORM_GET_CLOCK PlatformGetClock;
> +} NXP_PLATFORM_GET_CLOCK_PPI;
> +
> +extern NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi;
> +
> +#endif // NXP_PLATFORM_PPI_H__
> +
> diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
> index 441871757d67..e62de570da8a 100644
> --- a/Silicon/NXP/LS1043A/Include/Soc.h
> +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> @@ -8,6 +8,8 @@
> #ifndef SOC_H__
> #define SOC_H__
>
> +#include <Chassis2/NxpSoc.h>
> +
> /**
> Soc Memory Map
> **/
> @@ -41,4 +43,13 @@
> #define LS1043A_I2C_SIZE 0x10000
> #define LS1043A_I2C_NUM_CONTROLLERS 4
>
> +#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS
> +
> +/**
> + Reset Control Word (RCW) Bits
> +**/
> +#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
> +
> +typedef CCSR_GUR LS1043A_DEVICE_CONFIG;
> +
> #endif // SOC_H__
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index 98ca2e162f7b..480d8d18fb9f 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -18,6 +18,8 @@
> #include <Library/PcdLib.h>
> #include <Library/PrintLib.h>
> #include <Library/SerialPortLib.h>
> +#include <Library/SocLib.h>
> +#include <Soc.h>
>
> /**
> Calculate the frequency of various controllers and
> @@ -50,6 +52,56 @@ GetSysInfo (
> CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> }
>
> +/**
> + Return the input clock frequency to an IP Module.
> + This function reads the RCW bits and calculates the PLL multipler/divider
> + values to be applied to various IP modules.
> + If a module is disabled or doesn't exist on platform, then return zero.
> +
> + @param[in] BaseClock Base clock to which PLL multipler/divider values is
> + to be applied.
> + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
> + is to be retrieved.
> + @param[in] Args Variable argument list which is parsed based on
> + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> + the second argument will be interpreted as controller
> + number. e.g. if there are four i2c controllers in SOC,
> + then this value can be 0, 1, 2, 3
> + e.g. if ClockType is NXP_CORE_CLOCK, then second
> + argument is interpreted as cluster number and third
> + argument is interpreted as core number (within the
> + cluster)
> +
> + @return Actual Clock Frequency. Return value 0 should be
> + interpreted as clock not being provided to IP.
> +**/
> +UINT64
> +SocGetClock (
> + IN UINT64 BaseClock,
> + IN NXP_IP_CLOCK ClockType,
> + IN VA_LIST Args
> + )
> +{
> + LS1043A_DEVICE_CONFIG *Dcfg;
> + UINT32 RcwSr;
> + UINT64 ReturnValue;
> +
> + ReturnValue = 0;
> + Dcfg = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS;
> +
> + switch (ClockType) {
> + case NXP_UART_CLOCK:
> + case NXP_I2C_CLOCK:
> + RcwSr = GurRead ((UINTN)&Dcfg->RcwSr[0]);
> + ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
> + break;
> + default:
> + break;
> + }
> +
> + return ReturnValue;
> +}
> +
> /**
> Function to initialize SoC specific constructs
> **/
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index 99d89498e0e2..3d38a7e58b91 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -17,6 +17,7 @@ [Packages]
> ArmPkg/ArmPkg.dec
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> + Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 16/28] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs
2020-04-01 12:46 ` Leif Lindholm
@ 2020-04-06 10:15 ` Pankaj Bansal
0 siblings, 0 replies; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-06 10:15 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Wednesday, April 1, 2020 6:17 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 16/28] Platform/NXP/LS1043aRdbPkg: Add Clock
> retrieval APIs
>
> On Fri, Mar 20, 2020 at 20:05:31 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > The SOC takes primary clocking input from the external signal (a clock
> > generator on board). The input (frequency) is multiplied using multiple
> > phase locked loops (PLL) to create a variety of frequencies which can
> > then be passed to a variety of internal logic, including cores and
> > peripheral IP modules.
> >
> > Therefore, move the clock retrieval APIs to Platform Lib.
> > The Input clock is retrieved from board components in Platform Lib, and
> > passed on to SOC Lib APIs to get the correct clock for an IP (after PLL
> > multiplication).
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > .../Library/ArmPlatformLib/ArmPlatformLib.c | 51 ++++++++++++++++++
> > Silicon/NXP/Include/Library/SocLib.h | 44 +++++++++++++++
> > Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 53 +++++++++++++++++++
> > Silicon/NXP/LS1043A/Include/Soc.h | 11 ++++
> > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 52 ++++++++++++++++++
> > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 +
> > 6 files changed, 212 insertions(+)
> > create mode 100644 Silicon/NXP/Include/Library/SocLib.h
> > create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> >
> > diff --git
> a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > index 718c71bf02eb..7f5872a78cfc 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > +++
> b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > @@ -12,10 +12,60 @@
> > **/
> >
> > #include <Library/ArmPlatformLib.h>
> > +#include <Library/SocLib.h>
> > #include <Ppi/ArmMpCoreInfo.h>
> > +#include <Ppi/NxpPlatformGetClock.h>
> >
> > extern VOID SocInit (VOID);
> >
> > +/**
> > + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
> > +
> > + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP
> clock
> > + is to be retrieved.
> > + @param[in] ... Variable argument list which is parsed based on
> > + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> > + the second argument will be interpreted as controller
> > + number.
> > + if ClockType is NXP_CORE_CLOCK, then second argument
> > + is interpreted as cluster number and third argument is
> > + interpreted as core number (within the cluster)
> > +
> > + @return Actual Clock Frequency. Return value 0 should be
> > + interpreted as clock not being provided to IP.
> > +**/
> > +UINT64
> > +EFIAPI
> > +NxpPlatformGetClock(
> > + IN UINT32 ClockType,
> > + ...
> > + )
> > +{
> > + UINT64 Clock;
> > + VA_LIST Args;
> > +
> > + Clock = 0;
> > +
> > + VA_START (Args, ClockType);
> > +
> > + switch (ClockType) {
> > + case NXP_SYSTEM_CLOCK:
> > + Clock = 100 * 1000 * 1000; // 100 MHz
> > + break;
> > + case NXP_I2C_CLOCK:
> > + case NXP_UART_CLOCK:
> > + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> > + Clock = SocGetClock (Clock, ClockType, Args);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + VA_END (Args);
> > +
> > + return Clock;
> > +}
> > +
> > /**
> > Return the current Boot Mode
> >
> > @@ -69,6 +119,7 @@ PrePeiCoreGetMpCoreInfo (
> > }
> >
> > ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> > +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi =
> { NxpPlatformGetClock };
> >
> > EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> > {
> > diff --git a/Silicon/NXP/Include/Library/SocLib.h
> b/Silicon/NXP/Include/Library/SocLib.h
> > new file mode 100644
> > index 000000000000..749aa230dec5
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Library/SocLib.h
> > @@ -0,0 +1,44 @@
> > +/** @file
> > +
> > + Copyright 2020 NXP
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef SOC_LIB_H__
> > +#define SOC_LIB_H__
> > +
> > +#include <Uefi.h>
> > +#include <Ppi/NxpPlatformGetClock.h>
> > +
> > +/**
> > + Return the input clock frequency to an IP Module.
> > + This function reads the RCW bits and calculates the PLL multipler/divider
> > + values to be applied to various IP modules.
> > + If a module is disabled or doesn't exist on platform, then return zero.
> > +
> > + @param[in] BaseClock Base clock to which PLL multipler/divider values is
> > + to be applied.
> > + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP
> clock
> > + is to be retrieved.
> > + @param[in] Args Variable argument list which is parsed based on
> > + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> > + the second argument will be interpreted as controller
> > + number. e.g. if there are four i2c controllers in SOC,
> > + then this value can be 0, 1, 2, 3
> > + e.g. if ClockType is NXP_CORE_CLOCK, then second
> > + argument is interpreted as cluster number and third
> > + argument is interpreted as core number (within the
> > + cluster)
> > +
> > + @return Actual Clock Frequency. Return value 0 should be
> > + interpreted as clock not being provided to IP.
> > +**/
> > +UINT64
> > +SocGetClock (
> > + IN UINT64 BaseClock,
> > + IN NXP_IP_CLOCK ClockType,
> > + IN VA_LIST Args
> > + );
> > +
> > +#endif // SOC_LIB_H__
> > diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> > new file mode 100644
> > index 000000000000..6b553d36ce5b
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> > @@ -0,0 +1,53 @@
> > +/** @file
> > +*
> > +* Copyright 2020 NXP
> > +*
> > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > +*
> > +**/
> > +
> > +#ifndef NXP_PLATFORM_PPI_H__
> > +#define NXP_PLATFORM_PPI_H__
> > +
> > +#include <Uefi.h>
> > +
> > +typedef enum _NXP_IP_CLOCK {
> > + NXP_SYSTEM_CLOCK,
> > + NXP_CORE_CLOCK,
> > + NXP_UART_CLOCK,
> > + NXP_I2C_CLOCK
>
> Will this enum be used by standalone drivers/applications?
> If not, could the members be sorted alphabetically?
>
ok
> /
> Leif
>
> > +} NXP_IP_CLOCK;
> > +
> > +/**
> > + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
> > +
> > + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP
> clock
> > + is to be retrieved.
> > + @param[in] ... Variable argument list which is parsed based on
> > + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> > + the second argument will be interpreted as controller
> > + number. e.g. if there are four i2c controllers in SOC,
> > + then this value can be 0, 1, 2, 3
> > + e.g. if ClockType is NXP_CORE_CLOCK, then second
> > + argument is interpreted as cluster number and third
> > + argument is interpreted as core number (within the
> > + cluster)
> > +
> > + @return Actual Clock Frequency. Return value 0 should be
> > + interpreted as clock not being provided to IP.
> > +**/
> > +typedef
> > +UINT64
> > +(EFIAPI * NXP_PLATFORM_GET_CLOCK)(
> > + IN NXP_IP_CLOCK ClockType,
> > + ...
> > + );
> > +
> > +typedef struct {
> > + NXP_PLATFORM_GET_CLOCK PlatformGetClock;
> > +} NXP_PLATFORM_GET_CLOCK_PPI;
> > +
> > +extern NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi;
> > +
> > +#endif // NXP_PLATFORM_PPI_H__
> > +
> > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> b/Silicon/NXP/LS1043A/Include/Soc.h
> > index 441871757d67..e62de570da8a 100644
> > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> > @@ -8,6 +8,8 @@
> > #ifndef SOC_H__
> > #define SOC_H__
> >
> > +#include <Chassis2/NxpSoc.h>
> > +
> > /**
> > Soc Memory Map
> > **/
> > @@ -41,4 +43,13 @@
> > #define LS1043A_I2C_SIZE 0x10000
> > #define LS1043A_I2C_NUM_CONTROLLERS 4
> >
> > +#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS
> > +
> > +/**
> > + Reset Control Word (RCW) Bits
> > +**/
> > +#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
> > +
> > +typedef CCSR_GUR LS1043A_DEVICE_CONFIG;
> > +
> > #endif // SOC_H__
> > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > index 98ca2e162f7b..480d8d18fb9f 100644
> > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > @@ -18,6 +18,8 @@
> > #include <Library/PcdLib.h>
> > #include <Library/PrintLib.h>
> > #include <Library/SerialPortLib.h>
> > +#include <Library/SocLib.h>
> > +#include <Soc.h>
> >
> > /**
> > Calculate the frequency of various controllers and
> > @@ -50,6 +52,56 @@ GetSysInfo (
> > CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > }
> >
> > +/**
> > + Return the input clock frequency to an IP Module.
> > + This function reads the RCW bits and calculates the PLL multipler/divider
> > + values to be applied to various IP modules.
> > + If a module is disabled or doesn't exist on platform, then return zero.
> > +
> > + @param[in] BaseClock Base clock to which PLL multipler/divider values is
> > + to be applied.
> > + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP
> clock
> > + is to be retrieved.
> > + @param[in] Args Variable argument list which is parsed based on
> > + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
> > + the second argument will be interpreted as controller
> > + number. e.g. if there are four i2c controllers in SOC,
> > + then this value can be 0, 1, 2, 3
> > + e.g. if ClockType is NXP_CORE_CLOCK, then second
> > + argument is interpreted as cluster number and third
> > + argument is interpreted as core number (within the
> > + cluster)
> > +
> > + @return Actual Clock Frequency. Return value 0 should be
> > + interpreted as clock not being provided to IP.
> > +**/
> > +UINT64
> > +SocGetClock (
> > + IN UINT64 BaseClock,
> > + IN NXP_IP_CLOCK ClockType,
> > + IN VA_LIST Args
> > + )
> > +{
> > + LS1043A_DEVICE_CONFIG *Dcfg;
> > + UINT32 RcwSr;
> > + UINT64 ReturnValue;
> > +
> > + ReturnValue = 0;
> > + Dcfg = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS;
> > +
> > + switch (ClockType) {
> > + case NXP_UART_CLOCK:
> > + case NXP_I2C_CLOCK:
> > + RcwSr = GurRead ((UINTN)&Dcfg->RcwSr[0]);
> > + ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + return ReturnValue;
> > +}
> > +
> > /**
> > Function to initialize SoC specific constructs
> > **/
> > diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > index 99d89498e0e2..3d38a7e58b91 100644
> > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > @@ -17,6 +17,7 @@ [Packages]
> > ArmPkg/ArmPkg.dec
> > MdeModulePkg/MdeModulePkg.dec
> > MdePkg/MdePkg.dec
> > + Silicon/NXP/LS1043A/LS1043A.dec
> > Silicon/NXP/NxpQoriqLs.dec
> >
> > [LibraryClasses]
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 17/28] Silicon/NXP: Use Clock retrieval PPI in modules
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (15 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 16/28] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 12:47 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package Pankaj Bansal
` (12 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Use NXP_PLATFORM_GET_CLOCK_PPI in various Layerscape IP modules.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 --
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 3 +-
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 6 ----
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 2 +-
Silicon/NXP/Include/Chassis2/NxpSoc.h | 9 ------
.../SerialUartClockLib/SerialUartClockLib.c | 9 ++----
.../SerialUartClockLib/SerialUartClockLib.inf | 2 +-
Silicon/NXP/Library/SocLib/Chassis.c | 15 ---------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 31 -------------------
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
Silicon/NXP/NxpQoriqLs.dec | 5 ---
11 files changed, 6 insertions(+), 79 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index e5383aaf0cc5..d486c9b36fab 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -39,8 +39,6 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
-
#
# RTC Pcds
#
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index a5aba47b3ed4..30804450d2b7 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -17,6 +17,7 @@
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeLib.h>
+#include <Ppi/NxpPlatformGetClock.h>
#include "I2cDxe.h"
@@ -51,7 +52,7 @@ SetBusFrequency (
I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
- I2cClock = GetBusFrequency ();
+ I2cClock = gPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);
I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
index 88316f313380..7c4a306c16a0 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -37,12 +37,6 @@ typedef struct {
NON_DISCOVERABLE_DEVICE *Dev;
} NXP_I2C_MASTER;
-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
EFI_STATUS
NxpI2cInit (
IN EFI_HANDLE DriverBindingHandle,
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 867376044656..3bf7a8124fc6 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -25,13 +25,13 @@ [Sources.common]
[LibraryClasses]
ArmLib
+ ArmPlatformLib
BaseMemoryLib
DevicePathLib
I2cLib
IoLib
MemoryAllocationLib
PcdLib
- SocLib
TimerLib
UefiBootServicesTableLib
UefiDriverEntryPoint
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index 6812beafe447..3f00a2614131 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -27,10 +27,6 @@
#define SACR_PAGESIZE_MASK 0x00010000
#define IDR1_PAGESIZE_MASK 0x80000000
-typedef struct {
- UINTN FreqSystemBus;
-} SYS_INFO;
-
/* Device Configuration and Pin Control */
typedef struct {
UINT8 Res0[0x100-0x00];
@@ -39,11 +35,6 @@ typedef struct {
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
} CCSR_GUR;
-VOID
-GetSysInfo (
- OUT SYS_INFO *
- );
-
UINT32
EFIAPI
GurRead (
diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
index 9d49d7b4748b..eb29cf0373cc 100644
--- a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
+++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
@@ -7,12 +7,7 @@
**/
#include <Base.h>
-
-extern
-UINT64
-GetBusFrequency (
- VOID
- );
+#include <Ppi/NxpPlatformGetClock.h>
/**
Return clock in for Uart IP
@@ -23,5 +18,5 @@ BaseSerialPortGetClock (
VOID
)
{
- return GetBusFrequency ();
+ return gPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);
}
diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
index 9a3e80cf521d..c8840281763b 100644
--- a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
+++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
@@ -22,5 +22,5 @@ [Sources.common]
SerialUartClockLib.c
[LibraryClasses]
- SocLib
+ ArmPlatformLib
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 1ef99e8de25f..90677f0f36ca 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -37,21 +37,6 @@ GurRead (
}
}
-/*
- * Return system bus frequency
- */
-UINT64
-GetBusFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSystemBus;
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 480d8d18fb9f..b14ada7f595d 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -21,37 +21,6 @@
#include <Library/SocLib.h>
#include <Soc.h>
-/**
- Calculate the frequency of various controllers and
- populate the passed structure with frequuencies.
-
- @param PtrSysInfo Input structure to populate with
- frequencies.
-**/
-VOID
-GetSysInfo (
- OUT SYS_INFO *PtrSysInfo
- )
-{
- CCSR_GUR *GurBase;
- UINTN SysClk;
-
- GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
- SysClk = CLK_FREQ;
-
- SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
-
- PtrSysInfo->FreqSystemBus = SysClk;
-
- //
- // selects the platform clock:SYSCLK ratio and calculate
- // system frequency
- //
- PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-}
-
/**
Return the input clock frequency to an IP Module.
This function reads the RCW bits and calculates the PLL multipler/divider
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 3d38a7e58b91..bb15e0a3d710 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -36,4 +36,3 @@ [BuildOptions]
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index b478560450b3..2ac047a89274 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,11 +22,6 @@ [Guids.common]
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
[PcdsFixedAtBuild.common]
- #
- # Platform PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
-
#
# Pcds to support Big Endian IPs
#
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 17/28] Silicon/NXP: Use Clock retrieval PPI in modules
2020-03-20 14:35 ` [PATCH v2 17/28] Silicon/NXP: Use Clock retrieval PPI in modules Pankaj Bansal
@ 2020-04-01 12:47 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 12:47 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:32 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Use NXP_PLATFORM_GET_CLOCK_PPI in various Layerscape IP modules.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 --
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 3 +-
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 6 ----
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 2 +-
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 9 ------
> .../SerialUartClockLib/SerialUartClockLib.c | 9 ++----
> .../SerialUartClockLib/SerialUartClockLib.inf | 2 +-
> Silicon/NXP/Library/SocLib/Chassis.c | 15 ---------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 31 -------------------
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
> Silicon/NXP/NxpQoriqLs.dec | 5 ---
> 11 files changed, 6 insertions(+), 79 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index e5383aaf0cc5..d486c9b36fab 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -39,8 +39,6 @@ [PcdsFixedAtBuild.common]
> gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
> gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
>
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> -
> #
> # RTC Pcds
> #
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> index a5aba47b3ed4..30804450d2b7 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> @@ -17,6 +17,7 @@
> #include <Library/UefiBootServicesTableLib.h>
> #include <Library/UefiLib.h>
> #include <Library/UefiRuntimeLib.h>
> +#include <Ppi/NxpPlatformGetClock.h>
>
> #include "I2cDxe.h"
>
> @@ -51,7 +52,7 @@ SetBusFrequency (
>
> I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
>
> - I2cClock = GetBusFrequency ();
> + I2cClock = gPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);
>
> I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
>
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> index 88316f313380..7c4a306c16a0 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> @@ -37,12 +37,6 @@ typedef struct {
> NON_DISCOVERABLE_DEVICE *Dev;
> } NXP_I2C_MASTER;
>
> -extern
> -UINT64
> -GetBusFrequency (
> - VOID
> - );
> -
> EFI_STATUS
> NxpI2cInit (
> IN EFI_HANDLE DriverBindingHandle,
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> index 867376044656..3bf7a8124fc6 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -25,13 +25,13 @@ [Sources.common]
>
> [LibraryClasses]
> ArmLib
> + ArmPlatformLib
> BaseMemoryLib
> DevicePathLib
> I2cLib
> IoLib
> MemoryAllocationLib
> PcdLib
> - SocLib
> TimerLib
> UefiBootServicesTableLib
> UefiDriverEntryPoint
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> index 6812beafe447..3f00a2614131 100644
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> @@ -27,10 +27,6 @@
> #define SACR_PAGESIZE_MASK 0x00010000
> #define IDR1_PAGESIZE_MASK 0x80000000
>
> -typedef struct {
> - UINTN FreqSystemBus;
> -} SYS_INFO;
> -
> /* Device Configuration and Pin Control */
> typedef struct {
> UINT8 Res0[0x100-0x00];
> @@ -39,11 +35,6 @@ typedef struct {
> #define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> } CCSR_GUR;
>
> -VOID
> -GetSysInfo (
> - OUT SYS_INFO *
> - );
> -
> UINT32
> EFIAPI
> GurRead (
> diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> index 9d49d7b4748b..eb29cf0373cc 100644
> --- a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> +++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> @@ -7,12 +7,7 @@
> **/
>
> #include <Base.h>
> -
> -extern
> -UINT64
> -GetBusFrequency (
> - VOID
> - );
> +#include <Ppi/NxpPlatformGetClock.h>
>
> /**
> Return clock in for Uart IP
> @@ -23,5 +18,5 @@ BaseSerialPortGetClock (
> VOID
> )
> {
> - return GetBusFrequency ();
> + return gPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);
> }
> diff --git a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> index 9a3e80cf521d..c8840281763b 100644
> --- a/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> +++ b/Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> @@ -22,5 +22,5 @@ [Sources.common]
> SerialUartClockLib.c
>
> [LibraryClasses]
> - SocLib
> + ArmPlatformLib
>
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index 1ef99e8de25f..90677f0f36ca 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -37,21 +37,6 @@ GurRead (
> }
> }
>
> -/*
> - * Return system bus frequency
> - */
> -UINT64
> -GetBusFrequency (
> - VOID
> - )
> -{
> - SYS_INFO SocSysInfo;
> -
> - GetSysInfo (&SocSysInfo);
> -
> - return SocSysInfo.FreqSystemBus;
> -}
> -
> /*
> * Setup SMMU in bypass mode
> * and also set its pagesize
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index 480d8d18fb9f..b14ada7f595d 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -21,37 +21,6 @@
> #include <Library/SocLib.h>
> #include <Soc.h>
>
> -/**
> - Calculate the frequency of various controllers and
> - populate the passed structure with frequuencies.
> -
> - @param PtrSysInfo Input structure to populate with
> - frequencies.
> -**/
> -VOID
> -GetSysInfo (
> - OUT SYS_INFO *PtrSysInfo
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN SysClk;
> -
> - GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> - SysClk = CLK_FREQ;
> -
> - SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> -
> - PtrSysInfo->FreqSystemBus = SysClk;
> -
> - //
> - // selects the platform clock:SYSCLK ratio and calculate
> - // system frequency
> - //
> - PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> - CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> - CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> -}
> -
> /**
> Return the input clock frequency to an IP Module.
> This function reads the RCW bits and calculates the PLL multipler/divider
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index 3d38a7e58b91..bb15e0a3d710 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -36,4 +36,3 @@ [BuildOptions]
> [FixedPcd]
> gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index b478560450b3..2ac047a89274 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -22,11 +22,6 @@ [Guids.common]
> gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
>
> [PcdsFixedAtBuild.common]
> - #
> - # Platform PCDs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> -
> #
> # Pcds to support Big Endian IPs
> #
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (16 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 17/28] Silicon/NXP: Use Clock retrieval PPI in modules Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 14:17 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 19/28] Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg Pankaj Bansal
` (11 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
A Chassis is a base framework used for building SoCs.
We can think of Chassis/Soc/Platform(a.k.a Borad) in Oops terms.
Chassis is base. Soc is based on some Chassis.
Platform is based on some Soc.
SOCs that are designed around same chassis, reuse most of the components.
Therefore, add the package for Chassis2. LS1043A and LS1046A SOCs belong
to Chassis2.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Chassis2/Chassis2.dec | 23 +++++
Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 ++
Silicon/NXP/Chassis2/Include/Chassis.h | 34 +++++++
.../Chassis2/Library/ChassisLib/ChassisLib.c | 97 +++++++++++++++++++
.../Library/ChassisLib/ChassisLib.inf | 34 +++++++
Silicon/NXP/Include/Library/ChassisLib.h | 51 ++++++++++
Silicon/NXP/NxpQoriqLs.dec | 4 +
7 files changed, 253 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h
diff --git a/Silicon/NXP/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis2/Chassis2.dec
new file mode 100644
index 000000000000..a0048bd784ea
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dec
@@ -0,0 +1,23 @@
+# @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
new file mode 100644
index 000000000000..db8e5a92eacb
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
@@ -0,0 +1,10 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
new file mode 100644
index 000000000000..72bd97efd004
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -0,0 +1,34 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef CHASSIS_H__
+#define CHASSIS_H__
+
+#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x09000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+
+/**
+ The Device Configuration Unit provides general purpose configuration and
+ status for the device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+ UINT8 Reserved0[0x100 - 0x0];
+ UINT32 RcwSr[16]; // Reset Control Word Status Register
+} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index 000000000000..816e0fa29c4a
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,97 @@
+/** @file
+ Chassis specific functions common to all SOCs based on a specific Chessis
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Chassis.h>
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+/**
+ Read Dcfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+/**
+ Write Dcfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioWrite32 (Address, Value);
+ } else {
+ return MmioWrite32 (Address, Value);
+ }
+}
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+STATIC
+VOID
+SmmuInit (
+ VOID
+ )
+{
+ UINT32 Value;
+
+ /* set pagesize as 64K and ssmu-500 in bypass mode */
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+ MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK);
+ Value &= ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK);
+ Value &= ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ )
+{
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortInitialize ();
+
+ SmmuInit ();
+}
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index 000000000000..2bb16af53134
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,34 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+#
+
+[Defines]
+ INF_VERSION = 1.27
+ BASE_NAME = Chassis2Lib
+ FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ChassisLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ IoAccessLib
+ IoLib
+ PcdLib
+ SerialPortLib
+
+[Sources.common]
+ ChassisLib.c
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
new file mode 100644
index 000000000000..89992a4b6fd5
--- /dev/null
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -0,0 +1,51 @@
+/** @file
+ Chassis Lib to provide Chessis specific functionality to all SOCs in
+ a Chassis.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef CHASSIS_LIB_H__
+#define CHASSIS_LIB_H__
+
+#include <Chassis.h>
+
+/**
+ Read Dcfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Write Dcfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ );
+
+#endif // CHASSIS_LIB_H__
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 2ac047a89274..3e79f502c127 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -14,6 +14,9 @@ [Includes]
Include
[LibraryClasses]
+ ## @libraryclass Provides Chassis specific functions to other modules
+ ChassisLib|Include/Library/ChassisLib.h
+
## @libraryclass Provides services to read/write to I2c devices
I2cLib|Include/Library/I2cLib.h
@@ -29,4 +32,5 @@ [PcdsFixedAtBuild.common]
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package
2020-03-20 14:35 ` [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package Pankaj Bansal
@ 2020-04-01 14:17 ` Leif Lindholm
2020-04-06 11:07 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 14:17 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:33 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> A Chassis is a base framework used for building SoCs.
> We can think of Chassis/Soc/Platform(a.k.a Borad) in Oops terms.
Board?
"Oops" is not a term I am familiar with other than as an exclamation -
can you elaborate please?
> Chassis is base. Soc is based on some Chassis.
> Platform is based on some Soc.
>
> SOCs that are designed around same chassis, reuse most of the components.
>
> Therefore, add the package for Chassis2. LS1043A and LS1046A SOCs belong
> to Chassis2.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/Chassis2/Chassis2.dec | 23 +++++
> Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 ++
> Silicon/NXP/Chassis2/Include/Chassis.h | 34 +++++++
> .../Chassis2/Library/ChassisLib/ChassisLib.c | 97 +++++++++++++++++++
> .../Library/ChassisLib/ChassisLib.inf | 34 +++++++
> Silicon/NXP/Include/Library/ChassisLib.h | 51 ++++++++++
> Silicon/NXP/NxpQoriqLs.dec | 4 +
> 7 files changed, 253 insertions(+)
> create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
> create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
> create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h
>
> diff --git a/Silicon/NXP/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis2/Chassis2.dec
> new file mode 100644
> index 000000000000..a0048bd784ea
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Chassis2.dec
> @@ -0,0 +1,23 @@
> +# @file
> +# NXP Layerscape processor package.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 1.27
> + PACKAGE_VERSION = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> +
> diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
> new file mode 100644
> index 000000000000..db8e5a92eacb
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
> @@ -0,0 +1,10 @@
> +# @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[LibraryClasses.common]
> + ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
> new file mode 100644
> index 000000000000..72bd97efd004
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> @@ -0,0 +1,34 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef CHASSIS_H__
> +#define CHASSIS_H__
> +
> +#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
> +
> +/* SMMU Defintions */
> +#define SMMU_BASE_ADDR 0x09000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +
> +#define SCR0_USFCFG_MASK 0x00000400
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SACR_PAGESIZE_MASK 0x00010000
> +
> +/**
> + The Device Configuration Unit provides general purpose configuration and
> + status for the device. These registers only support 32-bit accesses.
> +**/
> +#pragma pack(1)
> +typedef struct {
> + UINT8 Reserved0[0x100 - 0x0];
> + UINT32 RcwSr[16]; // Reset Control Word Status Register
If this is the formal word as used in official documentation, it still
needs listing in a glossary in the file comment header.
> +} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
> +#pragma pack()
> +
> +#endif // CHASSIS_H__
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> new file mode 100644
> index 000000000000..816e0fa29c4a
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> @@ -0,0 +1,97 @@
> +/** @file
> + Chassis specific functions common to all SOCs based on a specific Chessis
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Chassis.h>
> +#include <Uefi.h>
> +#include <Library/IoLib.h>
> +#include <Library/IoAccessLib.h>
Can you flip the two above lines around to get them in order?
> +#include <Library/PcdLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +/**
> + Read Dcfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +DcfgRead32 (
> + IN UINTN Address
> + )
> +{
Please replace these with the GetMmioOperations call, as designed.
In fact, please provide an additional patch deleting all of the direct
SwapMmio* functions from IoAccessLib.h and changing all of the
SwapMmio* function definitions in IoAccessLib.c to STATIC to prevent
future accidental direct use.
/
Leif
> + if (FeaturePcdGet (PcdDcfgBigEndian)) {
> + return SwapMmioRead32 (Address);
> + } else {
> + return MmioRead32 (Address);
> + }
> +}
> +
> +/**
> + Write Dcfg register
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +**/
> +UINT32
> +EFIAPI
> +DcfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + if (FeaturePcdGet (PcdDcfgBigEndian)) {
> + return SwapMmioWrite32 (Address, Value);
> + } else {
> + return MmioWrite32 (Address, Value);
> + }
> +}
> +
> +/*
> + * Setup SMMU in bypass mode
> + * and also set its pagesize
> + */
> +STATIC
> +VOID
> +SmmuInit (
> + VOID
> + )
> +{
> + UINT32 Value;
> +
> + /* set pagesize as 64K and ssmu-500 in bypass mode */
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK);
> + Value &= ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK);
> + Value &= ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> +}
> +
> +/**
> + Function to initialize Chassis Specific functions
> + **/
> +VOID
> +ChassisInit (
> + VOID
> + )
> +{
> + //
> + // Early init serial Port to get board information.
> + //
> + SerialPortInitialize ();
> +
> + SmmuInit ();
> +}
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> new file mode 100644
> index 000000000000..2bb16af53134
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> @@ -0,0 +1,34 @@
> +# @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 1.27
> + BASE_NAME = Chassis2Lib
> + FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ChassisLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + IoAccessLib
> + IoLib
> + PcdLib
> + SerialPortLib
> +
> +[Sources.common]
> + ChassisLib.c
> +
> +[FeaturePcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
> +
> diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
> new file mode 100644
> index 000000000000..89992a4b6fd5
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> @@ -0,0 +1,51 @@
> +/** @file
> + Chassis Lib to provide Chessis specific functionality to all SOCs in
> + a Chassis.
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef CHASSIS_LIB_H__
> +#define CHASSIS_LIB_H__
> +
> +#include <Chassis.h>
> +
> +/**
> + Read Dcfg register
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +**/
> +UINT32
> +EFIAPI
> +DcfgRead32 (
> + IN UINTN Address
> + );
> +
> +/**
> + Write Dcfg register
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> + @return Value.
> +**/
> +UINT32
> +EFIAPI
> +DcfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> + Function to initialize Chassis Specific functions
> + **/
> +VOID
> +ChassisInit (
> + VOID
> + );
> +
> +#endif // CHASSIS_LIB_H__
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 2ac047a89274..3e79f502c127 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -14,6 +14,9 @@ [Includes]
> Include
>
> [LibraryClasses]
> + ## @libraryclass Provides Chassis specific functions to other modules
> + ChassisLib|Include/Library/ChassisLib.h
> +
> ## @libraryclass Provides services to read/write to I2c devices
> I2cLib|Include/Library/I2cLib.h
>
> @@ -29,4 +32,5 @@ [PcdsFixedAtBuild.common]
>
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package
2020-04-01 14:17 ` Leif Lindholm
@ 2020-04-06 11:07 ` Pankaj Bansal
2020-04-06 11:51 ` Leif Lindholm
0 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-06 11:07 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Wednesday, April 1, 2020 7:48 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package
>
> On Fri, Mar 20, 2020 at 20:05:33 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > A Chassis is a base framework used for building SoCs.
> > We can think of Chassis/Soc/Platform(a.k.a Borad) in Oops terms.
>
> Board?
> "Oops" is not a term I am familiar with other than as an exclamation -
> can you elaborate please?
Oops: Object-Oriented Programming System
Basically concept of base classes and derived classes.
>
> > Chassis is base. Soc is based on some Chassis.
> > Platform is based on some Soc.
> >
> > SOCs that are designed around same chassis, reuse most of the components.
> >
> > Therefore, add the package for Chassis2. LS1043A and LS1046A SOCs belong
> > to Chassis2.
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > Silicon/NXP/Chassis2/Chassis2.dec | 23 +++++
> > Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 ++
> > Silicon/NXP/Chassis2/Include/Chassis.h | 34 +++++++
> > .../Chassis2/Library/ChassisLib/ChassisLib.c | 97 +++++++++++++++++++
> > .../Library/ChassisLib/ChassisLib.inf | 34 +++++++
> > Silicon/NXP/Include/Library/ChassisLib.h | 51 ++++++++++
> > Silicon/NXP/NxpQoriqLs.dec | 4 +
> > 7 files changed, 253 insertions(+)
> > create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
> > create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
> > create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
> > create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> > create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h
> >
> > diff --git a/Silicon/NXP/Chassis2/Chassis2.dec
> b/Silicon/NXP/Chassis2/Chassis2.dec
> > new file mode 100644
> > index 000000000000..a0048bd784ea
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis2/Chassis2.dec
> > @@ -0,0 +1,23 @@
> > +# @file
> > +# NXP Layerscape processor package.
> > +#
> > +# Copyright 2020 NXP
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +#
> > +
> > +[Defines]
> > + DEC_SPECIFICATION = 1.27
> > + PACKAGE_VERSION = 0.1
> > +
> >
> +################################################################
> ################
> > +#
> > +# Include Section - list of Include Paths that are provided by this package.
> > +# Comments are used for Keywords and Module Types.
> > +#
> > +#
> >
> +################################################################
> ################
> > +[Includes.common]
> > + Include # Root include for the package
> > +
> > diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc
> b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
> > new file mode 100644
> > index 000000000000..db8e5a92eacb
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
> > @@ -0,0 +1,10 @@
> > +# @file
> > +#
> > +# Copyright 2020 NXP
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +#
> > +
> > +[LibraryClasses.common]
> > + ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> > diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h
> b/Silicon/NXP/Chassis2/Include/Chassis.h
> > new file mode 100644
> > index 000000000000..72bd97efd004
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> > @@ -0,0 +1,34 @@
> > +/** @file
> > +
> > + Copyright 2020 NXP
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#ifndef CHASSIS_H__
> > +#define CHASSIS_H__
> > +
> > +#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
> > +
> > +/* SMMU Defintions */
> > +#define SMMU_BASE_ADDR 0x09000000
> > +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> > +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> > +
> > +#define SCR0_USFCFG_MASK 0x00000400
> > +#define SCR0_CLIENTPD_MASK 0x00000001
> > +#define SACR_PAGESIZE_MASK 0x00010000
> > +
> > +/**
> > + The Device Configuration Unit provides general purpose configuration and
> > + status for the device. These registers only support 32-bit accesses.
> > +**/
> > +#pragma pack(1)
> > +typedef struct {
> > + UINT8 Reserved0[0x100 - 0x0];
> > + UINT32 RcwSr[16]; // Reset Control Word Status Register
>
> If this is the formal word as used in official documentation, it still
> needs listing in a glossary in the file comment header.
This is register in SOC.
I thought the explanation in structure definition is fine for registers.
In https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/v/release/2.20/6_documenting_software/64_what_you_must_comment.html
6.4.4 Comment data structure declarations and #define statements.
The structure data members won't be used standalone in code without including the structure definition.
So any abbreviation can be referred from structure definition right ?
Also I referred https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/v/release/2.20/appendix_a_common_examples.html
Type declarations.
/// Structure without forward reference.
typedef struct {
UINT32 Signature; ///< Signature description.
EFI_HANDLE Handle; ///< Handle description.
EFI_PROD_PROT1_PROTOCOL ProdProt1; ///< ProdProt1 description.
EFI_PROD_PROT2_PROTOCOL ProdProt2; ///< ProdProt2 description.
} DRIVER_NAME_INSTANCE;
>
> > +} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
> > +#pragma pack()
> > +
> > +#endif // CHASSIS_H__
> > diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > new file mode 100644
> > index 000000000000..816e0fa29c4a
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > @@ -0,0 +1,97 @@
> > +/** @file
> > + Chassis specific functions common to all SOCs based on a specific Chessis
> > +
> > + Copyright 2020 NXP
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#include <Chassis.h>
> > +#include <Uefi.h>
> > +#include <Library/IoLib.h>
> > +#include <Library/IoAccessLib.h>
>
> Can you flip the two above lines around to get them in order?
OK
>
> > +#include <Library/PcdLib.h>
> > +#include <Library/SerialPortLib.h>
> > +
> > +/**
> > + Read Dcfg register
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +**/
> > +UINT32
> > +EFIAPI
> > +DcfgRead32 (
> > + IN UINTN Address
> > + )
> > +{
>
> Please replace these with the GetMmioOperations call, as designed.
>
> In fact, please provide an additional patch deleting all of the direct
> SwapMmio* functions from IoAccessLib.h and changing all of the
> SwapMmio* function definitions in IoAccessLib.c to STATIC to prevent
> future accidental direct use.
ok
>
> /
> Leif
>
> > + if (FeaturePcdGet (PcdDcfgBigEndian)) {
> > + return SwapMmioRead32 (Address);
> > + } else {
> > + return MmioRead32 (Address);
> > + }
> > +}
> > +
> > +/**
> > + Write Dcfg register
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > + @return Value.
> > +**/
> > +UINT32
> > +EFIAPI
> > +DcfgWrite32 (
> > + IN UINTN Address,
> > + IN UINT32 Value
> > + )
> > +{
> > + if (FeaturePcdGet (PcdDcfgBigEndian)) {
> > + return SwapMmioWrite32 (Address, Value);
> > + } else {
> > + return MmioWrite32 (Address, Value);
> > + }
> > +}
> > +
> > +/*
> > + * Setup SMMU in bypass mode
> > + * and also set its pagesize
> > + */
> > +STATIC
> > +VOID
> > +SmmuInit (
> > + VOID
> > + )
> > +{
> > + UINT32 Value;
> > +
> > + /* set pagesize as 64K and ssmu-500 in bypass mode */
> > + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) |
> SACR_PAGESIZE_MASK);
> > + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> > +
> > + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) |
> SCR0_CLIENTPD_MASK);
> > + Value &= ~SCR0_USFCFG_MASK;
> > + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> > +
> > + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) |
> SCR0_CLIENTPD_MASK);
> > + Value &= ~SCR0_USFCFG_MASK;
> > + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> > +}
> > +
> > +/**
> > + Function to initialize Chassis Specific functions
> > + **/
> > +VOID
> > +ChassisInit (
> > + VOID
> > + )
> > +{
> > + //
> > + // Early init serial Port to get board information.
> > + //
> > + SerialPortInitialize ();
> > +
> > + SmmuInit ();
> > +}
> > diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> > new file mode 100644
> > index 000000000000..2bb16af53134
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> > @@ -0,0 +1,34 @@
> > +# @file
> > +#
> > +# Copyright 2020 NXP
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause
> > +#
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 1.27
> > + BASE_NAME = Chassis2Lib
> > + FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = ChassisLib
> > +
> > +[Packages]
> > + ArmPkg/ArmPkg.dec
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/Chassis2/Chassis2.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[LibraryClasses]
> > + IoAccessLib
> > + IoLib
> > + PcdLib
> > + SerialPortLib
> > +
> > +[Sources.common]
> > + ChassisLib.c
> > +
> > +[FeaturePcd]
> > + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
> > +
> > diff --git a/Silicon/NXP/Include/Library/ChassisLib.h
> b/Silicon/NXP/Include/Library/ChassisLib.h
> > new file mode 100644
> > index 000000000000..89992a4b6fd5
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> > @@ -0,0 +1,51 @@
> > +/** @file
> > + Chassis Lib to provide Chessis specific functionality to all SOCs in
> > + a Chassis.
> > +
> > + Copyright 2020 NXP
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +**/
> > +
> > +#ifndef CHASSIS_LIB_H__
> > +#define CHASSIS_LIB_H__
> > +
> > +#include <Chassis.h>
> > +
> > +/**
> > + Read Dcfg register
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +**/
> > +UINT32
> > +EFIAPI
> > +DcfgRead32 (
> > + IN UINTN Address
> > + );
> > +
> > +/**
> > + Write Dcfg register
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > + @return Value.
> > +**/
> > +UINT32
> > +EFIAPI
> > +DcfgWrite32 (
> > + IN UINTN Address,
> > + IN UINT32 Value
> > + );
> > +
> > +/**
> > + Function to initialize Chassis Specific functions
> > + **/
> > +VOID
> > +ChassisInit (
> > + VOID
> > + );
> > +
> > +#endif // CHASSIS_LIB_H__
> > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> > index 2ac047a89274..3e79f502c127 100644
> > --- a/Silicon/NXP/NxpQoriqLs.dec
> > +++ b/Silicon/NXP/NxpQoriqLs.dec
> > @@ -14,6 +14,9 @@ [Includes]
> > Include
> >
> > [LibraryClasses]
> > + ## @libraryclass Provides Chassis specific functions to other modules
> > + ChassisLib|Include/Library/ChassisLib.h
> > +
> > ## @libraryclass Provides services to read/write to I2c devices
> > I2cLib|Include/Library/I2cLib.h
> >
> > @@ -29,4 +32,5 @@ [PcdsFixedAtBuild.common]
> >
> > [PcdsFeatureFlag]
> >
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x0000
> 0315
> > +
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
> >
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package
2020-04-06 11:07 ` Pankaj Bansal
@ 2020-04-06 11:51 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-06 11:51 UTC (permalink / raw)
To: Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
On Mon, Apr 06, 2020 at 11:07:45 +0000, Pankaj Bansal (OSS) wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Wednesday, April 1, 2020 7:48 PM
> > To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> > <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> > <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> > Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> > Subject: Re: [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package
> >
> > On Fri, Mar 20, 2020 at 20:05:33 +0530, Pankaj Bansal wrote:
> > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > >
> > > A Chassis is a base framework used for building SoCs.
> > > We can think of Chassis/Soc/Platform(a.k.a Borad) in Oops terms.
> >
> > Board?
> > "Oops" is not a term I am familiar with other than as an exclamation -
> > can you elaborate please?
>
> Oops: Object-Oriented Programming System
> Basically concept of base classes and derived classes.
Could it say object model instead?
/
Leif
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 19/28] Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (17 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 18/28] Silicon/NXP: Add Chassis2 Package Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 14:19 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 20/28] Silicon/NXP/LS1043A: Move SocLib to Soc Package Pankaj Bansal
` (10 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Now the we have added Chassis Package, move the chassis specific common
code for all SOCs belonging to same chassis to ChassisLib.
Use ChassisLib APIs in SocLib.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../Drivers/PlatformDxe/PlatformDxe.inf | 1 +
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
Silicon/NXP/Include/Chassis2/NxpSoc.h | 44 -------------
Silicon/NXP/LS1043A/Include/Soc.h | 6 +-
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 9 ++-
Silicon/NXP/Library/SocLib/Chassis.c | 61 -------------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 19 +-----
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 15 +----
Silicon/NXP/Library/SocLib/NxpChassis.h | 22 -------
Silicon/NXP/NxpQoriqLs.dec | 6 --
10 files changed, 14 insertions(+), 170 deletions(-)
delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 038d48949a39..e522db81e5c0 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -24,6 +24,7 @@ [Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7a43ad86d183..07ca6b34445f 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -19,6 +19,7 @@ [Packages]
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
deleted file mode 100644
index 3f00a2614131..000000000000
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/** Soc.h
-* Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-* Copyright 2017-2020 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_SOC_H_
-#define NXP_SOC_H_
-
-#define CLK_FREQ 100000000
-
-#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
-
-/* SMMU Defintions */
-#define SMMU_BASE_ADDR 0x09000000
-#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
-#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
-#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
-#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
-#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
-
-#define SCR0_USFCFG_MASK 0x00000400
-#define SCR0_CLIENTPD_MASK 0x00000001
-#define SACR_PAGESIZE_MASK 0x00010000
-#define IDR1_PAGESIZE_MASK 0x80000000
-
-/* Device Configuration and Pin Control */
-typedef struct {
- UINT8 Res0[0x100-0x00];
- UINT32 RcwSr[16]; /* Reset control word status */
-#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
-#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
-} CCSR_GUR;
-
-UINT32
-EFIAPI
-GurRead (
- IN UINTN Address
- );
-
-#endif /* NXP_SOC_H_ */
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index e62de570da8a..97a77d3f5da6 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -8,7 +8,7 @@
#ifndef SOC_H__
#define SOC_H__
-#include <Chassis2/NxpSoc.h>
+#include <Chassis.h>
/**
Soc Memory Map
@@ -43,13 +43,13 @@
#define LS1043A_I2C_SIZE 0x10000
#define LS1043A_I2C_NUM_CONTROLLERS 4
-#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS
+#define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
/**
Reset Control Word (RCW) Bits
**/
#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
-typedef CCSR_GUR LS1043A_DEVICE_CONFIG;
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
#endif // SOC_H__
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 6239cfe761e6..7e75d5b7cba9 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -7,6 +7,8 @@
#
#
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
[LibraryClasses.common]
PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -29,9 +31,6 @@ [PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
- #
- # Big Endian IPs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
-
+[PcdsFeatureFlag]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
##
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
deleted file mode 100644
index 90677f0f36ca..000000000000
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/** @file
- SoC specific Library containg functions to initialize various SoC components
-
- Copyright 2017-2020 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#ifdef CHASSIS2
-#include <Chassis2/NxpSoc.h>
-#elif CHASSIS3
-#include <Chassis3/NxpSoc.h>
-#endif
-#include <Library/ArmSmcLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoAccessLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
-
-#include "NxpChassis.h"
-
-UINT32
-EFIAPI
-GurRead (
- IN UINTN Address
- )
-{
- if (FixedPcdGetBool (PcdGurBigEndian)) {
- return SwapMmioRead32 (Address);
- } else {
- return MmioRead32 (Address);
- }
-}
-
-/*
- * Setup SMMU in bypass mode
- * and also set its pagesize
- */
-VOID
-SmmuInit (
- VOID
- )
-{
- UINT32 Value;
-
- /* set pagesize as 64K and ssmu-500 in bypass mode */
- Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
- MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
-
- Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
- MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
-
- Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
- MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
-}
-
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index b14ada7f595d..a50c072e84d5 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -8,16 +8,8 @@
**/
#include <Base.h>
-#include <NxpChassis.h>
-#include <Chassis2/NxpSoc.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
+#include <Library/ChassisLib.h>
#include <Library/DebugLib.h>
-#include <Library/IoAccessLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
#include <Library/SocLib.h>
#include <Soc.h>
@@ -61,7 +53,7 @@ SocGetClock (
switch (ClockType) {
case NXP_UART_CLOCK:
case NXP_I2C_CLOCK:
- RcwSr = GurRead ((UINTN)&Dcfg->RcwSr[0]);
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
break;
default:
@@ -79,12 +71,7 @@ SocInit (
VOID
)
{
- SmmuInit ();
-
- //
- // Early init serial Port to get board information.
- //
- SerialPortInitialize ();
+ ChassisInit ();
return;
}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index bb15e0a3d710..1d042bbfc4e4 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -14,25 +14,14 @@ [Defines]
LIBRARY_CLASS = SocLib
[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec
[LibraryClasses]
- BaseLib
+ ChassisLib
DebugLib
- IoAccessLib
- SerialPortLib
[Sources.common]
- Chassis.c
Chassis2/Soc.c
-
-[BuildOptions]
- GCC:*_*_*_CC_FLAGS = -DCHASSIS2
-
-[FixedPcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
deleted file mode 100644
index 836df103f80f..000000000000
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/** @file
-* Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-* Copyright 2017-2020 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_CHASSIS_H_
-#define NXP_CHASSIS_H_
-
-/*
- * Setup SMMU in bypass mode
- * and also set its pagesize
- */
-VOID
-SmmuInit (
- VOID
- );
-
-#endif /* NXP_CHASSIS_H_ */
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 3e79f502c127..71e43c1ffd86 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -24,12 +24,6 @@ [Guids.common]
gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
-[PcdsFixedAtBuild.common]
- #
- # Pcds to support Big Endian IPs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
-
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 19/28] Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg
2020-03-20 14:35 ` [PATCH v2 19/28] Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg Pankaj Bansal
@ 2020-04-01 14:19 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 14:19 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:34 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Now the we have added Chassis Package, move the chassis specific common
> code for all SOCs belonging to same chassis to ChassisLib.
>
> Use ChassisLib APIs in SocLib.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
There will be minor API changes required to this file based on
addressing other feedback, but unless any substantial rewrites are
needed:
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.inf | 1 +
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 44 -------------
> Silicon/NXP/LS1043A/Include/Soc.h | 6 +-
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 9 ++-
> Silicon/NXP/Library/SocLib/Chassis.c | 61 -------------------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 19 +-----
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 15 +----
> Silicon/NXP/Library/SocLib/NxpChassis.h | 22 -------
> Silicon/NXP/NxpQoriqLs.dec | 6 --
> 10 files changed, 14 insertions(+), 170 deletions(-)
> delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> index 038d48949a39..e522db81e5c0 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -24,6 +24,7 @@ [Packages]
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 7a43ad86d183..07ca6b34445f 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -19,6 +19,7 @@ [Packages]
> ArmPlatformPkg/ArmPlatformPkg.dec
> EmbeddedPkg/EmbeddedPkg.dec
> MdePkg/MdePkg.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> deleted file mode 100644
> index 3f00a2614131..000000000000
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -/** Soc.h
> -* Header defining the Base addresses, sizes, flags etc for chassis 1
> -*
> -* Copyright 2017-2020 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef NXP_SOC_H_
> -#define NXP_SOC_H_
> -
> -#define CLK_FREQ 100000000
> -
> -#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> -
> -/* SMMU Defintions */
> -#define SMMU_BASE_ADDR 0x09000000
> -#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> -#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> -#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> -#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> -#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> -
> -#define SCR0_USFCFG_MASK 0x00000400
> -#define SCR0_CLIENTPD_MASK 0x00000001
> -#define SACR_PAGESIZE_MASK 0x00010000
> -#define IDR1_PAGESIZE_MASK 0x80000000
> -
> -/* Device Configuration and Pin Control */
> -typedef struct {
> - UINT8 Res0[0x100-0x00];
> - UINT32 RcwSr[16]; /* Reset control word status */
> -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> -} CCSR_GUR;
> -
> -UINT32
> -EFIAPI
> -GurRead (
> - IN UINTN Address
> - );
> -
> -#endif /* NXP_SOC_H_ */
> diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
> index e62de570da8a..97a77d3f5da6 100644
> --- a/Silicon/NXP/LS1043A/Include/Soc.h
> +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> @@ -8,7 +8,7 @@
> #ifndef SOC_H__
> #define SOC_H__
>
> -#include <Chassis2/NxpSoc.h>
> +#include <Chassis.h>
>
> /**
> Soc Memory Map
> @@ -43,13 +43,13 @@
> #define LS1043A_I2C_SIZE 0x10000
> #define LS1043A_I2C_NUM_CONTROLLERS 4
>
> -#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS
> +#define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
>
> /**
> Reset Control Word (RCW) Bits
> **/
> #define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
>
> -typedef CCSR_GUR LS1043A_DEVICE_CONFIG;
> +typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
>
> #endif // SOC_H__
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index 6239cfe761e6..7e75d5b7cba9 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -7,6 +7,8 @@
> #
> #
>
> +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
> +
> [LibraryClasses.common]
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
> SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -29,9 +31,6 @@ [PcdsFixedAtBuild.common]
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
>
> - #
> - # Big Endian IPs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> -
> +[PcdsFeatureFlag]
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> ##
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> deleted file mode 100644
> index 90677f0f36ca..000000000000
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ /dev/null
> @@ -1,61 +0,0 @@
> -/** @file
> - SoC specific Library containg functions to initialize various SoC components
> -
> - Copyright 2017-2020 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#ifdef CHASSIS2
> -#include <Chassis2/NxpSoc.h>
> -#elif CHASSIS3
> -#include <Chassis3/NxpSoc.h>
> -#endif
> -#include <Library/ArmSmcLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoAccessLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PrintLib.h>
> -#include <Library/SerialPortLib.h>
> -
> -#include "NxpChassis.h"
> -
> -UINT32
> -EFIAPI
> -GurRead (
> - IN UINTN Address
> - )
> -{
> - if (FixedPcdGetBool (PcdGurBigEndian)) {
> - return SwapMmioRead32 (Address);
> - } else {
> - return MmioRead32 (Address);
> - }
> -}
> -
> -/*
> - * Setup SMMU in bypass mode
> - * and also set its pagesize
> - */
> -VOID
> -SmmuInit (
> - VOID
> - )
> -{
> - UINT32 Value;
> -
> - /* set pagesize as 64K and ssmu-500 in bypass mode */
> - Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> - MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> -
> - Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> - MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> -
> - Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> - MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> -}
> -
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index b14ada7f595d..a50c072e84d5 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -8,16 +8,8 @@
> **/
>
> #include <Base.h>
> -#include <NxpChassis.h>
> -#include <Chassis2/NxpSoc.h>
> -#include <Library/BaseLib.h>
> -#include <Library/BaseMemoryLib.h>
> +#include <Library/ChassisLib.h>
> #include <Library/DebugLib.h>
> -#include <Library/IoAccessLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PrintLib.h>
> -#include <Library/SerialPortLib.h>
> #include <Library/SocLib.h>
> #include <Soc.h>
>
> @@ -61,7 +53,7 @@ SocGetClock (
> switch (ClockType) {
> case NXP_UART_CLOCK:
> case NXP_I2C_CLOCK:
> - RcwSr = GurRead ((UINTN)&Dcfg->RcwSr[0]);
> + RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
> ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
> break;
> default:
> @@ -79,12 +71,7 @@ SocInit (
> VOID
> )
> {
> - SmmuInit ();
> -
> - //
> - // Early init serial Port to get board information.
> - //
> - SerialPortInitialize ();
> + ChassisInit ();
>
> return;
> }
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index bb15e0a3d710..1d042bbfc4e4 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -14,25 +14,14 @@ [Defines]
> LIBRARY_CLASS = SocLib
>
> [Packages]
> - ArmPkg/ArmPkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/LS1043A/LS1043A.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> - BaseLib
> + ChassisLib
> DebugLib
> - IoAccessLib
> - SerialPortLib
>
> [Sources.common]
> - Chassis.c
> Chassis2/Soc.c
> -
> -[BuildOptions]
> - GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> -
> -[FixedPcd]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
> deleted file mode 100644
> index 836df103f80f..000000000000
> --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/** @file
> -* Header defining the Base addresses, sizes, flags etc for chassis 1
> -*
> -* Copyright 2017-2020 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef NXP_CHASSIS_H_
> -#define NXP_CHASSIS_H_
> -
> -/*
> - * Setup SMMU in bypass mode
> - * and also set its pagesize
> - */
> -VOID
> -SmmuInit (
> - VOID
> - );
> -
> -#endif /* NXP_CHASSIS_H_ */
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 3e79f502c127..71e43c1ffd86 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -24,12 +24,6 @@ [Guids.common]
> gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
>
> -[PcdsFixedAtBuild.common]
> - #
> - # Pcds to support Big Endian IPs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> -
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 20/28] Silicon/NXP/LS1043A: Move SocLib to Soc Package
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (18 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 19/28] Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 14:20 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib Pankaj Bansal
` (9 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
The SocLib contains code specific to an Soc. it should be part of
SOC package.
Therefore, move the SocLib to Soc Package.
Since we are moving the files to Soc Package, no need to mention the
Soc name in file names. Their location is enough to indicate for which
Soc the files are.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 +-
.../SocLib/Chassis2/Soc.c => LS1043A/Library/SocLib/SocLib.c} | 0
.../LS1043aSocLib.inf => LS1043A/Library/SocLib/SocLib.inf} | 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
rename Silicon/NXP/{Library/SocLib/Chassis2/Soc.c => LS1043A/Library/SocLib/SocLib.c} (100%)
rename Silicon/NXP/{Library/SocLib/LS1043aSocLib.inf => LS1043A/Library/SocLib/SocLib.inf} (92%)
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 7e75d5b7cba9..a5942c0f2c9c 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -11,7 +11,7 @@
[LibraryClasses.common]
PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
- SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+ SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
SerialUartClockLib|Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
similarity index 100%
rename from Silicon/NXP/Library/SocLib/Chassis2/Soc.c
rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
similarity index 92%
rename from Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
index 1d042bbfc4e4..3d0f988e1c67 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
@@ -24,4 +24,4 @@ [LibraryClasses]
DebugLib
[Sources.common]
- Chassis2/Soc.c
+ SocLib.c
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 20/28] Silicon/NXP/LS1043A: Move SocLib to Soc Package
2020-03-20 14:35 ` [PATCH v2 20/28] Silicon/NXP/LS1043A: Move SocLib to Soc Package Pankaj Bansal
@ 2020-04-01 14:20 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 14:20 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:35 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> The SocLib contains code specific to an Soc. it should be part of
> SOC package.
> Therefore, move the SocLib to Soc Package.
> Since we are moving the files to Soc Package, no need to mention the
> Soc name in file names. Their location is enough to indicate for which
> Soc the files are.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 +-
> .../SocLib/Chassis2/Soc.c => LS1043A/Library/SocLib/SocLib.c} | 0
> .../LS1043aSocLib.inf => LS1043A/Library/SocLib/SocLib.inf} | 2 +-
> 3 files changed, 2 insertions(+), 2 deletions(-)
> rename Silicon/NXP/{Library/SocLib/Chassis2/Soc.c => LS1043A/Library/SocLib/SocLib.c} (100%)
> rename Silicon/NXP/{Library/SocLib/LS1043aSocLib.inf => LS1043A/Library/SocLib/SocLib.inf} (92%)
>
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index 7e75d5b7cba9..a5942c0f2c9c 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -11,7 +11,7 @@
>
> [LibraryClasses.common]
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
> - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> + SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
> SerialUartClockLib|Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
>
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
> similarity index 100%
> rename from Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
> similarity index 92%
> rename from Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
> index 1d042bbfc4e4..3d0f988e1c67 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
> @@ -24,4 +24,4 @@ [LibraryClasses]
> DebugLib
>
> [Sources.common]
> - Chassis2/Soc.c
> + SocLib.c
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (19 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 20/28] Silicon/NXP/LS1043A: Move SocLib to Soc Package Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 14:53 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 22/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use default ArmPlatformHelper.S Pankaj Bansal
` (8 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
PlatformPeiLib is going to be linked to Platform PEIM.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../Library/PlatformPeiLib/PlatformPeiLib.c | 30 ++++++++++++++
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 41 +++++++++++++++++++
Silicon/NXP/NxpQoriqLs.dsc.inc | 3 +-
3 files changed, 73 insertions(+), 1 deletion(-)
create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
new file mode 100644
index 000000000000..f64e564469f8
--- /dev/null
+++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
@@ -0,0 +1,30 @@
+/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#define XPRINT(x) PRINT(x)
+#define PRINT(x) #x
+
+EFI_STATUS
+EFIAPI
+PlatformPeim (
+ VOID
+ )
+{
+ BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));
+ DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT (WORKSPACE_GIT_VERSION)));
+ DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT (PACKAGES_PATH_GIT_VERSION)));
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
new file mode 100644
index 000000000000..fb42693daa20
--- /dev/null
+++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
@@ -0,0 +1,41 @@
+#/** @file
+#
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmPlatformPeiLib
+ FILE_GUID = 49d37060-70b5-11e0-aa2d-0002a5d5c51b
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformPeiLib
+
+[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DWORKSPACE_GIT_VERSION="$(WORKSPACE_GIT_VERSION)"
+ GCC:*_*_*_CC_FLAGS = -DPACKAGES_PATH_GIT_VERSION="$(PACKAGES_PATH_GIT_VERSION)"
+
+[Sources]
+ PlatformPeiLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ PcdLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+ gArmTokenSpaceGuid.PcdFvSize
+
+[depex]
+ TRUE
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 234a5e2707cd..5f77f47f0399 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -101,6 +101,8 @@ [LibraryClasses.common]
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
+
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
@@ -111,7 +113,6 @@ [LibraryClasses.common.SEC]
PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
# 1/123 faster than Stm or Vstm version
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib
2020-03-20 14:35 ` [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib Pankaj Bansal
@ 2020-04-01 14:53 ` Leif Lindholm
2020-04-06 14:53 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 14:53 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:36 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> PlatformPeiLib is going to be linked to Platform PEIM.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../Library/PlatformPeiLib/PlatformPeiLib.c | 30 ++++++++++++++
> .../Library/PlatformPeiLib/PlatformPeiLib.inf | 41 +++++++++++++++++++
> Silicon/NXP/NxpQoriqLs.dsc.inc | 3 +-
> 3 files changed, 73 insertions(+), 1 deletion(-)
> create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
>
> diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> new file mode 100644
> index 000000000000..f64e564469f8
> --- /dev/null
> +++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> @@ -0,0 +1,30 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Library/HobLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
Although this is based on an existing library, please sort includes
alphabetically here.
> +
> +#define XPRINT(x) PRINT(x)
> +#define PRINT(x) #x
This isn't a PRINT operation, this is a Stringize operation.
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformPeim (
> + VOID
> + )
> +{
> + BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));
> + DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT (WORKSPACE_GIT_VERSION)));
> + DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT (PACKAGES_PATH_GIT_VERSION)));
The only benefit I can see from the macro as opposed to using '#'
directly is that it permits wrapping of too long lines, so please do
that.
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> new file mode 100644
> index 000000000000..fb42693daa20
> --- /dev/null
> +++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> @@ -0,0 +1,41 @@
> +#/** @file
> +#
> +# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
Update version.
> + BASE_NAME = ArmPlatformPeiLib
> + FILE_GUID = 49d37060-70b5-11e0-aa2d-0002a5d5c51b
Unless this is another magic GUID filename (like ACPI), please
generate a new GUID.
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformPeiLib
> +
> +[BuildOptions]
> + GCC:*_*_*_CC_FLAGS = -DWORKSPACE_GIT_VERSION="$(WORKSPACE_GIT_VERSION)"
> + GCC:*_*_*_CC_FLAGS = -DPACKAGES_PATH_GIT_VERSION="$(PACKAGES_PATH_GIT_VERSION)"
Does this not require special magic build command line options to do
anything useful? This needs documenting.
/
Leif
> +
> +[Sources]
> + PlatformPeiLib.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + DebugLib
> + HobLib
> + PcdLib
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFvBaseAddress
> + gArmTokenSpaceGuid.PcdFvSize
> +
> +[depex]
> + TRUE
> diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> index 234a5e2707cd..5f77f47f0399 100644
> --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> @@ -101,6 +101,8 @@ [LibraryClasses.common]
> PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>
> + PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> +
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> @@ -111,7 +113,6 @@ [LibraryClasses.common.SEC]
> PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
>
> # 1/123 faster than Stm or Vstm version
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib
2020-04-01 14:53 ` Leif Lindholm
@ 2020-04-06 14:53 ` Pankaj Bansal
2020-04-07 12:53 ` Leif Lindholm
0 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-06 14:53 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Wednesday, April 1, 2020 8:23 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib
>
> On Fri, Mar 20, 2020 at 20:05:36 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > PlatformPeiLib is going to be linked to Platform PEIM.
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > .../Library/PlatformPeiLib/PlatformPeiLib.c | 30 ++++++++++++++
> > .../Library/PlatformPeiLib/PlatformPeiLib.inf | 41 +++++++++++++++++++
> > Silicon/NXP/NxpQoriqLs.dsc.inc | 3 +-
> > 3 files changed, 73 insertions(+), 1 deletion(-)
> > create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> > create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> >
> > diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> > new file mode 100644
> > index 000000000000..f64e564469f8
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> > @@ -0,0 +1,30 @@
> > +/** @file
> > +*
> > +* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> > +* Copyright 2020 NXP
> > +*
> > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > +*
> > +**/
> > +
> > +#include <PiPei.h>
> > +
> > +#include <Library/HobLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/PcdLib.h>
>
> Although this is based on an existing library, please sort includes
> alphabetically here.
>
> > +
> > +#define XPRINT(x) PRINT(x)
> > +#define PRINT(x) #x
>
> This isn't a PRINT operation, this is a Stringize operation.
OK, I can rename these to
#define PRINTSTR(x) STR(x)
#define STR(x) #x
>
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +PlatformPeim (
> > + VOID
> > + )
> > +{
> > + BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));
> > + DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT
> (WORKSPACE_GIT_VERSION)));
> > + DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT
> (PACKAGES_PATH_GIT_VERSION)));
>
> The only benefit I can see from the macro as opposed to using '#'
> directly is that it permits wrapping of too long lines, so please do
> that.
OK.
>
> > +
> > + return EFI_SUCCESS;
> > +}
> > diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> > new file mode 100644
> > index 000000000000..fb42693daa20
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> > @@ -0,0 +1,41 @@
> > +#/** @file
> > +#
> > +# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> > +# Copyright 2020 NXP
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +#**/
> > +
> > +[Defines]
> > + INF_VERSION = 0x00010005
>
> Update version.
>
> > + BASE_NAME = ArmPlatformPeiLib
> > + FILE_GUID = 49d37060-70b5-11e0-aa2d-0002a5d5c51b
>
> Unless this is another magic GUID filename (like ACPI), please
> generate a new GUID.
Since this Library is replacement implementation of ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf,
Couldn't we use the same GUID ?
>
> > + MODULE_TYPE = PEIM
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = PlatformPeiLib
> > +
> > +[BuildOptions]
> > + GCC:*_*_*_CC_FLAGS = -
> DWORKSPACE_GIT_VERSION="$(WORKSPACE_GIT_VERSION)"
> > + GCC:*_*_*_CC_FLAGS = -
> DPACKAGES_PATH_GIT_VERSION="$(PACKAGES_PATH_GIT_VERSION)"
>
> Does this not require special magic build command line options to do
> anything useful? This needs documenting.
Actually I had submitted a patch is BaseTools for this:
https://edk2.groups.io/g/devel/message/53146
This patch makes use of that BaseTools patch.
But the BaseTools patch was not accepted because that is Linux specific.
Still these changes don't cause any negative affect.
Without BaseTools patch, empty string would be printed.
>
> /
> Leif
>
> > +
> > +[Sources]
> > + PlatformPeiLib.c
> > +
> > +[Packages]
> > + ArmPkg/ArmPkg.dec
> > + MdeModulePkg/MdeModulePkg.dec
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[LibraryClasses]
> > + DebugLib
> > + HobLib
> > + PcdLib
> > +
> > +[FixedPcd]
> > + gArmTokenSpaceGuid.PcdFvBaseAddress
> > + gArmTokenSpaceGuid.PcdFvSize
> > +
> > +[depex]
> > + TRUE
> > diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> > index 234a5e2707cd..5f77f47f0399 100644
> > --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> > +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> > @@ -101,6 +101,8 @@ [LibraryClasses.common]
> > PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> > PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
> >
> > + PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> > +
> > [LibraryClasses.common.SEC]
> > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> >
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
> ressLib.inf
> > @@ -111,7 +113,6 @@ [LibraryClasses.common.SEC]
> >
> PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiH
> obListPointerLib.inf
> >
> MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiM
> emoryAllocationLib.inf
> >
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib
> .inf
> > - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> > MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> >
> > # 1/123 faster than Stm or Vstm version
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib
2020-04-06 14:53 ` Pankaj Bansal
@ 2020-04-07 12:53 ` Leif Lindholm
2020-04-07 17:00 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-07 12:53 UTC (permalink / raw)
To: Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
OK, taking another look at this patch, this simply needs to be
deleted. Here is the sum total relevant difference compared to the
ArmPlatformPkg one.
DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT (WORKSPACE_GIT_VERSION)));
DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT (PACKAGES_PATH_GIT_VERSION)));
If all you want to do is to print that sort of thing, please don't
fork a core library to do so.
First of all, please do like most other platforms and override
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
if -D FIRMWARE_VER is specified on your build command line.
You can then extract current top commits of your respective
repositories and not worry about getting this.
I would suggest iterating across all locations in PACKAGES_PATH and
then doing something similar to
https://git.linaro.org/uefi/uefi-tools.git/tree/edk2-build.sh#n400
appending together.
If something like this should be integrated into the build system
(which might not be a bad idea), then it needs to be so properly,
rather than shoehorned in for each platform.
(In the past, this was difficult because we supported both git and
svn, but I would say we have given up pretending that is possible.)
For now, you could add the printout in a standalone Depex TRUE PEIM
added to your [FV.FVMAIN_COMPACT].
/
Leif
On Mon, Apr 06, 2020 at 14:53:02 +0000, Pankaj Bansal (OSS) wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Wednesday, April 1, 2020 8:23 PM
> > To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> > <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> > <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> > Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> > Subject: Re: [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib
> >
> > On Fri, Mar 20, 2020 at 20:05:36 +0530, Pankaj Bansal wrote:
> > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > >
> > > PlatformPeiLib is going to be linked to Platform PEIM.
> > >
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > ---
> > > .../Library/PlatformPeiLib/PlatformPeiLib.c | 30 ++++++++++++++
> > > .../Library/PlatformPeiLib/PlatformPeiLib.inf | 41 +++++++++++++++++++
> > > Silicon/NXP/NxpQoriqLs.dsc.inc | 3 +-
> > > 3 files changed, 73 insertions(+), 1 deletion(-)
> > > create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> > > create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> > >
> > > diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> > b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> > > new file mode 100644
> > > index 000000000000..f64e564469f8
> > > --- /dev/null
> > > +++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> > > @@ -0,0 +1,30 @@
> > > +/** @file
> > > +*
> > > +* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> > > +* Copyright 2020 NXP
> > > +*
> > > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +*
> > > +**/
> > > +
> > > +#include <PiPei.h>
> > > +
> > > +#include <Library/HobLib.h>
> > > +#include <Library/DebugLib.h>
> > > +#include <Library/PcdLib.h>
> >
> > Although this is based on an existing library, please sort includes
> > alphabetically here.
> >
> > > +
> > > +#define XPRINT(x) PRINT(x)
> > > +#define PRINT(x) #x
> >
> > This isn't a PRINT operation, this is a Stringize operation.
>
> OK, I can rename these to
> #define PRINTSTR(x) STR(x)
> #define STR(x) #x
>
> >
> > > +
> > > +EFI_STATUS
> > > +EFIAPI
> > > +PlatformPeim (
> > > + VOID
> > > + )
> > > +{
> > > + BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));
> > > + DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT
> > (WORKSPACE_GIT_VERSION)));
> > > + DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT
> > (PACKAGES_PATH_GIT_VERSION)));
> >
> > The only benefit I can see from the macro as opposed to using '#'
> > directly is that it permits wrapping of too long lines, so please do
> > that.
>
> OK.
>
> >
> > > +
> > > + return EFI_SUCCESS;
> > > +}
> > > diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> > b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> > > new file mode 100644
> > > index 000000000000..fb42693daa20
> > > --- /dev/null
> > > +++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> > > @@ -0,0 +1,41 @@
> > > +#/** @file
> > > +#
> > > +# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> > > +# Copyright 2020 NXP
> > > +#
> > > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +#
> > > +#**/
> > > +
> > > +[Defines]
> > > + INF_VERSION = 0x00010005
> >
> > Update version.
> >
> > > + BASE_NAME = ArmPlatformPeiLib
> > > + FILE_GUID = 49d37060-70b5-11e0-aa2d-0002a5d5c51b
> >
> > Unless this is another magic GUID filename (like ACPI), please
> > generate a new GUID.
>
> Since this Library is replacement implementation of
> ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf,
> Couldn't we use the same GUID ?
>
> >
> > > + MODULE_TYPE = PEIM
> > > + VERSION_STRING = 1.0
> > > + LIBRARY_CLASS = PlatformPeiLib
> > > +
> > > +[BuildOptions]
> > > + GCC:*_*_*_CC_FLAGS = -
> > DWORKSPACE_GIT_VERSION="$(WORKSPACE_GIT_VERSION)"
> > > + GCC:*_*_*_CC_FLAGS = -
> > DPACKAGES_PATH_GIT_VERSION="$(PACKAGES_PATH_GIT_VERSION)"
> >
> > Does this not require special magic build command line options to do
> > anything useful? This needs documenting.
>
> Actually I had submitted a patch is BaseTools for this:
> https://edk2.groups.io/g/devel/message/53146
>
> This patch makes use of that BaseTools patch.
> But the BaseTools patch was not accepted because that is Linux specific.
> Still these changes don't cause any negative affect.
> Without BaseTools patch, empty string would be printed.
>
> >
> > /
> > Leif
> >
> > > +
> > > +[Sources]
> > > + PlatformPeiLib.c
> > > +
> > > +[Packages]
> > > + ArmPkg/ArmPkg.dec
> > > + MdeModulePkg/MdeModulePkg.dec
> > > + MdePkg/MdePkg.dec
> > > + Silicon/NXP/NxpQoriqLs.dec
> > > +
> > > +[LibraryClasses]
> > > + DebugLib
> > > + HobLib
> > > + PcdLib
> > > +
> > > +[FixedPcd]
> > > + gArmTokenSpaceGuid.PcdFvBaseAddress
> > > + gArmTokenSpaceGuid.PcdFvSize
> > > +
> > > +[depex]
> > > + TRUE
> > > diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> > > index 234a5e2707cd..5f77f47f0399 100644
> > > --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> > > +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> > > @@ -101,6 +101,8 @@ [LibraryClasses.common]
> > > PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> > > PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
> > >
> > > + PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> > > +
> > > [LibraryClasses.common.SEC]
> > > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > >
> > UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
> > ressLib.inf
> > > @@ -111,7 +113,6 @@ [LibraryClasses.common.SEC]
> > >
> > PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiH
> > obListPointerLib.inf
> > >
> > MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiM
> > emoryAllocationLib.inf
> > >
> > PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib
> > .inf
> > > - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> > > MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> > >
> > > # 1/123 faster than Stm or Vstm version
> > > --
> > > 2.17.1
> > >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib
2020-04-07 12:53 ` Leif Lindholm
@ 2020-04-07 17:00 ` Pankaj Bansal
2020-04-08 13:04 ` [edk2-devel] " Leif Lindholm
0 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-07 17:00 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> OK, taking another look at this patch, this simply needs to be
> deleted. Here is the sum total relevant difference compared to the
> ArmPlatformPkg one.
>
> DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT
> (WORKSPACE_GIT_VERSION)));
> DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT
> (PACKAGES_PATH_GIT_VERSION)));
>
> If all you want to do is to print that sort of thing, please don't
> fork a core library to do so.
Not just the commit info. The plan is to print core/cluster info also from
this peim. As I have already stated in PATCH 10/28, that some print information would
be put into common code instead of SOC specific code.
In fact the further plan is to fixup device tree in this library before DXE phase starts.
So, this fork is needed.
>
> First of all, please do like most other platforms and override
> gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> if -D FIRMWARE_VER is specified on your build command line.
>
> You can then extract current top commits of your respective
> repositories and not worry about getting this.
> I would suggest iterating across all locations in PACKAGES_PATH and
> then doing something similar to
> https://git.linaro.org/uefi/uefi-tools.git/tree/edk2-build.sh#n400
> appending together.
>
OK, I can use this for printing git commit info.
> If something like this should be integrated into the build system
> (which might not be a bad idea), then it needs to be so properly,
> rather than shoehorned in for each platform.
I agree. Actually IMO, best place would be python script to do this.
I don't have much experience with python script.
That is why I made changes in shell script.
> (In the past, this was difficult because we supported both git and
> svn, but I would say we have given up pretending that is possible.)
>
> For now, you could add the printout in a standalone Depex TRUE PEIM
> added to your [FV.FVMAIN_COMPACT].
As I said, that version print is just one of the many things that we wish to
do in platform PEIM.
>
> /
> Leif
>
> On Mon, Apr 06, 2020 at 14:53:02 +0000, Pankaj Bansal (OSS) wrote:
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [edk2-devel] [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib
2020-04-07 17:00 ` Pankaj Bansal
@ 2020-04-08 13:04 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-08 13:04 UTC (permalink / raw)
To: devel, pankaj.bansal
Cc: Pankaj Bansal (OSS), Meenakshi Aggarwal, Michael D Kinney,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
On Tue, Apr 07, 2020 at 17:00:50 +0000, Pankaj Bansal wrote:
> > OK, taking another look at this patch, this simply needs to be
> > deleted. Here is the sum total relevant difference compared to the
> > ArmPlatformPkg one.
> >
> > DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT
> > (WORKSPACE_GIT_VERSION)));
> > DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT
> > (PACKAGES_PATH_GIT_VERSION)));
> >
> > If all you want to do is to print that sort of thing, please don't
> > fork a core library to do so.
>
> Not just the commit info. The plan is to print core/cluster info also from
> this peim. As I have already stated in PATCH 10/28, that some print information would
> be put into common code instead of SOC specific code.
Sure, but there are 11 patches in between. There is no way I am going
to recall what you stated was going to happen to something as basic as
a DEBUG printout by the time I get here. And that comment stated "a
common PEIM", not "a forked PlatformPeiLib containing only the
printouts".
> In fact the further plan is to fixup device tree in this library
> before DXE phase starts. So, this fork is needed.
Not at this time. See below.
> > First of all, please do like most other platforms and override
> > gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> > if -D FIRMWARE_VER is specified on your build command line.
> >
> > You can then extract current top commits of your respective
> > repositories and not worry about getting this.
> > I would suggest iterating across all locations in PACKAGES_PATH and
> > then doing something similar to
> > https://git.linaro.org/uefi/uefi-tools.git/tree/edk2-build.sh#n400
> > appending together.
> >
>
> OK, I can use this for printing git commit info.
>
> > If something like this should be integrated into the build system
> > (which might not be a bad idea), then it needs to be so properly,
> > rather than shoehorned in for each platform.
>
> I agree. Actually IMO, best place would be python script to do this.
> I don't have much experience with python script.
> That is why I made changes in shell script.
Yes, but edk2 is a cross-os project, so Python is needed.
To clarify, I think there shouldn't be a separate script to call, but
that this should be integrated into the build command itself, and
accessible as other predefined variables (like $ARCH).
If you would like to raise a feature request in
https://bugzilla.tianocore.org/enter_bug.cgi?product=EDK2, that would
be a good start even if you're not able to do the work yourself.
> > (In the past, this was difficult because we supported both git and
> > svn, but I would say we have given up pretending that is possible.)
> >
> > For now, you could add the printout in a standalone Depex TRUE PEIM
> > added to your [FV.FVMAIN_COMPACT].
>
> As I said, that version print is just one of the many things that we wish to
> do in platform PEIM.
OK, but it makes no sense to split something out *now* to be given
actual functionality at some later date. Please leave it out for now,
either completely or moving the printout to some standalone Peim, and
add it in when there is actual content.
At that point, please give it a unique FILE_GUID.
/
Leif
> >
> > /
> > Leif
> >
> > On Mon, Apr 06, 2020 at 14:53:02 +0000, Pankaj Bansal (OSS) wrote:
>
>
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 22/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use default ArmPlatformHelper.S
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (20 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 21/28] Slicon/NXP: Add PlatformPei Lib Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 14:58 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool Pankaj Bansal
` (7 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Default ArmPlatformHelper.S from ArmPlatformPkg is suffecient for
LS1043ARDB ArmPlatformLib. Use the same.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../AArch64/ArmPlatformHelper.S | 60 ++++++++++++-------
.../Library/ArmPlatformLib/ArmPlatformLib.c | 8 ---
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 2 +
3 files changed, 39 insertions(+), 31 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
index dfbf73675a2d..b7c6dbdc2e61 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -1,31 +1,45 @@
-# @file
-#
-# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-# Copyright 2017, 2020 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
#include <AsmMacroIoLibV8.h>
-#include <AutoGen.h>
-
-.text
-.align 2
-
-GCC_ASM_IMPORT(ArmReadMpidr)
-
-ASM_FUNC(ArmPlatformIsPrimaryCore)
- tst x0, #3
- cset x0, eq
- ret
+#include <Library/ArmLib.h>
ASM_FUNC(ArmPlatformPeiBootAction)
-EL1_OR_EL2(x0)
-1:
-2:
ret
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
- MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
- ldrh w0, [x0]
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
ret
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 7f5872a78cfc..1e2e85f87dfe 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -139,11 +139,3 @@ ArmPlatformGetPlatformPpiList (
*PpiList = gPlatformPpiTable;
}
-
-UINTN
-ArmPlatformGetCorePosition (
- IN UINTN MpId
- )
-{
- return 1;
-}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 07ca6b34445f..1faf99b99c54 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -37,3 +37,5 @@ [Ppis]
[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 22/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use default ArmPlatformHelper.S
2020-03-20 14:35 ` [PATCH v2 22/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use default ArmPlatformHelper.S Pankaj Bansal
@ 2020-04-01 14:58 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 14:58 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:37 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Default ArmPlatformHelper.S from ArmPlatformPkg is suffecient for
> LS1043ARDB ArmPlatformLib. Use the same.
The commit message could be clarified to to explicitly state that
ArmPlatformHelper.S is being replaced by the ArmPlatformPkg version at
commit hash f4dfad05dda2c7b29e8105605621f2b413f0af2b.
/
Leif
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../AArch64/ArmPlatformHelper.S | 60 ++++++++++++-------
> .../Library/ArmPlatformLib/ArmPlatformLib.c | 8 ---
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 2 +
> 3 files changed, 39 insertions(+), 31 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> index dfbf73675a2d..b7c6dbdc2e61 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> @@ -1,31 +1,45 @@
> -# @file
> -#
> -# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> -# Copyright 2017, 2020 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> +//
> +// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
>
> #include <AsmMacroIoLibV8.h>
> -#include <AutoGen.h>
> -
> -.text
> -.align 2
> -
> -GCC_ASM_IMPORT(ArmReadMpidr)
> -
> -ASM_FUNC(ArmPlatformIsPrimaryCore)
> - tst x0, #3
> - cset x0, eq
> - ret
> +#include <Library/ArmLib.h>
>
> ASM_FUNC(ArmPlatformPeiBootAction)
> -EL1_OR_EL2(x0)
> -1:
> -2:
> ret
>
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 4) + CoreId
> +ASM_FUNC(ArmPlatformGetCorePosition)
> + and x1, x0, #ARM_CORE_MASK
> + and x0, x0, #ARM_CLUSTER_MASK
> + add x0, x1, x0, LSR #6
> + ret
> +
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> - MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
> - ldrh w0, [x0]
> + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
> + ret
> +
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
> + and x0, x0, x1
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
> + cmp w0, w1
> + mov x0, #1
> + mov x1, #0
> + csel x0, x0, x1, eq
> ret
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index 7f5872a78cfc..1e2e85f87dfe 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -139,11 +139,3 @@ ArmPlatformGetPlatformPpiList (
> *PpiList = gPlatformPpiTable;
> }
>
> -
> -UINTN
> -ArmPlatformGetCorePosition (
> - IN UINTN MpId
> - )
> -{
> - return 1;
> -}
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 07ca6b34445f..1faf99b99c54 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -37,3 +37,5 @@ [Ppis]
>
> [FixedPcd]
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> +
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (21 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 22/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use default ArmPlatformHelper.S Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 18:03 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 24/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit Pankaj Bansal
` (6 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Allocate Pages may allocate more memory than required for
VirtualMemoryTable.
There is no special requirement that VirtualMemoryTable size should be
page size aligned.
Therefore, replace AllocatePages with AllocatePool.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
.../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 1faf99b99c54..c64032f32772 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -25,6 +25,7 @@ [Packages]
[LibraryClasses]
ArmLib
+ DebugLib
SocLib
[Sources.common]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
index f5fa308551aa..f8dd642e3cff 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -43,10 +43,11 @@ ArmPlatformGetVirtualMemoryMap (
ASSERT (VirtualMemoryMap != NULL);
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
- EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
if (VirtualMemoryTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
return;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool
2020-03-20 14:35 ` [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool Pankaj Bansal
@ 2020-04-01 18:03 ` Leif Lindholm
2020-04-06 15:26 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 18:03 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:38 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Allocate Pages may allocate more memory than required for
> VirtualMemoryTable.
> There is no special requirement that VirtualMemoryTable size should be
> page size aligned.
>
> Therefore, replace AllocatePages with AllocatePool.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
I don't object to this as such (although one comment), but what is the
purpose of this change?
My comment is that most other platforms use AllocatePages for this. So
this is diverging from the norm. Secondly, while I don't necessarily
*like* the current design (copied across most ARM platforms), it's
somewhat mitigated by the AllocatePages giving you a minimum of 128
entries before you start overwriting things. I don't know what you'll
overwrite if you do go too far, but you will overwrite it *before* the
ASSERT ever gets evaluated.
/
Leif
> ---
> .../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
> .../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 5 +++--
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 1faf99b99c54..c64032f32772 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -25,6 +25,7 @@ [Packages]
>
> [LibraryClasses]
> ArmLib
> + DebugLib
> SocLib
>
> [Sources.common]
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> index f5fa308551aa..f8dd642e3cff 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> @@ -43,10 +43,11 @@ ArmPlatformGetVirtualMemoryMap (
>
> ASSERT (VirtualMemoryMap != NULL);
>
> - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> - EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> + VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
>
> if (VirtualMemoryTable == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
> return;
> }
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool
2020-04-01 18:03 ` Leif Lindholm
@ 2020-04-06 15:26 ` Pankaj Bansal
2020-04-07 13:08 ` Leif Lindholm
0 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-06 15:26 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Wednesday, April 1, 2020 11:34 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use
> Allocate pool
>
> On Fri, Mar 20, 2020 at 20:05:38 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > Allocate Pages may allocate more memory than required for
> > VirtualMemoryTable.
> > There is no special requirement that VirtualMemoryTable size should be
> > page size aligned.
> >
> > Therefore, replace AllocatePages with AllocatePool.
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> I don't object to this as such (although one comment), but what is the
> purpose of this change?
>
> My comment is that most other platforms use AllocatePages for this. So
> this is diverging from the norm.
I referred ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoLib.c
> Secondly, while I don't necessarily
> *like* the current design (copied across most ARM platforms), it's
> somewhat mitigated by the AllocatePages giving you a minimum of 128
> entries before you start overwriting things. I don't know what you'll
> overwrite if you do go too far, but you will overwrite it *before* the
> ASSERT ever gets evaluated.
>
We can improve this by evaluating ASSERT after each entry like this :
VirtualMemoryTable[Index].PhysicalBase = 0xXXXXXXXX;
VirtualMemoryTable[Index].VirtualBase = 0xXXXXXXXX;
VirtualMemoryTable[Index].Length = 0xXXXXXXXX;
VirtualMemoryTable[Index++].Attributes = 0xXXXXXXXX;
ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> /
> Leif
>
> > ---
> > .../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
> > .../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 5 +++--
> > 2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git
> a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > index 1faf99b99c54..c64032f32772 100644
> > ---
> a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > +++
> b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > @@ -25,6 +25,7 @@ [Packages]
> >
> > [LibraryClasses]
> > ArmLib
> > + DebugLib
> > SocLib
> >
> > [Sources.common]
> > diff --git
> a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> c
> b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> c
> > index f5fa308551aa..f8dd642e3cff 100644
> > ---
> a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> c
> > +++
> b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> c
> > @@ -43,10 +43,11 @@ ArmPlatformGetVirtualMemoryMap (
> >
> > ASSERT (VirtualMemoryMap != NULL);
> >
> > - VirtualMemoryTable =
> (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> > - EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> > + VirtualMemoryTable = AllocatePool (sizeof
> (ARM_MEMORY_REGION_DESCRIPTOR) *
> > + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> >
> > if (VirtualMemoryTable == NULL) {
> > + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n",
> __FUNCTION__));
> > return;
> > }
> >
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool
2020-04-06 15:26 ` Pankaj Bansal
@ 2020-04-07 13:08 ` Leif Lindholm
2020-04-13 6:11 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-04-07 13:08 UTC (permalink / raw)
To: Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton, ard.biesheuvel
+Ard
On Mon, Apr 06, 2020 at 15:26:45 +0000, Pankaj Bansal (OSS) wrote:
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Wednesday, April 1, 2020 11:34 PM
> > To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> > <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> > <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> > Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> > Subject: Re: [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use
> > Allocate pool
> >
> > On Fri, Mar 20, 2020 at 20:05:38 +0530, Pankaj Bansal wrote:
> > > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> > >
> > > Allocate Pages may allocate more memory than required for
> > > VirtualMemoryTable.
> > > There is no special requirement that VirtualMemoryTable size should be
> > > page size aligned.
> > >
> > > Therefore, replace AllocatePages with AllocatePool.
> > >
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > I don't object to this as such (although one comment), but what is the
> > purpose of this change?
> >
> > My comment is that most other platforms use AllocatePages for this. So
> > this is diverging from the norm.
>
> I referred ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoLib.c
Sure. This one was converted to AllocatePool because the QEMU virt
machine is very simple (because it does not emulate much real
hardware) and the port rarely changes.
Ard's what's your opinion - do you think this worth it even for a
platform that has
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
?
Clearly there is still wasteage going on, but it's 16% less bad.
> > Secondly, while I don't necessarily
> > *like* the current design (copied across most ARM platforms), it's
> > somewhat mitigated by the AllocatePages giving you a minimum of 128
> > entries before you start overwriting things. I don't know what you'll
> > overwrite if you do go too far, but you will overwrite it *before* the
> > ASSERT ever gets evaluated.
> >
>
> We can improve this by evaluating ASSERT after each entry like this :
> VirtualMemoryTable[Index].PhysicalBase = 0xXXXXXXXX;
> VirtualMemoryTable[Index].VirtualBase = 0xXXXXXXXX;
> VirtualMemoryTable[Index].Length = 0xXXXXXXXX;
> VirtualMemoryTable[Index++].Attributes = 0xXXXXXXXX;
>
> ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
Whilst functionally preferable, I think that would make for very
tedious reading. I'll let Ard call this one.
/
Leif
> > /
> > Leif
> >
> > > ---
> > > .../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
> > > .../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 5 +++--
> > > 2 files changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > index 1faf99b99c54..c64032f32772 100644
> > > ---
> > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > +++
> > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > @@ -25,6 +25,7 @@ [Packages]
> > >
> > > [LibraryClasses]
> > > ArmLib
> > > + DebugLib
> > > SocLib
> > >
> > > [Sources.common]
> > > diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> > c
> > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> > c
> > > index f5fa308551aa..f8dd642e3cff 100644
> > > ---
> > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> > c
> > > +++
> > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.
> > c
> > > @@ -43,10 +43,11 @@ ArmPlatformGetVirtualMemoryMap (
> > >
> > > ASSERT (VirtualMemoryMap != NULL);
> > >
> > > - VirtualMemoryTable =
> > (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> > > - EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> > MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> > > + VirtualMemoryTable = AllocatePool (sizeof
> > (ARM_MEMORY_REGION_DESCRIPTOR) *
> > > + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> > >
> > > if (VirtualMemoryTable == NULL) {
> > > + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n",
> > __FUNCTION__));
> > > return;
> > > }
> > >
> > > --
> > > 2.17.1
> > >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool
2020-04-07 13:08 ` Leif Lindholm
@ 2020-04-13 6:11 ` Pankaj Bansal
0 siblings, 0 replies; 81+ messages in thread
From: Pankaj Bansal @ 2020-04-13 6:11 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS), 'Ard Biesheuvel'
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton,
ard.biesheuvel@arm.com
Hi Ard,
> > >
> > > I don't object to this as such (although one comment), but what is the
> > > purpose of this change?
> > >
> > > My comment is that most other platforms use AllocatePages for this. So
> > > this is diverging from the norm.
> >
> > I referred ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoLib.c
>
> Sure. This one was converted to AllocatePool because the QEMU virt
> machine is very simple (because it does not emulate much real
> hardware) and the port rarely changes.
>
> Ard's what's your opinion - do you think this worth it even for a
> platform that has
> #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> ?
>
> Clearly there is still wasteage going on, but it's 16% less bad.
>
Can you please reply ? I have to send v3 of these patches.
Please let me know if I need to keep or remove these changes ?
> > > Secondly, while I don't necessarily
> > > *like* the current design (copied across most ARM platforms), it's
> > > somewhat mitigated by the AllocatePages giving you a minimum of 128
> > > entries before you start overwriting things. I don't know what you'll
> > > overwrite if you do go too far, but you will overwrite it *before* the
> > > ASSERT ever gets evaluated.
> > >
> >
> > We can improve this by evaluating ASSERT after each entry like this :
> > VirtualMemoryTable[Index].PhysicalBase = 0xXXXXXXXX;
> > VirtualMemoryTable[Index].VirtualBase = 0xXXXXXXXX;
> > VirtualMemoryTable[Index].Length = 0xXXXXXXXX;
> > VirtualMemoryTable[Index++].Attributes = 0xXXXXXXXX;
> >
> > ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
>
> Whilst functionally preferable, I think that would make for very
> tedious reading. I'll let Ard call this one.
>
This is also a minor improvement that I am proposing.
Please comment if this should be done or not ?
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 24/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (22 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 23/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 19:53 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 25/28] Platform/NXP: Modify FV rules Pankaj Bansal
` (5 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
SocInit can be defined in SocLib.h
No need to make it extern in ArmPlatformLib
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 2 --
Silicon/NXP/Include/Library/SocLib.h | 8 ++++++++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 1e2e85f87dfe..dc81e7ba3101 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -16,8 +16,6 @@
#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/NxpPlatformGetClock.h>
-extern VOID SocInit (VOID);
-
/**
Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
index 749aa230dec5..0ca68602618d 100644
--- a/Silicon/NXP/Include/Library/SocLib.h
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -41,4 +41,12 @@ SocGetClock (
IN VA_LIST Args
);
+/**
+ Function to initialize SoC specific constructs
+ **/
+VOID
+SocInit (
+ VOID
+ );
+
#endif // SOC_LIB_H__
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 24/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit
2020-03-20 14:35 ` [PATCH v2 24/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit Pankaj Bansal
@ 2020-04-01 19:53 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 19:53 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:39 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> SocInit can be defined in SocLib.h
> No need to make it extern in ArmPlatformLib
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
But do please move it as early as possible in the series.
> ---
> .../LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 2 --
> Silicon/NXP/Include/Library/SocLib.h | 8 ++++++++
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index 1e2e85f87dfe..dc81e7ba3101 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -16,8 +16,6 @@
> #include <Ppi/ArmMpCoreInfo.h>
> #include <Ppi/NxpPlatformGetClock.h>
>
> -extern VOID SocInit (VOID);
> -
> /**
> Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
>
> diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
> index 749aa230dec5..0ca68602618d 100644
> --- a/Silicon/NXP/Include/Library/SocLib.h
> +++ b/Silicon/NXP/Include/Library/SocLib.h
> @@ -41,4 +41,12 @@ SocGetClock (
> IN VA_LIST Args
> );
>
> +/**
> + Function to initialize SoC specific constructs
> + **/
> +VOID
> +SocInit (
> + VOID
> + );
> +
> #endif // SOC_LIB_H__
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 25/28] Platform/NXP: Modify FV rules
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (23 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 24/28] NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 19:57 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 26/28] Platform/NXP/LS1043aRdbPkg: Add VarStore Pankaj Bansal
` (4 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Use same FV rules as ArmVirtPkg/ArmVirtRules.fdf.inc
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/FVRules.fdf.inc | 59 +++++++++++++++++++++++-------------
1 file changed, 38 insertions(+), 21 deletions(-)
diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
index c9fba65dae85..63de26abe056 100644
--- a/Platform/NXP/FVRules.fdf.inc
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -1,8 +1,7 @@
-# FvRules.fdf.inc
#
-# Rules for creating FD.
-#
-# Copyright 2017-2019 NXP
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+# Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
+# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -16,40 +15,49 @@
#
################################################################################
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE PEI_CORE = $(NAMED_GUID) FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING ="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
+ FILE PEIM = $(NAMED_GUID) FIXED {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
-[Rule.Common.PEIM.TIANOCOMPRESSED]
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
- }
-
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
-
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
@@ -62,6 +70,8 @@ [Rule.Common.DXE_DRIVER]
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
}
[Rule.Common.DXE_RUNTIME_DRIVER]
@@ -73,7 +83,7 @@ [Rule.Common.DXE_RUNTIME_DRIVER]
[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
- UI STRING ="$(MODULE_NAME)" Optional
+ UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
@@ -91,3 +101,10 @@ [Rule.Common.UEFI_APPLICATION.BINARY]
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ UI STRING="$(MODULE_NAME)" Optional
+ }
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 25/28] Platform/NXP: Modify FV rules
2020-03-20 14:35 ` [PATCH v2 25/28] Platform/NXP: Modify FV rules Pankaj Bansal
@ 2020-04-01 19:57 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 19:57 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
Please make the subject contain information.
/
Leif
On Fri, Mar 20, 2020 at 20:05:40 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Use same FV rules as ArmVirtPkg/ArmVirtRules.fdf.inc
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Platform/NXP/FVRules.fdf.inc | 59 +++++++++++++++++++++++-------------
> 1 file changed, 38 insertions(+), 21 deletions(-)
>
> diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
> index c9fba65dae85..63de26abe056 100644
> --- a/Platform/NXP/FVRules.fdf.inc
> +++ b/Platform/NXP/FVRules.fdf.inc
> @@ -1,8 +1,7 @@
> -# FvRules.fdf.inc
> #
> -# Rules for creating FD.
> -#
> -# Copyright 2017-2019 NXP
> +# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
> +# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -16,40 +15,49 @@
> #
> ################################################################################
>
> +
> +############################################################################
> +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
> +############################################################################
> +#
> +#[Rule.Common.DXE_DRIVER]
> +# FILE DRIVER = $(NAMED_GUID) {
> +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> +# COMPRESS PI_STD {
> +# GUIDED {
> +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> +# UI STRING="$(MODULE_NAME)" Optional
> +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> +# }
> +# }
> +# }
> +#
> +############################################################################
> +
> [Rule.Common.SEC]
> - FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> - TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> }
>
> [Rule.Common.PEI_CORE]
> - FILE PEI_CORE = $(NAMED_GUID) {
> - TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
> + FILE PEI_CORE = $(NAMED_GUID) FIXED {
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING ="$(MODULE_NAME)" Optional
> }
>
> [Rule.Common.PEIM]
> - FILE PEIM = $(NAMED_GUID) {
> + FILE PEIM = $(NAMED_GUID) FIXED {
> PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> }
>
> -[Rule.Common.PEIM.TIANOCOMPRESSED]
> - FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> - GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> - UI STRING="$(MODULE_NAME)" Optional
> - }
> - }
> -
> [Rule.Common.DXE_CORE]
> FILE DXE_CORE = $(NAMED_GUID) {
> PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> }
>
> -
> [Rule.Common.UEFI_DRIVER]
> FILE DRIVER = $(NAMED_GUID) {
> DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> @@ -62,6 +70,8 @@ [Rule.Common.DXE_DRIVER]
> DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> }
>
> [Rule.Common.DXE_RUNTIME_DRIVER]
> @@ -73,7 +83,7 @@ [Rule.Common.DXE_RUNTIME_DRIVER]
>
> [Rule.Common.UEFI_APPLICATION]
> FILE APPLICATION = $(NAMED_GUID) {
> - UI STRING ="$(MODULE_NAME)" Optional
> + UI STRING ="$(MODULE_NAME)" Optional
> PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> }
>
> @@ -91,3 +101,10 @@ [Rule.Common.UEFI_APPLICATION.BINARY]
> UI STRING="$(MODULE_NAME)" Optional
> VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> }
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ACPI |.acpi
> + RAW ASL |.aml
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 26/28] Platform/NXP/LS1043aRdbPkg: Add VarStore
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (24 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 25/28] Platform/NXP: Modify FV rules Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 19:59 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 27/28] Silicon/NXP: move MemoryInitPeiLib as per PEIM structures Pankaj Bansal
` (3 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Add VarStore Fd. This Fd is used to store non volatile variables in
flash.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 3 +-
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 ++++++++++++++++++++
2 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 8d66f36d7407..99fbc87e1200 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -3,7 +3,7 @@
# FLASH layout file for LS1043a board.
#
# Copyright (c) 2016, Freescale Ltd. All rights reserved.
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -49,6 +49,7 @@ [FD.LS1043ARDB_EFI]
FV = FVMAIN_COMPACT
!include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
################################################################################
#
# FV Section
diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 000000000000..391e4ae5eaf8
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1043aRdbNv_EFI]
+BaseAddress = 0x60500000 #The base address of the FLASH device
+Size = 0x000C0000 #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x40000
+NumBlocks = 0x3
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS1043ARDB NVRAM Area
+# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0xC0000
+ 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
+ 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 26/28] Platform/NXP/LS1043aRdbPkg: Add VarStore
2020-03-20 14:35 ` [PATCH v2 26/28] Platform/NXP/LS1043aRdbPkg: Add VarStore Pankaj Bansal
@ 2020-04-01 19:59 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 19:59 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:41 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Add VarStore Fd. This Fd is used to store non volatile variables in
> flash.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 3 +-
> Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 ++++++++++++++++++++
> 2 files changed, 93 insertions(+), 1 deletion(-)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> index 8d66f36d7407..99fbc87e1200 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -3,7 +3,7 @@
> # FLASH layout file for LS1043a board.
> #
> # Copyright (c) 2016, Freescale Ltd. All rights reserved.
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -49,6 +49,7 @@ [FD.LS1043ARDB_EFI]
> FV = FVMAIN_COMPACT
>
> !include Platform/NXP/FVRules.fdf.inc
> +!include VarStore.fdf.inc
> ################################################################################
> #
> # FV Section
> diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> new file mode 100644
> index 000000000000..391e4ae5eaf8
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> @@ -0,0 +1,91 @@
> +## @file
> +# FDF include file with FD definition that defines an empty variable store.
> +#
> +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
> +# Copyright (C) 2014, Red Hat, Inc.
> +# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
> +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> +# Copyright 2017-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[FD.LS1043aRdbNv_EFI]
> +BaseAddress = 0x60500000 #The base address of the FLASH device
> +Size = 0x000C0000 #The size in bytes of the FLASH device
> +ErasePolarity = 1
> +BlockSize = 0x40000
> +NumBlocks = 0x3
> +
> +#
> +# Place NV Storage just above Platform Data Base
> +#
> +DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
> +DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
> +DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
> +DEFINE FTW_WORKING_SIZE = 0x00040000
> +DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
> +DEFINE FTW_SPARE_SIZE = 0x00040000
> +
> +#############################################################################
> +# LS1043ARDB NVRAM Area
> +# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
> +#############################################################################
> +
> +
> +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
> + # { 0xFFF12B8D, 0x7696, 0x4C8B,
> + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: 0xC0000
> + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # Signature "_FVH" # Attributes
> + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
> + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> + 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02,
> + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
> + 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
> + # Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
> + # Signature: gEfiVariableGuid =
> + # { 0xddcf3616, 0x3275, 0x4164,
> + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
> + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xFF, 0x03, 0x00,
> + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64
> + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 27/28] Silicon/NXP: move MemoryInitPeiLib as per PEIM structures
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (25 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 26/28] Platform/NXP/LS1043aRdbPkg: Add VarStore Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-04-01 20:00 ` Leif Lindholm
2020-03-20 14:35 ` [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase Pankaj Bansal
` (2 subsequent siblings)
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
MemoryInitPeiLib would be linked to MemoryInitPeim, when we implement
PEI phase. therefore, move the library to directory of same name.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c | 0
.../{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h | 0
.../{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf | 0
Silicon/NXP/NxpQoriqLs.dsc.inc | 3 +--
4 files changed, 1 insertion(+), 2 deletions(-)
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c (100%)
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h (100%)
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf (100%)
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 5f77f47f0399..b2b10ce28a93 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -102,6 +102,7 @@ [LibraryClasses.common]
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
+ MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@@ -113,7 +114,6 @@ [LibraryClasses.common.SEC]
PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
# 1/123 faster than Stm or Vstm version
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -143,7 +143,6 @@ [LibraryClasses.common.DXE_DRIVER]
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
[LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 27/28] Silicon/NXP: move MemoryInitPeiLib as per PEIM structures
2020-03-20 14:35 ` [PATCH v2 27/28] Silicon/NXP: move MemoryInitPeiLib as per PEIM structures Pankaj Bansal
@ 2020-04-01 20:00 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 20:00 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:42 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> MemoryInitPeiLib would be linked to MemoryInitPeim, when we implement
> PEI phase. therefore, move the library to directory of same name.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> .../{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c | 0
> .../{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h | 0
> .../{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf | 0
> Silicon/NXP/NxpQoriqLs.dsc.inc | 3 +--
> 4 files changed, 1 insertion(+), 2 deletions(-)
> rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c (100%)
> rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h (100%)
> rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf (100%)
>
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> similarity index 100%
> rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
> similarity index 100%
> rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> similarity index 100%
> rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> index 5f77f47f0399..b2b10ce28a93 100644
> --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> @@ -102,6 +102,7 @@ [LibraryClasses.common]
> PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>
> PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> + MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
>
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> @@ -113,7 +114,6 @@ [LibraryClasses.common.SEC]
> PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> - MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
>
> # 1/123 faster than Stm or Vstm version
> BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> @@ -143,7 +143,6 @@ [LibraryClasses.common.DXE_DRIVER]
> DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> - MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
>
> [LibraryClasses.common.UEFI_APPLICATION]
> PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (26 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 27/28] Silicon/NXP: move MemoryInitPeiLib as per PEIM structures Pankaj Bansal
@ 2020-03-20 14:35 ` Pankaj Bansal
2020-03-30 12:18 ` Leif Lindholm
2020-03-26 12:36 ` [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Samer El-Haj-Mahmoud
2020-04-01 20:52 ` Leif Lindholm
29 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-20 14:35 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, devel,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
From: Pankaj Bansal <pankaj.bansal@nxp.com>
Add PEI phase to LS1043aRdb. This is needed becuase we need to have
dynamic PCDs support to be able to reserve memory before reporting
memory to UEFI fimrware.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 ---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 18 +++--
.../MemoryInitPeiLib/MemoryInitPeiLib.c | 77 ++++++++++---------
.../MemoryInitPeiLib/MemoryInitPeiLib.inf | 3 +-
Silicon/NXP/NxpQoriqLs.dsc.inc | 59 ++++++++++----
5 files changed, 99 insertions(+), 67 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index d486c9b36fab..d45fd67c03b5 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -30,15 +30,6 @@ [LibraryClasses.common]
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
[PcdsFixedAtBuild.common]
-
- #
- # LS1043a board Specific PCDs
- # XX (DRAM - Region 1 2GB)
- # (NOR - IFC Region 1 512MB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
-
#
# RTC Pcds
#
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 99fbc87e1200..931d0bb14f9b 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -24,10 +24,10 @@
[FD.LS1043ARDB_EFI]
BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
-Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
ErasePolarity = 1
-BlockSize = 0x1
-NumBlocks = 0xED000
+BlockSize = 0x40000
+NumBlocks = 0x5
################################################################################
#
@@ -44,7 +44,7 @@ [FD.LS1043ARDB_EFI]
# RegionType <FV, DATA, or FILE>
#
################################################################################
-0x00000000|0x000ED000
+0x00000000|0x00140000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
@@ -159,7 +159,15 @@ [FV.FVMAIN_COMPACT]
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
- INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
index 54d026ef1270..7fdf9cb77a6e 100644
--- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
@@ -46,30 +46,12 @@ InitMmu (
}
}
-/*++
-
-Routine Description:
-
-
-
-Arguments:
-
- FileHandle - Handle of the file being invoked.
- PeiServices - Describes the list of possible PEI Services.
-
-Returns:
-
- Status - EFI_SUCCESS if the boot mode could be set
-
---*/
EFI_STATUS
EFIAPI
-MemoryPeim (
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
- IN UINT64 UefiMemorySize
+MemoryInitPeiLibConstructor (
+ VOID
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
ARM_SMC_ARGS ArmSmcArgs;
INT32 Index;
UINTN DramSize;
@@ -82,18 +64,6 @@ MemoryPeim (
UINTN FdTop;
BOOLEAN FoundSystemMem;
- // Get Virtual Memory Map from the Platform Library
- ArmPlatformGetVirtualMemoryMap (&MemoryTable);
-
- //
- // Ensure MemoryTable[0].Length which is size of DRAM has been set
- // by ArmPlatformGetVirtualMemoryMap ()
- //
- ASSERT (MemoryTable[0].Length != 0);
-
- //
- // Now, the permanent memory has been installed, we can call AllocatePages()
- //
ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
@@ -133,8 +103,8 @@ MemoryPeim (
ASSERT (!DramSize);
- FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
- FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+ FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);
// Declare memory regios to system
for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
@@ -178,8 +148,8 @@ MemoryPeim (
);
};
// Mark the memory covering the Firmware Device as boot services data
- BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
- FixedPcdGet32 (PcdFdSize),
+ BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress),
+ PcdGet32 (PcdFdSize),
EfiBootServicesData);
} else {
BuildResourceDescriptorHob (
@@ -199,16 +169,49 @@ MemoryPeim (
Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
if (FdBase >= BaseAddress && FdTop <= Top) {
- Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ Size -= (UINTN)PcdGet32 (PcdFdSize);
}
if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
FoundSystemMem = TRUE;
+ PcdSet64S (PcdSystemMemoryBase, BaseAddress);
+ PcdSet64S (PcdSystemMemorySize, Size);
}
}
ASSERT (FoundSystemMem);
+ return EFI_SUCCESS;
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
// Build Memory Allocation Hob
InitMmu (MemoryTable);
diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
index ad2371115b17..a33f8cd3f743 100644
--- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
@@ -13,7 +13,8 @@ [Defines]
FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
- LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
+ LIBRARY_CLASS = MemoryInitPeiLib|PEIM
+ CONSTRUCTOR = MemoryInitPeiLibConstructor
[Sources]
MemoryInitPeiLib.c
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index b2b10ce28a93..a3f18abb37b1 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -93,6 +93,7 @@ [LibraryClasses.common]
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
@@ -106,20 +107,24 @@ [LibraryClasses.common]
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
- LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
- PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
- MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- # 1/123 faster than Stm or Vstm version
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-
- # Uncomment to turn on GDB stub in SEC.
- #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
[LibraryClasses.common.PEIM]
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -128,14 +133,16 @@ [LibraryClasses.common.PEIM]
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
[LibraryClasses.common.DXE_CORE]
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
@@ -207,6 +214,9 @@ [PcdsDynamicDefault.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0
+
[PcdsDynamicHii.common.DEFAULT]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
@@ -227,6 +237,12 @@ [PcdsFixedAtBuild.common]
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+ ## Base of DRAM
+ ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this space
+ ## for temporary ram
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
!if $(TARGET) == RELEASE
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
@@ -284,13 +300,26 @@ [PcdsFixedAtBuild.common]
################################################################################
[Components.common]
#
- # SEC
+ # PEI Phase modules
#
- ArmPlatformPkg/PrePi/PeiUniCore.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+
+ MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
#
# DXE
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread* Re: [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase
2020-03-20 14:35 ` [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase Pankaj Bansal
@ 2020-03-30 12:18 ` Leif Lindholm
2020-03-31 10:23 ` Pankaj Bansal
0 siblings, 1 reply; 81+ messages in thread
From: Leif Lindholm @ 2020-03-30 12:18 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
On Fri, Mar 20, 2020 at 20:05:43 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> Add PEI phase to LS1043aRdb. This is needed becuase we need to have
> dynamic PCDs support to be able to reserve memory before reporting
> memory to UEFI fimrware.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 18 +++--
> .../MemoryInitPeiLib/MemoryInitPeiLib.c | 77 ++++++++++---------
> .../MemoryInitPeiLib/MemoryInitPeiLib.inf | 3 +-
> Silicon/NXP/NxpQoriqLs.dsc.inc | 59 ++++++++++----
> 5 files changed, 99 insertions(+), 67 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index d486c9b36fab..d45fd67c03b5 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -30,15 +30,6 @@ [LibraryClasses.common]
> RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
>
> [PcdsFixedAtBuild.common]
> -
> - #
> - # LS1043a board Specific PCDs
> - # XX (DRAM - Region 1 2GB)
> - # (NOR - IFC Region 1 512MB)
> - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> - gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
> - gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> -
> #
> # RTC Pcds
> #
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> index 99fbc87e1200..931d0bb14f9b 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -24,10 +24,10 @@
>
> [FD.LS1043ARDB_EFI]
> BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> -Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> ErasePolarity = 1
> -BlockSize = 0x1
> -NumBlocks = 0xED000
> +BlockSize = 0x40000
> +NumBlocks = 0x5
>
> ################################################################################
> #
> @@ -44,7 +44,7 @@ [FD.LS1043ARDB_EFI]
> # RegionType <FV, DATA, or FILE>
> #
> ################################################################################
> -0x00000000|0x000ED000
> +0x00000000|0x00140000
> gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> FV = FVMAIN_COMPACT
>
> @@ -159,7 +159,15 @@ [FV.FVMAIN_COMPACT]
> READ_LOCK_CAP = TRUE
> READ_LOCK_STATUS = TRUE
>
> - INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> + INF MdeModulePkg/Core/Pei/PeiMain.inf
> + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> + INF ArmPkg/Drivers/CpuPei/CpuPei.inf
> + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>
> FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> index 54d026ef1270..7fdf9cb77a6e 100644
> --- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> @@ -46,30 +46,12 @@ InitMmu (
> }
> }
>
> -/*++
> -
> -Routine Description:
> -
> -
> -
> -Arguments:
> -
> - FileHandle - Handle of the file being invoked.
> - PeiServices - Describes the list of possible PEI Services.
> -
> -Returns:
> -
> - Status - EFI_SUCCESS if the boot mode could be set
> -
> ---*/
The above line caused me an unexpected level of excitement this
morning, as my "put back the CRs SMTP strips out" script treated the
--- as a diff separator.
Now, I *have* seen the use of /*++ --*/ elsewhere in the tree, but
this syntax is *not* described in the coding style and should not be
used. While this is a delete statement, there is an addition below
using the same format. The doxygen tags to use are /** and **/.
Fortunately, I can't spot any of these in the rest of the set.
Please send an updated version of this patch - alone if it's the only
patch that needs changes, or with a v4 if such is required.
> EFI_STATUS
> EFIAPI
> -MemoryPeim (
> - IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> - IN UINT64 UefiMemorySize
> +MemoryInitPeiLibConstructor (
> + VOID
> )
> {
> - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> ARM_SMC_ARGS ArmSmcArgs;
> INT32 Index;
> UINTN DramSize;
> @@ -82,18 +64,6 @@ MemoryPeim (
> UINTN FdTop;
> BOOLEAN FoundSystemMem;
>
> - // Get Virtual Memory Map from the Platform Library
> - ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> -
> - //
> - // Ensure MemoryTable[0].Length which is size of DRAM has been set
> - // by ArmPlatformGetVirtualMemoryMap ()
> - //
> - ASSERT (MemoryTable[0].Length != 0);
> -
> - //
> - // Now, the permanent memory has been installed, we can call AllocatePages()
> - //
> ResourceAttributes = (
> EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> @@ -133,8 +103,8 @@ MemoryPeim (
>
> ASSERT (!DramSize);
>
> - FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
> - FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
> + FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
> + FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);
>
> // Declare memory regios to system
> for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
> @@ -178,8 +148,8 @@ MemoryPeim (
> );
> };
> // Mark the memory covering the Firmware Device as boot services data
> - BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
> - FixedPcdGet32 (PcdFdSize),
> + BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress),
> + PcdGet32 (PcdFdSize),
> EfiBootServicesData);
> } else {
> BuildResourceDescriptorHob (
> @@ -199,16 +169,49 @@ MemoryPeim (
> Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
>
> if (FdBase >= BaseAddress && FdTop <= Top) {
> - Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
> + Size -= (UINTN)PcdGet32 (PcdFdSize);
> }
>
> if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
> FoundSystemMem = TRUE;
> + PcdSet64S (PcdSystemMemoryBase, BaseAddress);
> + PcdSet64S (PcdSystemMemorySize, Size);
> }
> }
>
> ASSERT (FoundSystemMem);
>
> + return EFI_SUCCESS;
> +}
> +
> +/*++
Here is the incorrect addition.
(I'm not reviewing the set backwards, this was just the only patch
that wouldn't apply cleanly after conversion.)
/
Leif
> +
> +Routine Description:
> +
> +
> +
> +Arguments:
> +
> + FileHandle - Handle of the file being invoked.
> + PeiServices - Describes the list of possible PEI Services.
> +
> +Returns:
> +
> + Status - EFI_SUCCESS if the boot mode could be set
> +
> +--*/
> +EFI_STATUS
> +EFIAPI
> +MemoryPeim (
> + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> + IN UINT64 UefiMemorySize
> + )
> +{
> + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> +
> + // Get Virtual Memory Map from the Platform Library
> + ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> +
> // Build Memory Allocation Hob
> InitMmu (MemoryTable);
>
> diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> index ad2371115b17..a33f8cd3f743 100644
> --- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> @@ -13,7 +13,8 @@ [Defines]
> FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
> MODULE_TYPE = BASE
> VERSION_STRING = 1.0
> - LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
> + LIBRARY_CLASS = MemoryInitPeiLib|PEIM
> + CONSTRUCTOR = MemoryInitPeiLibConstructor
>
> [Sources]
> MemoryInitPeiLib.c
> diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> index b2b10ce28a93..a3f18abb37b1 100644
> --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> @@ -93,6 +93,7 @@ [LibraryClasses.common]
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
>
> I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
> ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> @@ -106,20 +107,24 @@ [LibraryClasses.common]
>
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> - ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> - LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> - PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> - HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> - PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> - MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> +
> +[LibraryClasses.common.PEI_CORE]
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
> + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
>
> - # 1/123 faster than Stm or Vstm version
> - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> -
> - # Uncomment to turn on GDB stub in SEC.
> - #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
> + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
>
> [LibraryClasses.common.PEIM]
> PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> @@ -128,14 +133,16 @@ [LibraryClasses.common.PEIM]
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
> + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
>
> [LibraryClasses.common.DXE_CORE]
> HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
>
> @@ -207,6 +214,9 @@ [PcdsDynamicDefault.common]
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
>
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0
> +
> [PcdsDynamicHii.common.DEFAULT]
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
>
> @@ -227,6 +237,12 @@ [PcdsFixedAtBuild.common]
> gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
>
> + ## Base of DRAM
> + ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this space
> + ## for temporary ram
> + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> !if $(TARGET) == RELEASE
> gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
> @@ -284,13 +300,26 @@ [PcdsFixedAtBuild.common]
> ################################################################################
> [Components.common]
> #
> - # SEC
> + # PEI Phase modules
> #
> - ArmPlatformPkg/PrePi/PeiUniCore.inf
> + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> +
> + MdeModulePkg/Core/Pei/PeiMain.inf
> MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> <LibraryClasses>
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> }
> + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +
> + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> + ArmPkg/Drivers/CpuPei/CpuPei.inf
> + ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> +
> + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> + }
>
> #
> # DXE
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase
2020-03-30 12:18 ` Leif Lindholm
@ 2020-03-31 10:23 ` Pankaj Bansal
2020-03-31 10:50 ` Leif Lindholm
0 siblings, 1 reply; 81+ messages in thread
From: Pankaj Bansal @ 2020-03-31 10:23 UTC (permalink / raw)
To: Leif Lindholm, Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Monday, March 30, 2020 5:49 PM
> To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
> <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
> Subject: Re: [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase
>
> On Fri, Mar 20, 2020 at 20:05:43 +0530, Pankaj Bansal wrote:
> > From: Pankaj Bansal <pankaj.bansal@nxp.com>
> >
> > Add PEI phase to LS1043aRdb. This is needed becuase we need to have
> > dynamic PCDs support to be able to reserve memory before reporting
> > memory to UEFI fimrware.
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 ---
> > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 18 +++--
> > .../MemoryInitPeiLib/MemoryInitPeiLib.c | 77 ++++++++++---------
> > .../MemoryInitPeiLib/MemoryInitPeiLib.inf | 3 +-
> > Silicon/NXP/NxpQoriqLs.dsc.inc | 59 ++++++++++----
> > 5 files changed, 99 insertions(+), 67 deletions(-)
> >
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > index d486c9b36fab..d45fd67c03b5 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > @@ -30,15 +30,6 @@ [LibraryClasses.common]
> > RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> >
> > [PcdsFixedAtBuild.common]
> > -
> > - #
> > - # LS1043a board Specific PCDs
> > - # XX (DRAM - Region 1 2GB)
> > - # (NOR - IFC Region 1 512MB)
> > - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> > - gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
> > -
> gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> > -
> > #
> > # RTC Pcds
> > #
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > index 99fbc87e1200..931d0bb14f9b 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > @@ -24,10 +24,10 @@
> >
> > [FD.LS1043ARDB_EFI]
> > BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The
> base address of the FLASH Device.
> > -Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in
> bytes of the FLASH Device
> > +Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in
> bytes of the FLASH Device
> > ErasePolarity = 1
> > -BlockSize = 0x1
> > -NumBlocks = 0xED000
> > +BlockSize = 0x40000
> > +NumBlocks = 0x5
> >
> >
> #################################################################
> ###############
> > #
> > @@ -44,7 +44,7 @@ [FD.LS1043ARDB_EFI]
> > # RegionType <FV, DATA, or FILE>
> > #
> >
> #################################################################
> ###############
> > -0x00000000|0x000ED000
> > +0x00000000|0x00140000
> > gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> > FV = FVMAIN_COMPACT
> >
> > @@ -159,7 +159,15 @@ [FV.FVMAIN_COMPACT]
> > READ_LOCK_CAP = TRUE
> > READ_LOCK_STATUS = TRUE
> >
> > - INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> > + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> > + INF MdeModulePkg/Core/Pei/PeiMain.inf
> > + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> > + INF
> MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> > + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> > + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> > + INF ArmPkg/Drivers/CpuPei/CpuPei.inf
> > + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> > + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >
> > FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> > SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> > diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> > index 54d026ef1270..7fdf9cb77a6e 100644
> > --- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> > +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> > @@ -46,30 +46,12 @@ InitMmu (
> > }
> > }
> >
> > -/*++
> > -
> > -Routine Description:
> > -
> > -
> > -
> > -Arguments:
> > -
> > - FileHandle - Handle of the file being invoked.
> > - PeiServices - Describes the list of possible PEI Services.
> > -
> > -Returns:
> > -
> > - Status - EFI_SUCCESS if the boot mode could be set
> > -
> > ---*/
>
> The above line caused me an unexpected level of excitement this
> morning, as my "put back the CRs SMTP strips out" script treated the
> --- as a diff separator.
>
> Now, I *have* seen the use of /*++ --*/ elsewhere in the tree, but
> this syntax is *not* described in the coding style and should not be
> used. While this is a delete statement, there is an addition below
> using the same format. The doxygen tags to use are /** and **/.
>
> Fortunately, I can't spot any of these in the rest of the set.
>
> Please send an updated version of this patch - alone if it's the only
> patch that needs changes, or with a v4 if such is required.
I have not received any comments on other patches so far.
Does that mean all patches are OK (except above)?
If that is the case, then I can send only this patch after update.
If some rework is needed for other patches as well, I will send this patch along with other reworked patches in v3.
>
> > EFI_STATUS
> > EFIAPI
> > -MemoryPeim (
> > - IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> > - IN UINT64 UefiMemorySize
> > +MemoryInitPeiLibConstructor (
> > + VOID
> > )
> > {
> > - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> > ARM_SMC_ARGS ArmSmcArgs;
> > INT32 Index;
> > UINTN DramSize;
> > @@ -82,18 +64,6 @@ MemoryPeim (
> > UINTN FdTop;
> > BOOLEAN FoundSystemMem;
> >
> > - // Get Virtual Memory Map from the Platform Library
> > - ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> > -
> > - //
> > - // Ensure MemoryTable[0].Length which is size of DRAM has been set
> > - // by ArmPlatformGetVirtualMemoryMap ()
> > - //
> > - ASSERT (MemoryTable[0].Length != 0);
> > -
> > - //
> > - // Now, the permanent memory has been installed, we can call
> AllocatePages()
> > - //
> > ResourceAttributes = (
> > EFI_RESOURCE_ATTRIBUTE_PRESENT |
> > EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> > @@ -133,8 +103,8 @@ MemoryPeim (
> >
> > ASSERT (!DramSize);
> >
> > - FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
> > - FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
> > + FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
> > + FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);
> >
> > // Declare memory regios to system
> > for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
> > @@ -178,8 +148,8 @@ MemoryPeim (
> > );
> > };
> > // Mark the memory covering the Firmware Device as boot services data
> > - BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
> > - FixedPcdGet32 (PcdFdSize),
> > + BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress),
> > + PcdGet32 (PcdFdSize),
> > EfiBootServicesData);
> > } else {
> > BuildResourceDescriptorHob (
> > @@ -199,16 +169,49 @@ MemoryPeim (
> > Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
> >
> > if (FdBase >= BaseAddress && FdTop <= Top) {
> > - Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
> > + Size -= (UINTN)PcdGet32 (PcdFdSize);
> > }
> >
> > if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
> > FoundSystemMem = TRUE;
> > + PcdSet64S (PcdSystemMemoryBase, BaseAddress);
> > + PcdSet64S (PcdSystemMemorySize, Size);
> > }
> > }
> >
> > ASSERT (FoundSystemMem);
> >
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/*++
>
> Here is the incorrect addition.
>
> (I'm not reviewing the set backwards, this was just the only patch
> that wouldn't apply cleanly after conversion.)
>
> /
> Leif
>
> > +
> > +Routine Description:
> > +
> > +
> > +
> > +Arguments:
> > +
> > + FileHandle - Handle of the file being invoked.
> > + PeiServices - Describes the list of possible PEI Services.
> > +
> > +Returns:
> > +
> > + Status - EFI_SUCCESS if the boot mode could be set
> > +
> > +--*/
> > +EFI_STATUS
> > +EFIAPI
> > +MemoryPeim (
> > + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> > + IN UINT64 UefiMemorySize
> > + )
> > +{
> > + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> > +
> > + // Get Virtual Memory Map from the Platform Library
> > + ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> > +
> > // Build Memory Allocation Hob
> > InitMmu (MemoryTable);
> >
> > diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> > index ad2371115b17..a33f8cd3f743 100644
> > --- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> > +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> > @@ -13,7 +13,8 @@ [Defines]
> > FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
> > MODULE_TYPE = BASE
> > VERSION_STRING = 1.0
> > - LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
> > + LIBRARY_CLASS = MemoryInitPeiLib|PEIM
> > + CONSTRUCTOR = MemoryInitPeiLibConstructor
> >
> > [Sources]
> > MemoryInitPeiLib.c
> > diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> > index b2b10ce28a93..a3f18abb37b1 100644
> > --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> > +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> > @@ -93,6 +93,7 @@ [LibraryClasses.common]
> >
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> >
> NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl
> eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
> >
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRep
> ortStatusCodeLib.inf
> > +
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
> ressLib.inf
> >
> > I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
> >
> ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetS
> ystemLib.inf
> > @@ -106,20 +107,24 @@ [LibraryClasses.common]
> >
> > [LibraryClasses.common.SEC]
> > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > -
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
> ressLib.inf
> > -
> ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/P
> rePiExtractGuidedSectionLib.inf
> > -
> LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/Lzma
> CustomDecompressLib.inf
> > - PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > - HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> > -
> PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiH
> obListPointerLib.inf
> > -
> MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiM
> emoryAllocationLib.inf
> > +
> DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymb
> olsBaseLib.inf
> > + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> > + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> > +
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServi
> cesTablePointerLib.inf
> > +
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllo
> cationLib.inf
> > +
> > +[LibraryClasses.common.PEI_CORE]
> > + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> > + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> > + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> > +
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllo
> cationLib.inf
> > +
> PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> >
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib
> .inf
> > +
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtrac
> tGuidedSectionLib.inf
> > +
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepo
> rtStatusCodeLib.inf
> > +
> OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/
> OemHookStatusCodeLibNull.inf
> >
> > - # 1/123 faster than Stm or Vstm version
> > - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> > -
> > - # Uncomment to turn on GDB stub in SEC.
> > -
> #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
> > +
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServi
> cesTablePointerLib.inf
> >
> > [LibraryClasses.common.PEIM]
> > PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> > @@ -128,14 +133,16 @@ [LibraryClasses.common.PEIM]
> >
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServi
> cesTablePointerLib.inf
> > HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> >
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllo
> cationLib.inf
> > +
> PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib
> .inf
> > +
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtrac
> tGuidedSectionLib.inf
> >
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepo
> rtStatusCodeLib.inf
> > +
> OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/
> OemHookStatusCodeLibNull.inf
> >
> > [LibraryClasses.common.DXE_CORE]
> > HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> >
> MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/D
> xeCoreMemoryAllocationLib.inf
> >
> DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> >
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtra
> ctGuidedSectionLib.inf
> > -
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
> ressLib.inf
> > DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> >
> PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerf
> ormanceLib.inf
> >
> > @@ -207,6 +214,9 @@ [PcdsDynamicDefault.common]
> >
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> > gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
> >
> > + gArmTokenSpaceGuid.PcdSystemMemoryBase|0
> > + gArmTokenSpaceGuid.PcdSystemMemorySize|0
> > +
> > [PcdsDynamicHii.common.DEFAULT]
> >
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalV
> ariableGuid|0x0|10
> >
> > @@ -227,6 +237,12 @@ [PcdsFixedAtBuild.common]
> > gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> > gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> >
> > + ## Base of DRAM
> > + ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this
> space
> > + ## for temporary ram
> > + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
> > +
> gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> > +
> > !if $(TARGET) == RELEASE
> > gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> > gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
> > @@ -284,13 +300,26 @@ [PcdsFixedAtBuild.common]
> >
> #################################################################
> ###############
> > [Components.common]
> > #
> > - # SEC
> > + # PEI Phase modules
> > #
> > - ArmPlatformPkg/PrePi/PeiUniCore.inf
> > + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> > +
> > + MdeModulePkg/Core/Pei/PeiMain.inf
> > MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> > <LibraryClasses>
> > PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > }
> > + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> > + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> > +
> > + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> > + ArmPkg/Drivers/CpuPei/CpuPei.inf
> > + ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> > +
> > + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> > + <LibraryClasses>
> > +
> NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecom
> pressLib.inf
> > + }
> >
> > #
> > # DXE
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase
2020-03-31 10:23 ` Pankaj Bansal
@ 2020-03-31 10:50 ` Leif Lindholm
0 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-03-31 10:50 UTC (permalink / raw)
To: Pankaj Bansal (OSS)
Cc: Meenakshi Aggarwal, Michael D Kinney, devel@edk2.groups.io,
Varun Sethi, Samer El-Haj-Mahmoud, Jon Nettleton
On Tue, Mar 31, 2020 at 10:23:48 +0000, Pankaj Bansal (OSS) wrote:
> > > -/*++
> > > -
> > > -Routine Description:
> > > -
> > > -
> > > -
> > > -Arguments:
> > > -
> > > - FileHandle - Handle of the file being invoked.
> > > - PeiServices - Describes the list of possible PEI Services.
> > > -
> > > -Returns:
> > > -
> > > - Status - EFI_SUCCESS if the boot mode could be set
> > > -
> > > ---*/
> >
> > The above line caused me an unexpected level of excitement this
> > morning, as my "put back the CRs SMTP strips out" script treated the
> > --- as a diff separator.
> >
> > Now, I *have* seen the use of /*++ --*/ elsewhere in the tree, but
> > this syntax is *not* described in the coding style and should not be
> > used. While this is a delete statement, there is an addition below
> > using the same format. The doxygen tags to use are /** and **/.
> >
> > Fortunately, I can't spot any of these in the rest of the set.
> >
> > Please send an updated version of this patch - alone if it's the only
> > patch that needs changes, or with a v4 if such is required.
>
> I have not received any comments on other patches so far.
> Does that mean all patches are OK (except above)?
> If that is the case, then I can send only this patch after update.
> If some rework is needed for other patches as well, I will send this patch along with other reworked patches in v3.
No, sorry, going through them now.
Had a lot of random interruptions.
I commented on this first because it caused an error when I was
importing the set.
/
Leif
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (27 preceding siblings ...)
2020-03-20 14:35 ` [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase Pankaj Bansal
@ 2020-03-26 12:36 ` Samer El-Haj-Mahmoud
2020-04-01 20:52 ` Leif Lindholm
29 siblings, 0 replies; 81+ messages in thread
From: Samer El-Haj-Mahmoud @ 2020-03-26 12:36 UTC (permalink / raw)
To: Pankaj Bansal, Leif Lindholm,
Meenakshi Aggarwal (meenakshi.aggarwal@nxp.com), Michael D Kinney,
devel@edk2.groups.io, V Sethi (v.sethi@nxp.com),
Jon (jon@solid-run.com), Ard Biesheuvel, Samer El-Haj-Mahmoud
Pankaj,
Please Cc Ard on Arm platform patches
Leif,
Any help in reviewing this big series is appreciated.
Thanks,
--Samer
> -----Original Message-----
> From: Pankaj Bansal <pankaj.bansal@oss.nxp.com>
> Sent: Friday, March 20, 2020 10:35 AM
> To: Leif Lindholm <leif@nuviainc.com>; Meenakshi Aggarwal
> (meenakshi.aggarwal@nxp.com) <meenakshi.aggarwal@nxp.com>; Michael D
> Kinney <michael.d.kinney@intel.com>; devel@edk2.groups.io; V Sethi
> (v.sethi@nxp.com) <v.sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jon (jon@solid-run.com) <jon@solid-run.com>
> Subject: [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform
>
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> This patch series adds PEI phase to NXP LS1043ARDB Platform.
> The previous attempt at this feature can be referred here:
> https://edk2.groups.io/g/devel/message/54006
>
> I have taken care of the review comments received on v1 and have broken
> down the patches further to make review easier.
>
> That is why the number of patches have increased from 19 in v1 to
> 28 in v2.
>
> As such the v1 and v2 patches have diverged, which is why i am not putting
> version specific changes in each indivisual patch.
>
> i have created v2 series in a way that the changes feel more organic and not
> abrupt.
> Only the patch "12/28 remove not needed components" would seem too
> invasive. But, as i have noted in patch description, i am not removing anything
> which is needed for booting LS1043ARDB as of now. i have done this to keep
> the code simple and introduce the components as and when needed for new
> features. This makes code review simpler too.
>
> Pankaj Bansal (28):
> Silicon/NXP: Add I2c lib
> Silicon/NXP: changes to use I2clib in i2cdxe
> Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC
> Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib
> Silicon/Maxim: Add comments in Ds1307RtcLib
> NXP/LS1043aRdb: Move Soc specific components to soc files
> Silicon/NXP: Implement SerialUartClockLib
> Silicon/NXP/LS1043A: Use BaseSerialPortLib16550 as SerialPortLib
> Silicon/NXP: Drop DUartPortLib
> Silicon/NXP: remove print information from Soc lib
> Silicon/NXP: remove not needed components
> Silicon/NXP: Remove unnecessary PCDs
> Silicon/NXP: Move dsc file
> Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg
> Silicon/NXP: Move RAM retrieval from SocLib
> Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs
> Silicon/NXP: Use Clock retrieval PPI in modules
> Silicon/NXP: Add Chassis2 Package
> Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg
> Silicon/NXP/LS1043A: Move SocLib to Soc Package
> Slicon/NXP: Add PlatformPei Lib
> NXP/LS1043aRdbPkg/ArmPlatformLib: Use default ArmPlatformHelper.S
> NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool
> NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit
> Platform/NXP: Modify FV rules
> Platform/NXP/LS1043aRdbPkg: Add VarStore
> Silicon/NXP: move MemoryInitPeiLib as per PEIM structures
> Platform/NXP/LS1043aRdbPkg: Add PEI Phase
>
> Platform/NXP/FVRules.fdf.inc | 59 +-
> .../Drivers/PlatformDxe/PlatformDxe.c | 15 +-
> .../Drivers/PlatformDxe/PlatformDxe.inf | 11 +-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 26 +-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 21 +-
> .../AArch64/ArmPlatformHelper.S | 45 ++
> .../ArmPlatformLib.c | 61 +-
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 42 ++
> .../ArmPlatformLibMem.c} | 84 ++-
> .../Library/PlatformLib/ArmPlatformLib.inf | 55 --
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 31 -
> Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 +++
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 23 +-
> Silicon/NXP/Chassis2/Chassis2.dec | 23 +
> Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 +
> Silicon/NXP/Chassis2/Include/Chassis.h | 34 ++
> .../Chassis2/Library/ChassisLib/ChassisLib.c | 97 +++
> .../Library/ChassisLib/ChassisLib.inf | 34 ++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 533 +---------------
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 50 +-
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 14 +-
> Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 --
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 -----------
> Silicon/NXP/Include/DramInfo.h | 38 --
> Silicon/NXP/Include/Library/ChassisLib.h | 51 ++
> Silicon/NXP/Include/Library/I2cLib.h | 120 ++++
> Silicon/NXP/Include/Library/SocLib.h | 52 ++
> Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 53 ++
> Silicon/NXP/LS1043A/Include/Soc.h | 55 ++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 --
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 51 +-
> Silicon/NXP/LS1043A/Library/SocLib/SocLib.c | 77 +++
> Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf | 27 +
> Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ----
> .../NXP/Library/DUartPortLib/DUartPortLib.c | 364 -----------
> .../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 --
> Silicon/NXP/Library/I2cLib/I2cLib.c | 576 ++++++++++++++++++
> Silicon/NXP/Library/I2cLib/I2cLib.inf | 31 +
> Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 105 ++++
> .../Library/MemoryInitPei/MemoryInitPeiLib.c | 140 -----
> .../MemoryInitPeiLib/MemoryInitPeiLib.c | 224 +++++++
> .../MemoryInitPeiLib/MemoryInitPeiLib.h | 25 +
> .../MemoryInitPeiLib.inf | 10 +-
> .../Library/PlatformPeiLib/PlatformPeiLib.c | 30 +
> .../Library/PlatformPeiLib/PlatformPeiLib.inf | 41 ++
> .../SerialUartClockLib/SerialUartClockLib.c | 22 +
> .../SerialUartClockLib/SerialUartClockLib.inf | 26 +
> Silicon/NXP/Library/SocLib/Chassis.c | 495 ---------------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 -----
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 --
> Silicon/NXP/Library/SocLib/NxpChassis.h | 136 -----
> Silicon/NXP/Library/SocLib/SerDes.c | 268 --------
> Silicon/NXP/NxpQoriqLs.dec | 95 +--
> {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 74 ++-
> 54 files changed, 2181 insertions(+), 3201 deletions(-) create mode 100644
> Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatform
> Helper.S
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib =>
> ArmPlatformLib}/ArmPlatformLib.c (51%) create mode 100644
> Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> rename
> Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c =>
> ArmPlatformLib/ArmPlatformLibMem.c} (51%) delete mode 100644
> Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> delete mode 100644
> Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec create mode 100644
> Silicon/NXP/Chassis2/Chassis2.dsc.inc
> create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
> delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> delete mode 100644 Silicon/NXP/Include/DramInfo.h create mode 100644
> Silicon/NXP/Include/Library/ChassisLib.h
> create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
> create mode 100644 Silicon/NXP/Include/Library/SocLib.h
> create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> create mode 100644 Silicon/NXP/LS1043A/Include/Soc.h delete mode 100644
> Silicon/NXP/LS1043A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
> create mode 100644 Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> delete mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> create mode 100644
> Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> create mode 100644
> Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
> rename Silicon/NXP/Library/{MemoryInitPei =>
> MemoryInitPeiLib}/MemoryInitPeiLib.inf (74%) create mode 100644
> Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> create mode 100644
> Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> create mode 100644
> Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
> delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
> rename {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc (84%)
>
> --
> 2.17.1
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 81+ messages in thread* Re: [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform
2020-03-20 14:35 [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Pankaj Bansal
` (28 preceding siblings ...)
2020-03-26 12:36 ` [PATCH v2 00/28] Add PEI phase to LS1043ARDB Platform Samer El-Haj-Mahmoud
@ 2020-04-01 20:52 ` Leif Lindholm
29 siblings, 0 replies; 81+ messages in thread
From: Leif Lindholm @ 2020-04-01 20:52 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, devel, Varun Sethi,
Samer El-Haj-Mahmoud, Jon Nettleton
Hi Pankaj,
I have now finished my review of individual patches.
Beyond that, the build fails at the patch
10/28 "Silicon/NXP: remove print information from Soc lib" with the error
edk2-platforms/Silicon/NXP/Library/SocLib/Chassis.c:209:1: error:
‘CpuMaskNext’ defined but not used [-Werror=unused-function]
The function is deleted in the subsequent patch,
11/28 "Silicon/NXP: remove not needed components".
Please move that deletion to the now failing patch.
Regards,
Leif
On Fri, Mar 20, 2020 at 20:05:15 +0530, Pankaj Bansal wrote:
> From: Pankaj Bansal <pankaj.bansal@nxp.com>
>
> This patch series adds PEI phase to NXP LS1043ARDB Platform.
> The previous attempt at this feature can be referred here:
> https://edk2.groups.io/g/devel/message/54006
>
> I have taken care of the review comments received on v1 and have
> broken down the patches further to make review easier.
>
> That is why the number of patches have increased from 19 in v1 to
> 28 in v2.
>
> As such the v1 and v2 patches have diverged, which is why i am not
> putting version specific changes in each indivisual patch.
>
> i have created v2 series in a way that the changes feel more organic
> and not abrupt.
> Only the patch "12/28 remove not needed components" would seem too
> invasive. But, as i have noted in patch description, i am not removing
> anything which is needed for booting LS1043ARDB as of now. i have done
> this to keep the code simple and introduce the components as and when
> needed for new features. This makes code review simpler too.
>
> Pankaj Bansal (28):
> Silicon/NXP: Add I2c lib
> Silicon/NXP: changes to use I2clib in i2cdxe
> Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC
> Silicon/Maxim: Fix bug in RtcWrite in Ds1307RtcLib
> Silicon/Maxim: Add comments in Ds1307RtcLib
> NXP/LS1043aRdb: Move Soc specific components to soc files
> Silicon/NXP: Implement SerialUartClockLib
> Silicon/NXP/LS1043A: Use BaseSerialPortLib16550 as SerialPortLib
> Silicon/NXP: Drop DUartPortLib
> Silicon/NXP: remove print information from Soc lib
> Silicon/NXP: remove not needed components
> Silicon/NXP: Remove unnecessary PCDs
> Silicon/NXP: Move dsc file
> Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg
> Silicon/NXP: Move RAM retrieval from SocLib
> Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs
> Silicon/NXP: Use Clock retrieval PPI in modules
> Silicon/NXP: Add Chassis2 Package
> Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg
> Silicon/NXP/LS1043A: Move SocLib to Soc Package
> Slicon/NXP: Add PlatformPei Lib
> NXP/LS1043aRdbPkg/ArmPlatformLib: Use default ArmPlatformHelper.S
> NXP/LS1043aRdbPkg/ArmPlatformLib: Use Allocate pool
> NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit
> Platform/NXP: Modify FV rules
> Platform/NXP/LS1043aRdbPkg: Add VarStore
> Silicon/NXP: move MemoryInitPeiLib as per PEIM structures
> Platform/NXP/LS1043aRdbPkg: Add PEI Phase
>
> Platform/NXP/FVRules.fdf.inc | 59 +-
> .../Drivers/PlatformDxe/PlatformDxe.c | 15 +-
> .../Drivers/PlatformDxe/PlatformDxe.inf | 11 +-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 26 +-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 21 +-
> .../AArch64/ArmPlatformHelper.S | 45 ++
> .../ArmPlatformLib.c | 61 +-
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 42 ++
> .../ArmPlatformLibMem.c} | 84 ++-
> .../Library/PlatformLib/ArmPlatformLib.inf | 55 --
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 31 -
> Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 +++
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 23 +-
> Silicon/NXP/Chassis2/Chassis2.dec | 23 +
> Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 +
> Silicon/NXP/Chassis2/Include/Chassis.h | 34 ++
> .../Chassis2/Library/ChassisLib/ChassisLib.c | 97 +++
> .../Library/ChassisLib/ChassisLib.inf | 34 ++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 533 +---------------
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 50 +-
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 14 +-
> Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 --
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 -----------
> Silicon/NXP/Include/DramInfo.h | 38 --
> Silicon/NXP/Include/Library/ChassisLib.h | 51 ++
> Silicon/NXP/Include/Library/I2cLib.h | 120 ++++
> Silicon/NXP/Include/Library/SocLib.h | 52 ++
> Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 53 ++
> Silicon/NXP/LS1043A/Include/Soc.h | 55 ++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 --
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 51 +-
> Silicon/NXP/LS1043A/Library/SocLib/SocLib.c | 77 +++
> Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf | 27 +
> Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ----
> .../NXP/Library/DUartPortLib/DUartPortLib.c | 364 -----------
> .../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 --
> Silicon/NXP/Library/I2cLib/I2cLib.c | 576 ++++++++++++++++++
> Silicon/NXP/Library/I2cLib/I2cLib.inf | 31 +
> Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 105 ++++
> .../Library/MemoryInitPei/MemoryInitPeiLib.c | 140 -----
> .../MemoryInitPeiLib/MemoryInitPeiLib.c | 224 +++++++
> .../MemoryInitPeiLib/MemoryInitPeiLib.h | 25 +
> .../MemoryInitPeiLib.inf | 10 +-
> .../Library/PlatformPeiLib/PlatformPeiLib.c | 30 +
> .../Library/PlatformPeiLib/PlatformPeiLib.inf | 41 ++
> .../SerialUartClockLib/SerialUartClockLib.c | 22 +
> .../SerialUartClockLib/SerialUartClockLib.inf | 26 +
> Silicon/NXP/Library/SocLib/Chassis.c | 495 ---------------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 -----
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 --
> Silicon/NXP/Library/SocLib/NxpChassis.h | 136 -----
> Silicon/NXP/Library/SocLib/SerDes.c | 268 --------
> Silicon/NXP/NxpQoriqLs.dec | 95 +--
> {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 74 ++-
> 54 files changed, 2181 insertions(+), 3201 deletions(-)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c (51%)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} (51%)
> delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
> create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
> create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
> delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> delete mode 100644 Silicon/NXP/Include/DramInfo.h
> create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h
> create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
> create mode 100644 Silicon/NXP/Include/Library/SocLib.h
> create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> create mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
> delete mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
> create mode 100644 Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> delete mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> create mode 100644 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> create mode 100644 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
> rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf (74%)
> create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> create mode 100644 Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.c
> create mode 100644 Silicon/NXP/Library/SerialUartClockLib/SerialUartClockLib.inf
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
> delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
> rename {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc (84%)
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 81+ messages in thread