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[109.210.65.247]) by smtp.gmail.com with ESMTPSA id a13sm4756386wrt.64.2020.03.28.03.43.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Mar 2020 03:43:27 -0700 (PDT) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH 2/5] ArmPkg/CpuDxe: move PageAttributeToGcdAttribute() out of ArmMmuLib Date: Sat, 28 Mar 2020 11:43:18 +0100 Message-Id: <20200328104321.8668-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200328104321.8668-1-ard.biesheuvel@linaro.org> References: <20200328104321.8668-1-ard.biesheuvel@linaro.org> The routine PageAttributeToGcdAttribute() is exported by ArmMmuLib but only ever used in the implementation of CpuDxe. So let's move the function there and make it STATIC. Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 46 ++++++++++++++++++++ ArmPkg/Include/Chipset/AArch64.h | 5 --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 45 ------------------- 3 files changed, 46 insertions(+), 50 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c index 24eb1c4221e3..29fa08f9e07c 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -30,6 +30,52 @@ GetRootTranslationTableInfo ( *RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL; } +STATIC +UINT64 +PageAttributeToGcdAttribute ( + IN UINT64 PageAttributes + ) +{ + UINT64 GcdAttributes; + + switch (PageAttributes & TT_ATTR_INDX_MASK) { + case TT_ATTR_INDX_DEVICE_MEMORY: + GcdAttributes = EFI_MEMORY_UC; + break; + case TT_ATTR_INDX_MEMORY_NON_CACHEABLE: + GcdAttributes = EFI_MEMORY_WC; + break; + case TT_ATTR_INDX_MEMORY_WRITE_THROUGH: + GcdAttributes = EFI_MEMORY_WT; + break; + case TT_ATTR_INDX_MEMORY_WRITE_BACK: + GcdAttributes = EFI_MEMORY_WB; + break; + default: + DEBUG ((DEBUG_ERROR, + "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", + PageAttributes)); + ASSERT (0); + // The Global Coherency Domain (GCD) value is defined as a bit set. + // Returning 0 means no attribute has been set. + GcdAttributes = 0; + } + + // Determine protection attributes + if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || + ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) { + // Read only cases map to write-protect + GcdAttributes |= EFI_MEMORY_RO; + } + + // Process eXecute Never attribute + if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0) { + GcdAttributes |= EFI_MEMORY_XP; + } + + return GcdAttributes; +} + STATIC UINT64 GetFirstPageAttribute ( diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index e3d877207b38..0ade5cce91c3 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -219,11 +219,6 @@ ArmReadCurrentEL ( VOID ); -UINT64 -PageAttributeToGcdAttribute ( - IN UINT64 PageAttributes - ); - UINTN ArmWriteCptr ( IN UINT64 Cptr diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 3b10ef58f0a2..d16e847218b7 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -57,51 +57,6 @@ ArmMemoryAttributeToPageAttribute ( } } -UINT64 -PageAttributeToGcdAttribute ( - IN UINT64 PageAttributes - ) -{ - UINT64 GcdAttributes; - - switch (PageAttributes & TT_ATTR_INDX_MASK) { - case TT_ATTR_INDX_DEVICE_MEMORY: - GcdAttributes = EFI_MEMORY_UC; - break; - case TT_ATTR_INDX_MEMORY_NON_CACHEABLE: - GcdAttributes = EFI_MEMORY_WC; - break; - case TT_ATTR_INDX_MEMORY_WRITE_THROUGH: - GcdAttributes = EFI_MEMORY_WT; - break; - case TT_ATTR_INDX_MEMORY_WRITE_BACK: - GcdAttributes = EFI_MEMORY_WB; - break; - default: - DEBUG ((DEBUG_ERROR, - "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", - PageAttributes)); - ASSERT (0); - // The Global Coherency Domain (GCD) value is defined as a bit set. - // Returning 0 means no attribute has been set. - GcdAttributes = 0; - } - - // Determine protection attributes - if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || - ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) { - // Read only cases map to write-protect - GcdAttributes |= EFI_MEMORY_RO; - } - - // Process eXecute Never attribute - if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0) { - GcdAttributes |= EFI_MEMORY_XP; - } - - return GcdAttributes; -} - #define MIN_T0SZ 16 #define BITS_PER_LEVEL 9 -- 2.17.1