From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by mx.groups.io with SMTP id smtpd.web10.8848.1586173727091851983 for ; Mon, 06 Apr 2020 04:48:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=qT9TcRSA; spf=pass (domain: nuviainc.com, ip: 209.85.221.65, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f65.google.com with SMTP id o17so2789475wrv.5 for ; Mon, 06 Apr 2020 04:48:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=zcRQStj0g+qu8wQ8wRk/G2yvKRyyBcm6pj+kikDcXnU=; b=qT9TcRSA4e/VcoL3YVZFx4ROegvVIUMstoY3mSLuklczJrnh9Iyguj55xKjh052H+i cRhZeoZ45dVPfw8qD0J93Q0pk5XxOs5yeUBN6DId6R8MejR8g7nCWQyobVwnQ/bN07Ky kqwU62PvEJ4GUYv+25AKXbcVOMhQD7Ba3j24FzpMmEr4GY7ppaatSU7t7ERx6Z14fpID xFycVa7fV5u7Juc3E8AeUHgJosKFpS59dSEq11pIBo8IcAA4SAbo/wUDxzhj3CCcToTJ YwG2Cmw5huIl5AxQ66qeIa1pkZQCby383+TrXFODlA0IgTC+DuIX5MhVCM+ZDZHN2ViC qtpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=zcRQStj0g+qu8wQ8wRk/G2yvKRyyBcm6pj+kikDcXnU=; b=IPEPneSb2/fNPP6d8ITi1Hd7kJLcueB87bPvkUwoPEgyH468baxjQCTX0EI9ns0+3t 9U0iC6/S8L28gBYibosgQOgR7ZVGwRPcIggtNOnVikfFl8ciM8uw0y8f+njBGSuHJoQD CkXh0ANa/FfgOeMVkKH8t3MhWQalN1M0vEzG2vdIoJtB28C3a/Ci3i2ycdt9V4TuAve3 Dz/1Ie+AihUHRj1f9XjhgDiq+iUWIe27W2JdKda2IagSBEDdoVBG5H18A/P145VBljl1 NOe6ZNwNu4D3VKgzWxOy5QfcJa+Ekj9kXdYX0WGnyF4bCiJnkzfCs9Z7SIKjkBZ9Fo2K yMKw== X-Gm-Message-State: AGi0Pua5iHi56Pck9FG06P4rShBio7Q6qitL5qQTO0dR+NU9myjK9cSw 6aut9domSU3DPznOAjl8S5k2Pg== X-Google-Smtp-Source: APiQypJa/cWFfRGpXh0s1hoGmo6KcA3S84geFrzftCXVNellN5WYQU/7KtjQPfR4OyYTDdYTC6f7zg== X-Received: by 2002:a5d:50d1:: with SMTP id f17mr24874697wrt.150.1586173725558; Mon, 06 Apr 2020 04:48:45 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id 106sm15894328wrc.46.2020.04.06.04.48.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Apr 2020 04:48:45 -0700 (PDT) Date: Mon, 6 Apr 2020 12:48:43 +0100 From: "Leif Lindholm" To: "Pankaj Bansal (OSS)" Cc: Meenakshi Aggarwal , Michael D Kinney , "devel@edk2.groups.io" , Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton Subject: Re: [PATCH v2 15/28] Silicon/NXP: Move RAM retrieval from SocLib Message-ID: <20200406114843.GE14075@vanye> References: <20200320143543.18615-1-pankaj.bansal@oss.nxp.com> <20200320143543.18615-16-pankaj.bansal@oss.nxp.com> <20200401124255.GW7468@vanye> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Apr 06, 2020 at 10:08:43 +0000, Pankaj Bansal (OSS) wrote: > > > > + > > > + FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress); > > > + FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize); > > > + > > > + // Declare memory regios to system > > > > regions > > OK > > > > > > + for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) { > > > > I guess what confuses me about this loop is the combination of: > > - Iterating over the DRAM regions backwards (optimization?) > > - Not terminating the iteration once all of the Fd region has been > > covered (the opposite of optimization). > > > > Could something be done about that? > > > > The DRAM region info is sorted based on the RAM address is SOC memory map. > i.e. region0 is at lower address, as compared to region1. > The goal to start from last region is to find the topmost RAM region that can contain UEFI DXE region i.e. PcdSystemMemoryUefiRegionSize. > In the upcoming patches I would update the PcdSystemMemoryBase dynamically from that region. > If UEFI were to allocate any reserved or runtime region, it would be allocated from topmost RAM region. > This ensures that maximum amount of lower RAM (32 bit addresses) are left for OS to allocate to devices that can only > work with 32bit physical addresses. E.g. legacy devices that need to DMA to 32bit addresses. OK, that's (sadly) a good reason. Can it be explained in a comment? / Leif