From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by mx.groups.io with SMTP id smtpd.web12.9200.1586174977368973730 for ; Mon, 06 Apr 2020 05:09:37 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=zQ9NBtSb; spf=pass (domain: nuviainc.com, ip: 209.85.128.68, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f68.google.com with SMTP id h2so6408858wmb.4 for ; Mon, 06 Apr 2020 05:09:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=I1QAyotTA/fy1FYsjsgyAqnWDmCjaUdKmk2sEkd8lkU=; b=zQ9NBtSbPa79NfsSdIS+KvsseNubtLSCu+ND9RVZuSVE3zvX2BiBfYB5oXaqyXWhTN Q20juaRNeUJj1EoAvtlr3cUQQxCa4BA6qtnjNIU6D1H1mS3A/jETDmeUsrrMem+itPPl XtdlWsmad3c+Agz51XCnQVAcQrL6SbIqKakQUostIyE0fPQSXRKmQix1CTO6zY3wcd8M ePnvK8NrptvcydIRqOb+endRNZiiNq0w3qYjab1eLqNAcUwULlGf5Fz1lik6iYZRnjXh gzpVEAm6KBrKHjk7OkOwdAwLR6JceXgJtou5ZPlaf9gWEFilMRxODUDHl/zKaais1jh4 +NQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=I1QAyotTA/fy1FYsjsgyAqnWDmCjaUdKmk2sEkd8lkU=; b=fOlEVVYYecX0UgONp7FE2hB9d4+YrVOqZfjutzdwM0ggLjeydpebypQry3cKs1C76Z x9SM6QBVr80F9ysCDZlYQJUczqz2UKziLFJ/WdY1ZexKhFEcWbpXGHdNtJARx1/GhbL0 KvkTzVrjC8K+RJQiB52SoTUsBP6xat7nDYsf/LNUnwpZGrU1gQTmFrmuQ5quHpjcKfTW sHZvdIkRdnFaaGUuHDu91Ge02lAf1Ey9tCDfRT0TaYCXkqzJ7ZHrH2dM+wKOGlp1Ymb9 hMJ2I1p882aEF2pFEJAcbpvNR3ixa4jRrV2ORfakSNykvLTetEK1Ts1WDXvXccP79uGM z1QQ== X-Gm-Message-State: AGi0PuYZf3Sqm57WZg371GfJUohux6qMf7w0GQ/9EEmMBAg9aDdQO+J+ Gzk3+64a9uqKR0EGWyNQ/mgr8w== X-Google-Smtp-Source: APiQypLU1yJkaCrXcS7xSU90WceWUg+f/dFomEnxAg5j6w2oGkudiUA4SUES2rrZRvJgKFAKXL5rFw== X-Received: by 2002:a7b:c401:: with SMTP id k1mr21778425wmi.152.1586174975745; Mon, 06 Apr 2020 05:09:35 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id p10sm25936467wrm.6.2020.04.06.05.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Apr 2020 05:09:35 -0700 (PDT) Date: Mon, 6 Apr 2020 13:09:32 +0100 From: "Leif Lindholm" To: Ard Biesheuvel Cc: devel@edk2.groups.io Subject: Re: [PATCH 1/1] ArmPkg: rename misleading local #define in CpuDxe Message-ID: <20200406120932.GG14075@vanye> References: <20200403114847.15760-1-leif@nuviainc.com> <4ac2f00a-f51c-073d-de13-86e9d4cee565@arm.com> MIME-Version: 1.0 In-Reply-To: <4ac2f00a-f51c-073d-de13-86e9d4cee565@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Apr 06, 2020 at 13:55:44 +0200, Ard Biesheuvel wrote: > On 4/3/20 1:48 PM, Leif Lindholm wrote: > > The local #define TT_ATTR_INDX_INVALID is used as a local error code > > in the AArch64 implementation, but is misleadingly named to match the > > definitions in ArmPkg/Include/Chipset/AArch64Mmu.h. > > > > Rename it INVALID_ENTRY to reduce confusion and improve readability. > > > > Signed-off-by: Leif Lindholm > > Reviewed-by: Ard Biesheuvel Thanks! Pushed as ee026ea78b0e. > > --- > > ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 14 +++++++------- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > > index 29fa08f9e07c..fca2d4f7638a 100644 > > --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > > +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > > @@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #include > > #include "CpuDxe.h" > > -#define TT_ATTR_INDX_INVALID ((UINT32)~0) > > +#define INVALID_ENTRY ((UINT32)~0) > > #define MIN_T0SZ 16 > > #define BITS_PER_LEVEL 9 > > @@ -98,7 +98,7 @@ GetFirstPageAttribute ( > > { > > return FirstEntry & TT_ATTR_INDX_MASK; > > } else { > > - return TT_ATTR_INDX_INVALID; > > + return INVALID_ENTRY; > > } > > } > > @@ -139,8 +139,8 @@ GetNextEntryAttribute ( > > // If Entry is a Table Descriptor type entry then go through the sub-level table > > if ((EntryType == TT_TYPE_BLOCK_ENTRY) || > > ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) { > > - if ((*PrevEntryAttribute == TT_ATTR_INDX_INVALID) || (EntryAttribute != *PrevEntryAttribute)) { > > - if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) { > > + if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) { > > + if (*PrevEntryAttribute != INVALID_ENTRY) { > > // Update GCD with the last region > > SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, > > *StartGcdRegion, > > @@ -164,7 +164,7 @@ GetNextEntryAttribute ( > > (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))), > > PrevEntryAttribute, StartGcdRegion); > > } else { > > - if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) { > > + if (*PrevEntryAttribute != INVALID_ENTRY) { > > // Update GCD with the last region > > SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, > > *StartGcdRegion, > > @@ -173,7 +173,7 @@ GetNextEntryAttribute ( > > // Start of the new region > > *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); > > - *PrevEntryAttribute = TT_ATTR_INDX_INVALID; > > + *PrevEntryAttribute = INVALID_ENTRY; > > } > > } > > } > > @@ -238,7 +238,7 @@ SyncCacheConfig ( > > &PageAttribute, &BaseAddressGcdRegion); > > // Update GCD with the last region if valid > > - if (PageAttribute != TT_ATTR_INDX_INVALID) { > > + if (PageAttribute != INVALID_ENTRY) { > > SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, > > BaseAddressGcdRegion, > > EndAddressGcdRegion - BaseAddressGcdRegion, > > >