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From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com
Subject: [PATCH v1 0/3] Enable RISC-V architecture for RISC-V EDK2 CI.
Date: Fri, 10 Apr 2020 15:13:18 +0800	[thread overview]
Message-ID: <20200410071321.7159-1-abner.chang@hpe.com> (raw)

Enable EDK2 CI test on RISC-V architecture.

BZ for entire RISC-V edk2 port,
https://bugzilla.tianocore.org/show_bug.cgi?id=2672

These commits are verified by below PR,
https://github.com/tianocore/edk2/pull/512

Abner Chang (3):
  BaseTools: Enable RISC-V architecture for RISC-V EDK2 CI.
  .azurepipelines: Add RISC-V architecture on RISC-V EDK2 CI.
  .pytool: Add RISC-V architecture on RISC-V EDK2 CI.

 .azurepipelines/Ubuntu-GCC5.yml               |  3 +-
 .pytool/CISettings.py                         |  9 ++++-
 .../Bin/gcc_riscv64_unknown_ext_dep.yaml      | 22 +++++++++++
 .../LinuxGcc5ToolChain/LinuxGcc5ToolChain.py  | 38 +++++++++++++++++++
 4 files changed, 69 insertions(+), 3 deletions(-)
 create mode 100644 BaseTools/Bin/gcc_riscv64_unknown_ext_dep.yaml

-- 
2.25.0


             reply	other threads:[~2020-04-10  7:51 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-10  7:13 Abner Chang [this message]
2020-04-10  7:13 ` [PATCH v1 2/3] .azurepipelines: Enable RISC-V architecture for RISC-V EDK2 CI Abner Chang
2020-04-10  7:13 ` [PATCH v1 3/3] .pytool: " Abner Chang
2020-04-25  3:36 ` [edk2-devel] [PATCH v1 0/3] " Sean
2020-04-26 11:36   ` Abner Chang

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