From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.4992.1586505075221452739 for ; Fri, 10 Apr 2020 00:51:15 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=036964ab29=abner.chang@hpe.com) Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7mVsa003137 for ; Fri, 10 Apr 2020 07:51:14 GMT Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0a-002e3701.pphosted.com with ESMTP id 30agp0s86n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 10 Apr 2020 07:51:14 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 1FEEF62 for ; Fri, 10 Apr 2020 07:51:14 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 603F749; Fri, 10 Apr 2020 07:51:13 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH v1 0/3] Enable RISC-V architecture for RISC-V EDK2 CI. Date: Fri, 10 Apr 2020 15:13:18 +0800 Message-Id: <20200410071321.7159-1-abner.chang@hpe.com> X-Mailer: git-send-email 2.25.0 X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-10_02:2020-04-07,2020-04-10 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 spamscore=0 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 mlxlogscore=757 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004100065 Content-Transfer-Encoding: quoted-printable Enable EDK2 CI test on RISC-V architecture.=0D =0D BZ for entire RISC-V edk2 port,=0D https://bugzilla.tianocore.org/show_bug.cgi?id=3D2672=0D =0D These commits are verified by below PR,=0D https://github.com/tianocore/edk2/pull/512=0D =0D Abner Chang (3):=0D BaseTools: Enable RISC-V architecture for RISC-V EDK2 CI.=0D .azurepipelines: Add RISC-V architecture on RISC-V EDK2 CI.=0D .pytool: Add RISC-V architecture on RISC-V EDK2 CI.=0D =0D .azurepipelines/Ubuntu-GCC5.yml | 3 +-=0D .pytool/CISettings.py | 9 ++++-=0D .../Bin/gcc_riscv64_unknown_ext_dep.yaml | 22 +++++++++++=0D .../LinuxGcc5ToolChain/LinuxGcc5ToolChain.py | 38 +++++++++++++++++++=0D 4 files changed, 69 insertions(+), 3 deletions(-)=0D create mode 100644 BaseTools/Bin/gcc_riscv64_unknown_ext_dep.yaml=0D =0D -- =0D 2.25.0=0D =0D