From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com
Subject: [PATCH v1 0/9] MdePkg changes for RISC-V edk2 port
Date: Fri, 10 Apr 2020 15:21:03 +0800 [thread overview]
Message-ID: <20200410072112.7310-1-abner.chang@hpe.com> (raw)
MdePkg modules and definitionsfor RISC-V architecture on edk2.
BZ for entire RISC-V edk2 port,
https://bugzilla.tianocore.org/show_bug.cgi?id=2672
These commits are verified by below PR,
https://github.com/tianocore/edk2/pull/512
Abner Chang (9):
MdePkg: RISC-V RV64 binding in MdePkg
MdePkg/Include: RISC-V definitions.
MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance
implementation.
MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=>IoLibNoIo.c
MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
MdePkg/BaseSynchronizationLib: RISC-V cache related code.
MdePkg/BaseSafeIntLib: Add RISCV64 arch for BaseSafeIntLib.
MdePkg/MdePkg.dec | 5 +-
MdePkg/MdePkg.dsc | 3 +-
.../BaseCacheMaintenanceLib.inf | 4 +
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +-
.../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 12 +-
MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
.../Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
.../Library/BaseSafeIntLib/BaseSafeIntLib.inf | 6 +-
.../BaseSynchronizationLib.inf | 5 +
MdePkg/Include/IndustryStandard/PeImage.h | 12 +
MdePkg/Include/Library/BaseLib.h | 26 ++
MdePkg/Include/Protocol/DebugSupport.h | 55 ++++
MdePkg/Include/Protocol/PxeBaseCode.h | 4 +
MdePkg/Include/RiscV64/ProcessorBind.h | 173 ++++++++++++
MdePkg/Include/Uefi/UefiBaseType.h | 13 +
MdePkg/Include/Uefi/UefiSpec.h | 5 +
.../BasePeCoffLib/BasePeCoffLibInternals.h | 9 +
.../BaseCacheMaintenanceLib/RiscVCache.c | 250 ++++++++++++++++++
.../{IoLibArm.c => IoLibNoIo.c} | 4 +-
.../Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 ++
MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 ++
.../BaseLib/RiscV64/DisableInterrupts.c | 24 ++
.../BaseLib/RiscV64/EnableInterrupts.c | 25 ++
.../BaseLib/RiscV64/GetInterruptState.c | 35 +++
.../BaseLib/RiscV64/InternalSwitchStack.c | 55 ++++
MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
.../BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 133 ++++++++++
MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +-
MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 ++
MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 ++
.../BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +
.../Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +
.../Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++
.../BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 ++++
.../Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
.../RiscV64/SynchronizationAsm.S | 78 ++++++
37 files changed, 1204 insertions(+), 14 deletions(-)
create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h
create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
rename MdePkg/Library/BaseIoLibIntrinsic/{IoLibArm.c => IoLibNoIo.c} (94%)
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
--
2.25.0
next reply other threads:[~2020-04-10 7:59 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-10 7:21 Abner Chang [this message]
2020-04-10 7:21 ` [PATCH v1 1/9] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
2020-04-21 6:30 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 2/9] MdePkg/Include: RISC-V definitions Abner Chang
2020-04-21 6:32 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 3/9] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2020-04-21 6:32 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 4/9] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2020-04-21 6:32 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 5/9] MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=>IoLibNoIo.c Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
2020-04-21 8:21 ` Abner Chang
2020-04-10 7:21 ` [PATCH v1 6/9] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 7/9] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
2020-04-10 7:21 ` [PATCH v1 9/9] MdePkg/BaseSafeIntLib: Add RISCV64 arch for BaseSafeIntLib Abner Chang
2020-04-21 6:36 ` [edk2-devel] " Zhiguang Liu
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