From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.5089.1586505546184880322 for ; Fri, 10 Apr 2020 00:59:06 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=036964ab29=abner.chang@hpe.com) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7uq0t000491 for ; Fri, 10 Apr 2020 07:59:05 GMT Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 3091pkm0qq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 10 Apr 2020 07:59:05 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 142A1A1 for ; Fri, 10 Apr 2020 07:59:05 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 6197636; Fri, 10 Apr 2020 07:59:04 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH v1 0/9] MdePkg changes for RISC-V edk2 port Date: Fri, 10 Apr 2020 15:21:03 +0800 Message-Id: <20200410072112.7310-1-abner.chang@hpe.com> X-Mailer: git-send-email 2.25.0 X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-10_02:2020-04-07,2020-04-10 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=532 suspectscore=0 bulkscore=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004100066 Content-Transfer-Encoding: quoted-printable MdePkg modules and definitionsfor RISC-V architecture on edk2.=0D =0D BZ for entire RISC-V edk2 port,=0D https://bugzilla.tianocore.org/show_bug.cgi?id=3D2672=0D =0D These commits are verified by below PR,=0D https://github.com/tianocore/edk2/pull/512=0D =0D Abner Chang (9):=0D MdePkg: RISC-V RV64 binding in MdePkg=0D MdePkg/Include: RISC-V definitions.=0D MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.=0D MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance=0D implementation.=0D MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=3D>IoLibNoIo.c=0D MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.=0D MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.=0D MdePkg/BaseSynchronizationLib: RISC-V cache related code.=0D MdePkg/BaseSafeIntLib: Add RISCV64 arch for BaseSafeIntLib.=0D =0D MdePkg/MdePkg.dec | 5 +-=0D MdePkg/MdePkg.dsc | 3 +-=0D .../BaseCacheMaintenanceLib.inf | 4 +=0D MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +-=0D .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 12 +-=0D MdePkg/Library/BaseLib/BaseLib.inf | 18 +-=0D .../Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +=0D .../Library/BaseSafeIntLib/BaseSafeIntLib.inf | 6 +-=0D .../BaseSynchronizationLib.inf | 5 +=0D MdePkg/Include/IndustryStandard/PeImage.h | 12 +=0D MdePkg/Include/Library/BaseLib.h | 26 ++=0D MdePkg/Include/Protocol/DebugSupport.h | 55 ++++=0D MdePkg/Include/Protocol/PxeBaseCode.h | 4 +=0D MdePkg/Include/RiscV64/ProcessorBind.h | 173 ++++++++++++=0D MdePkg/Include/Uefi/UefiBaseType.h | 13 +=0D MdePkg/Include/Uefi/UefiSpec.h | 5 +=0D .../BasePeCoffLib/BasePeCoffLibInternals.h | 9 +=0D .../BaseCacheMaintenanceLib/RiscVCache.c | 250 ++++++++++++++++++=0D .../{IoLibArm.c =3D> IoLibNoIo.c} | 4 +-=0D .../Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 ++=0D MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 ++=0D .../BaseLib/RiscV64/DisableInterrupts.c | 24 ++=0D .../BaseLib/RiscV64/EnableInterrupts.c | 25 ++=0D .../BaseLib/RiscV64/GetInterruptState.c | 35 +++=0D .../BaseLib/RiscV64/InternalSwitchStack.c | 55 ++++=0D MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++=0D MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-=0D .../BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 133 ++++++++++=0D MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +-=0D MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 ++=0D MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 ++=0D .../BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +=0D .../Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +=0D .../Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++=0D .../BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 ++++=0D .../Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +=0D .../RiscV64/SynchronizationAsm.S | 78 ++++++=0D 37 files changed, 1204 insertions(+), 14 deletions(-)=0D create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h=0D create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c=0D rename MdePkg/Library/BaseIoLibIntrinsic/{IoLibArm.c =3D> IoLibNoIo.c} (94= %)=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c=0D create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c=0D create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S=0D create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S=0D create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zationAsm.S=0D =0D -- =0D 2.25.0=0D =0D