From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5058.1586505551259537265 for ; Fri, 10 Apr 2020 00:59:11 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=036964ab29=abner.chang@hpe.com) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7urCo000536; Fri, 10 Apr 2020 07:59:11 GMT Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 3091pkm0rf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:10 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 2A6929D; Fri, 10 Apr 2020 07:59:10 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id C4F5436; Fri, 10 Apr 2020 07:59:08 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [PATCH v1 3/9] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor. Date: Fri, 10 Apr 2020 15:21:06 +0800 Message-Id: <20200410072112.7310-4-abner.chang@hpe.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-10_02:2020-04-07,2020-04-10 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=999 suspectscore=1 bulkscore=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004100066 Content-Transfer-Encoding: quoted-printable Add RISC-V RV64 BaseLib functions. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- MdePkg/Library/BaseLib/BaseLib.inf | 18 +++++- MdePkg/Include/Library/BaseLib.h | 26 +++++++++ .../Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++++++++ MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 ++++++++++ .../BaseLib/RiscV64/DisableInterrupts.c | 24 ++++++++ .../BaseLib/RiscV64/EnableInterrupts.c | 25 +++++++++ .../BaseLib/RiscV64/GetInterruptState.c | 35 ++++++++++++ .../BaseLib/RiscV64/InternalSwitchStack.c | 55 +++++++++++++++++++ MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++++++++++ MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 +++++++ .../BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +++++ .../Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +++++ .../Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++++++++++ .../BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 +++++++++++++++++++ 14 files changed, 406 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3586beb0ab..a57ae2da31 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -4,6 +4,7 @@ # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= =0D # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -20,7 +21,7 @@ LIBRARY_CLASS =3D BaseLib=0D =0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D #=0D =0D [Sources]=0D @@ -381,6 +382,21 @@ AArch64/CpuBreakpoint.asm | MSFT=0D AArch64/SpeculationBarrier.asm | MSFT=0D =0D +[Sources.RISCV64]=0D + Math64.c=0D + Unaligned.c=0D + RiscV64/InternalSwitchStack.c=0D + RiscV64/CpuBreakpoint.c=0D + RiscV64/GetInterruptState.c=0D + RiscV64/DisableInterrupts.c=0D + RiscV64/EnableInterrupts.c=0D + RiscV64/CpuPause.c=0D + RiscV64/RiscVSetJumpLongJump.S | GCC=0D + RiscV64/RiscVCpuBreakpoint.S | GCC=0D + RiscV64/RiscVCpuPause.S | GCC=0D + RiscV64/RiscVInterrupt.S | GCC=0D + RiscV64/FlushCache.S | GCC=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index ecadff8b23..41862e4285 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -4,6 +4,8 @@ =0D Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
=0D Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=0D +Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -124,6 +126,30 @@ typedef struct { =0D #endif // defined (MDE_CPU_AARCH64)=0D =0D +#if defined (MDE_CPU_RISCV64)=0D +///=0D +/// The RISC-V architecture context buffer used by SetJump() and LongJump(= ).=0D +///=0D +typedef struct {=0D + UINT64 RA;=0D + UINT64 S0;=0D + UINT64 S1;=0D + UINT64 S2;=0D + UINT64 S3;=0D + UINT64 S4;=0D + UINT64 S5;=0D + UINT64 S6;=0D + UINT64 S7;=0D + UINT64 S8;=0D + UINT64 S9;=0D + UINT64 S10;=0D + UINT64 S11;=0D + UINT64 SP;=0D +} BASE_LIBRARY_JUMP_BUFFER;=0D +=0D +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8=0D +=0D +#endif // defined (MDE_CPU_RISCV64)=0D =0D //=0D // String Services=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Librar= y/BaseLib/RiscV64/CpuBreakpoint.c new file mode 100644 index 0000000000..88d0877a2f --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c @@ -0,0 +1,27 @@ +/** @file=0D + CPU breakpoint for RISC-V=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +extern VOID RiscVCpuBreakpoint (VOID);=0D +=0D +/**=0D + Generates a breakpoint on the CPU.=0D +=0D + Generates a breakpoint on the CPU. The breakpoint must be implemented su= ch=0D + that code can resume normal execution after the breakpoint.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +CpuBreakpoint (=0D + VOID=0D + )=0D +{=0D + RiscVCpuBreakpoint ();=0D +}=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/Bas= eLib/RiscV64/CpuPause.c new file mode 100644 index 0000000000..9931bad294 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c @@ -0,0 +1,29 @@ +/** @file=0D + CPU pause for RISC-V=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +extern VOID RiscVCpuPause (VOID);=0D +=0D +=0D +/**=0D + Requests CPU to pause for a short period of time.=0D +=0D + Requests CPU to pause for a short period of time. Typically used in MP=0D + systems to prevent memory starvation while waiting for a spin lock.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +CpuPause (=0D + VOID=0D + )=0D +{=0D + RiscVCpuPause ();=0D +}=0D +=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Li= brary/BaseLib/RiscV64/DisableInterrupts.c new file mode 100644 index 0000000000..867086c09c --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c @@ -0,0 +1,24 @@ +/** @file=0D + CPU disable interrupt function for RISC-V=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include "BaseLibInternals.h"=0D +=0D +extern VOID RiscVDisableSupervisorModeInterrupts (VOID);=0D +=0D +/**=0D + Disables CPU interrupts.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +DisableInterrupts (=0D + VOID=0D + )=0D +{=0D + RiscVDisableSupervisorModeInterrupts ();=0D +}=0D +=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Lib= rary/BaseLib/RiscV64/EnableInterrupts.c new file mode 100644 index 0000000000..22ef73067e --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c @@ -0,0 +1,25 @@ +/** @file=0D + CPU enable interrupt function for RISC-V=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +extern VOID RiscVEnableSupervisorModeInterrupt (VOID);=0D +=0D +/**=0D + Enables CPU interrupts.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +EnableInterrupts (=0D + VOID=0D + )=0D +{=0D + RiscVEnableSupervisorModeInterrupt ();=0D +}=0D +=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Li= brary/BaseLib/RiscV64/GetInterruptState.c new file mode 100644 index 0000000000..292f1ec441 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c @@ -0,0 +1,35 @@ +/** @file=0D + CPU get interrupt state function for RISC-V=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);=0D +=0D +/**=0D + Retrieves the current CPU interrupt state.=0D +=0D + Returns TRUE is interrupts are currently enabled. Otherwise=0D + returns FALSE.=0D +=0D + @retval TRUE CPU interrupts are enabled.=0D + @retval FALSE CPU interrupts are disabled.=0D +=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +GetInterruptState (=0D + VOID=0D + )=0D +{=0D + unsigned long RetValue;=0D +=0D + RetValue =3D RiscVGetSupervisorModeInterrupts ();=0D + return RetValue? TRUE: FALSE;=0D +}=0D +=0D +=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/= Library/BaseLib/RiscV64/InternalSwitchStack.c new file mode 100644 index 0000000000..0bb292141d --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c @@ -0,0 +1,55 @@ +/** @file=0D + Switch stack function for RISC-V=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +/**=0D + Transfers control to a function starting with a new stack.=0D +=0D + Transfers control to the function specified by EntryPoint using the=0D + new stack specified by NewStack and passing in the parameters specified= =0D + by Context1 and Context2. Context1 and Context2 are optional and may=0D + be NULL. The function EntryPoint must never return.=0D + Marker will be ignored on IA-32, x64, and EBC.=0D + IPF CPUs expect one additional parameter of type VOID * that specifies=0D + the new backing store pointer.=0D +=0D + If EntryPoint is NULL, then ASSERT().=0D + If NewStack is NULL, then ASSERT().=0D +=0D + @param EntryPoint A pointer to function to call with the new stack.=0D + @param Context1 A pointer to the context to pass into the EntryPoint= =0D + function.=0D + @param Context2 A pointer to the context to pass into the EntryPoint= =0D + function.=0D + @param NewStack A pointer to the new stack to use for the EntryPoint= =0D + function.=0D + @param Marker VA_LIST marker for the variable argument list.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InternalSwitchStack (=0D + IN SWITCH_STACK_ENTRY_POINT EntryPoint,=0D + IN VOID *Context1, OPTIONAL=0D + IN VOID *Context2, OPTIONAL=0D + IN VOID *NewStack,=0D + IN VA_LIST Marker=0D + )=0D +{=0D + BASE_LIBRARY_JUMP_BUFFER JumpBuffer;=0D +=0D + DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Con= text2:%x NewStack%x\n", \=0D + EntryPoint, Context1, Context2, NewStack));=0D + JumpBuffer.RA =3D (UINTN)EntryPoint;=0D + JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID *);=0D + JumpBuffer.S0 =3D (UINT64)(UINTN)Context1;=0D + JumpBuffer.S1 =3D (UINT64)(UINTN)Context2;=0D + LongJump (&JumpBuffer, (UINTN)-1);=0D + ASSERT(FALSE);=0D +}=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c b/MdePkg/Library/Bas= eLib/RiscV64/LongJump.c new file mode 100644 index 0000000000..fb2ed3fa2d --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c @@ -0,0 +1,32 @@ +/** @file=0D + Long jump implementation of RISC-V=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +=0D +/**=0D + Restores the CPU context that was saved with SetJump().=0D +=0D + Restores the CPU context from the buffer specified by JumpBuffer.=0D + This function never returns to the caller.=0D + Instead is resumes execution based on the state of JumpBuffer.=0D +=0D + @param JumpBuffer A pointer to CPU context buffer.=0D + @param Value The value to return when the SetJump() context is = restored.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InternalLongJump (=0D + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,=0D + IN UINTN Value=0D + )=0D +{=0D + ASSERT (FALSE);=0D +}=0D +=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/FlushCache.S new file mode 100644 index 0000000000..7c10fdd268 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -0,0 +1,21 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// RISC-V cache operation.=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +=0D +.align 3=0D +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)=0D +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)=0D +=0D +ASM_PFX(RiscVInvalidateInstCacheAsm):=0D + fence.i=0D + ret=0D +=0D +ASM_PFX(RiscVInvalidateDataCacheAsm):=0D + fence=0D + ret=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/L= ibrary/BaseLib/RiscV64/RiscVCpuBreakpoint.S new file mode 100644 index 0000000000..ccf91df816 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// CpuBreakpoint for RISC-V=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +=0D +ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)=0D +ASM_PFX(RiscVCpuBreakpoint):=0D + ebreak=0D + ret=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Librar= y/BaseLib/RiscV64/RiscVCpuPause.S new file mode 100644 index 0000000000..6660c2fcb3 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S @@ -0,0 +1,14 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// CpuPause for RISC-V=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +=0D +ASM_GLOBAL ASM_PFX(RiscVCpuPause)=0D +ASM_PFX(RiscVCpuPause):=0D + nop=0D + ret=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S new file mode 100644 index 0000000000..766fcfb9cb --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -0,0 +1,32 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// RISC-V Supervisor Mode interrupt enable/disable=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +=0D +ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)=0D +ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)=0D +ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)=0D +=0D +# define MSTATUS_SIE 0x00000002=0D +# define CSR_SSTATUS 0x100=0D +=0D +ASM_PFX(RiscVDisableSupervisorModeInterrupts):=0D + li a1, MSTATUS_SIE=0D + csrc CSR_SSTATUS, a1=0D + ret=0D +=0D +ASM_PFX(RiscVEnableSupervisorModeInterrupt):=0D + li a1, MSTATUS_SIE=0D + csrs CSR_SSTATUS, a1=0D + ret=0D +=0D +ASM_PFX(RiscVGetSupervisorModeInterrupts):=0D + csrr a0, CSR_SSTATUS=0D + andi a0, a0, MSTATUS_SIE=0D + ret=0D +=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg= /Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S new file mode 100644 index 0000000000..34486eabba --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// Set/Long jump for RISC-V=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +# define REG_S sd=0D +# define REG_L ld=0D +# define SZREG 8=0D +.align 3=0D + .globl SetJump=0D +=0D +SetJump:=0D + REG_S ra, 0*SZREG(a0)=0D + REG_S s0, 1*SZREG(a0)=0D + REG_S s1, 2*SZREG(a0)=0D + REG_S s2, 3*SZREG(a0)=0D + REG_S s3, 4*SZREG(a0)=0D + REG_S s4, 5*SZREG(a0)=0D + REG_S s5, 6*SZREG(a0)=0D + REG_S s6, 7*SZREG(a0)=0D + REG_S s7, 8*SZREG(a0)=0D + REG_S s8, 9*SZREG(a0)=0D + REG_S s9, 10*SZREG(a0)=0D + REG_S s10, 11*SZREG(a0)=0D + REG_S s11, 12*SZREG(a0)=0D + REG_S sp, 13*SZREG(a0)=0D + li a0, 0=0D + ret=0D +=0D + .globl InternalLongJump=0D +InternalLongJump:=0D + REG_L ra, 0*SZREG(a0)=0D + REG_L s0, 1*SZREG(a0)=0D + REG_L s1, 2*SZREG(a0)=0D + REG_L s2, 3*SZREG(a0)=0D + REG_L s3, 4*SZREG(a0)=0D + REG_L s4, 5*SZREG(a0)=0D + REG_L s5, 6*SZREG(a0)=0D + REG_L s6, 7*SZREG(a0)=0D + REG_L s7, 8*SZREG(a0)=0D + REG_L s8, 9*SZREG(a0)=0D + REG_L s9, 10*SZREG(a0)=0D + REG_L s10, 11*SZREG(a0)=0D + REG_L s11, 12*SZREG(a0)=0D + REG_L sp, 13*SZREG(a0)=0D +=0D + add a0, s0, 0=0D + add a1, s1, 0=0D + add a2, s2, 0=0D + add a3, s3, 0=0D + ret=0D --=20 2.25.0