From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.5059.1586505552965315956 for ; Fri, 10 Apr 2020 00:59:13 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=036964ab29=abner.chang@hpe.com) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7wXri009909; Fri, 10 Apr 2020 07:59:12 GMT Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 30a5ehwygu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:12 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id D00D765; Fri, 10 Apr 2020 07:59:11 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 78F0B39; Fri, 10 Apr 2020 07:59:10 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [PATCH v1 4/9] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Date: Fri, 10 Apr 2020 15:21:07 +0800 Message-Id: <20200410072112.7310-5-abner.chang@hpe.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-10_02:2020-04-07,2020-04-10 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 phishscore=0 mlxlogscore=972 clxscore=1015 adultscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004100067 Content-Transfer-Encoding: quoted-printable Implement RISC-V cache maintenance functions in BaseCacheMaintenanceLib. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- .../BaseCacheMaintenanceLib.inf | 4 + .../BaseCacheMaintenanceLib/RiscVCache.c | 250 ++++++++++++++++++ 2 files changed, 254 insertions(+) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index ec7feecf9c..33114243d5 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -6,6 +6,7 @@ #=0D # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= =0D +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -41,6 +42,9 @@ [Sources.AARCH64]=0D ArmCache.c=0D =0D +[Sources.RISCV64]=0D + RiscVCache.c=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c new file mode 100644 index 0000000000..21a695c843 --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -0,0 +1,250 @@ +/** @file=0D + RISC-V specific functionality for cache.=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + RISC-V invalidate instruction cache.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVInvalidateInstCacheAsm (=0D + VOID=0D + );=0D +=0D +/**=0D + RISC-V invalidate data cache.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVInvalidateDataCacheAsm (=0D + VOID=0D + );=0D +=0D +/**=0D + Invalidates the entire instruction cache in cache coherency domain of th= e=0D + calling CPU.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InvalidateInstructionCache (=0D + VOID=0D + )=0D +{=0D + RiscVInvalidateInstCacheAsm ();=0D +}=0D +=0D +/**=0D + Invalidates a range of instruction cache lines in the cache coherency do= main=0D + of the calling CPU.=0D +=0D + Invalidates the instruction cache lines specified by Address and Length.= If=0D + Address is not aligned on a cache line boundary, then entire instruction= =0D + cache line containing Address is invalidated. If Address + Length is not= =0D + aligned on a cache line boundary, then the entire instruction cache line= =0D + containing Address + Length -1 is invalidated. This function may choose = to=0D + invalidate the entire instruction cache if that is more efficient than=0D + invalidating the specified range. If Length is 0, then no instruction ca= che=0D + lines are invalidated. Address is returned.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param Address The base address of the instruction cache lines to=0D + invalidate. If the CPU is in a physical addressing mode,= then=0D + Address is a physical address. If the CPU is in a virtua= l=0D + addressing mode, then Address is a virtual address.=0D +=0D + @param Length The number of bytes to invalidate from the instruction c= ache.=0D +=0D + @return Address.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +InvalidateInstructionCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length=0D + )=0D +{=0D + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));= =0D + return Address;=0D +}=0D +=0D +/**=0D + Writes back and invalidates the entire data cache in cache coherency dom= ain=0D + of the calling CPU.=0D +=0D + Writes back and invalidates the entire data cache in cache coherency dom= ain=0D + of the calling CPU. This function guarantees that all dirty cache lines = are=0D + written back to system memory, and also invalidates all the data cache l= ines=0D + in the cache coherency domain of the calling CPU.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +WriteBackInvalidateDataCache (=0D + VOID=0D + )=0D +{=0D + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));= =0D +}=0D +=0D +/**=0D + Writes back and invalidates a range of data cache lines in the cache=0D + coherency domain of the calling CPU.=0D +=0D + Writes back and invalidates the data cache lines specified by Address an= d=0D + Length. If Address is not aligned on a cache line boundary, then entire = data=0D + cache line containing Address is written back and invalidated. If Addres= s +=0D + Length is not aligned on a cache line boundary, then the entire data cac= he=0D + line containing Address + Length -1 is written back and invalidated. Thi= s=0D + function may choose to write back and invalidate the entire data cache i= f=0D + that is more efficient than writing back and invalidating the specified= =0D + range. If Length is 0, then no data cache lines are written back and=0D + invalidated. Address is returned.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param Address The base address of the data cache lines to write back a= nd=0D + invalidate. If the CPU is in a physical addressing mode,= then=0D + Address is a physical address. If the CPU is in a virtua= l=0D + addressing mode, then Address is a virtual address.=0D + @param Length The number of bytes to write back and invalidate from th= e=0D + data cache.=0D +=0D + @return Address of cache invalidation.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +WriteBackInvalidateDataCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length=0D + )=0D +{=0D + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));= =0D + return Address;=0D +}=0D +=0D +/**=0D + Writes back the entire data cache in cache coherency domain of the calli= ng=0D + CPU.=0D +=0D + Writes back the entire data cache in cache coherency domain of the calli= ng=0D + CPU. This function guarantees that all dirty cache lines are written bac= k to=0D + system memory. This function may also invalidate all the data cache line= s in=0D + the cache coherency domain of the calling CPU.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +WriteBackDataCache (=0D + VOID=0D + )=0D +{=0D + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));= =0D +}=0D +=0D +/**=0D + Writes back a range of data cache lines in the cache coherency domain of= the=0D + calling CPU.=0D +=0D + Writes back the data cache lines specified by Address and Length. If Add= ress=0D + is not aligned on a cache line boundary, then entire data cache line=0D + containing Address is written back. If Address + Length is not aligned o= n a=0D + cache line boundary, then the entire data cache line containing Address = +=0D + Length -1 is written back. This function may choose to write back the en= tire=0D + data cache if that is more efficient than writing back the specified ran= ge.=0D + If Length is 0, then no data cache lines are written back. This function= may=0D + also invalidate all the data cache lines in the specified range of the c= ache=0D + coherency domain of the calling CPU. Address is returned.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param Address The base address of the data cache lines to write back. = If=0D + the CPU is in a physical addressing mode, then Address i= s a=0D + physical address. If the CPU is in a virtual addressing= =0D + mode, then Address is a virtual address.=0D + @param Length The number of bytes to write back from the data cache.=0D +=0D + @return Address of cache written in main memory.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +WriteBackDataCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length=0D + )=0D +{=0D + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));= =0D + return Address;=0D +}=0D +=0D +/**=0D + Invalidates the entire data cache in cache coherency domain of the calli= ng=0D + CPU.=0D +=0D + Invalidates the entire data cache in cache coherency domain of the calli= ng=0D + CPU. This function must be used with care because dirty cache lines are = not=0D + written back to system memory. It is typically used for cache diagnostic= s. If=0D + the CPU does not support invalidation of the entire data cache, then a w= rite=0D + back and invalidate operation should be performed on the entire data cac= he.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InvalidateDataCache (=0D + VOID=0D + )=0D +{=0D + RiscVInvalidateDataCacheAsm ();=0D +}=0D +=0D +/**=0D + Invalidates a range of data cache lines in the cache coherency domain of= the=0D + calling CPU.=0D +=0D + Invalidates the data cache lines specified by Address and Length. If Add= ress=0D + is not aligned on a cache line boundary, then entire data cache line=0D + containing Address is invalidated. If Address + Length is not aligned on= a=0D + cache line boundary, then the entire data cache line containing Address = +=0D + Length -1 is invalidated. This function must never invalidate any cache = lines=0D + outside the specified range. If Length is 0, then no data cache lines ar= e=0D + invalidated. Address is returned. This function must be used with care=0D + because dirty cache lines are not written back to system memory. It is=0D + typically used for cache diagnostics. If the CPU does not support=0D + invalidation of a data cache range, then a write back and invalidate=0D + operation should be performed on the data cache range.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param Address The base address of the data cache lines to invalidate. = If=0D + the CPU is in a physical addressing mode, then Address i= s a=0D + physical address. If the CPU is in a virtual addressing = mode,=0D + then Address is a virtual address.=0D + @param Length The number of bytes to invalidate from the data cache.=0D +=0D + @return Address.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +InvalidateDataCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length=0D + )=0D +{=0D + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));= =0D + return Address;=0D +}=0D --=20 2.25.0