From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.5063.1586505580205824353 for ; Fri, 10 Apr 2020 00:59:40 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=036964ab29=abner.chang@hpe.com) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7xdwK009719; Fri, 10 Apr 2020 07:59:39 GMT Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 3091n0m2n4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:39 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id E25BD65; Fri, 10 Apr 2020 07:59:16 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 89AF63A; Fri, 10 Apr 2020 07:59:15 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [PATCH v1 7/9] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation. Date: Fri, 10 Apr 2020 15:21:10 +0800 Message-Id: <20200410072112.7310-8-abner.chang@hpe.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-10_02:2020-04-07,2020-04-10 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 mlxlogscore=886 spamscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=1 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004100067 Content-Transfer-Encoding: quoted-printable Implement RISC-V CPU related functions in BaseCpuLib. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++- MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++-- MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++ 3 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index a7cb381a85..950f5229b2 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -7,6 +7,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= =0D # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -24,7 +25,7 @@ =0D =0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D #=0D =0D [Sources.IA32]=0D @@ -59,6 +60,9 @@ AArch64/CpuFlushTlb.asm | MSFT=0D AArch64/CpuSleep.asm | MSFT=0D =0D +[Sources.RISCV64]=0D + RiscV/Cpu.S=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/Base= CpuLib/BaseCpuLib.uni index fc95cda9fc..80dc495786 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni @@ -1,12 +1,13 @@ // /** @file=0D // Instance of CPU Library for various architecture.=0D //=0D -// CPU Library implemented using ASM functions for IA-32 and X64,=0D +// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,= =0D // PAL CALLs for IPF, and empty functions for EBC.=0D //=0D // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
= =0D // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= =0D // Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D @@ -15,5 +16,5 @@ =0D #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU L= ibrary for various architectures"=0D =0D -#string STR_MODULE_DESCRIPTION #language en-US "CPU Library imple= mented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty = functions for EBC."=0D +#string STR_MODULE_DESCRIPTION #language en-US "CPU Library imple= mented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, a= nd empty functions for EBC."=0D =0D diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpu= Lib/RiscV/Cpu.S new file mode 100644 index 0000000000..375b91d314 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S @@ -0,0 +1,19 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// CpuSleep for RISC-V=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +.data=0D +.align 3=0D +.section .text=0D +=0D +.global ASM_PFX(_CpuSleep)=0D +=0D +ASM_PFX(_CpuSleep):=0D + wfi=0D + ret=0D +=0D +=0D --=20 2.25.0