From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.5090.1586505559640193090 for ; Fri, 10 Apr 2020 00:59:19 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=036964ab29=abner.chang@hpe.com) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03A7wYAu009963; Fri, 10 Apr 2020 07:59:19 GMT Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 30a5ehwyhc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Apr 2020 07:59:19 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 98BBBAF; Fri, 10 Apr 2020 07:59:18 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 3F3F03A; Fri, 10 Apr 2020 07:59:17 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Leif Lindholm , Michael D Kinney , Liming Gao Subject: [PATCH v1 8/9] MdePkg/BaseSynchronizationLib: RISC-V cache related code. Date: Fri, 10 Apr 2020 15:21:11 +0800 Message-Id: <20200410072112.7310-9-abner.chang@hpe.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200410072112.7310-1-abner.chang@hpe.com> References: <20200410072112.7310-1-abner.chang@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-10_02:2020-04-07,2020-04-10 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 phishscore=0 mlxlogscore=626 clxscore=1015 adultscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004100067 Content-Transfer-Encoding: quoted-printable Support RISC-V cache related functions. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- .../BaseSynchronizationLib.inf | 5 ++ .../RiscV64/SynchronizationAsm.S | 78 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchroni= zationAsm.S diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 446bc19b63..9309d2e1d5 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -3,6 +3,7 @@ #=0D # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= =0D +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -78,6 +79,10 @@ AArch64/Synchronization.S | GCC=0D AArch64/Synchronization.asm | MSFT=0D =0D +[Sources.RISCV64]=0D + Synchronization.c=0D + RiscV64/SynchronizationAsm.S=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationA= sm.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S new file mode 100644 index 0000000000..bac80d6871 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// RISC-V synchronization functions.=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +#include =0D +=0D +.data=0D +=0D +.text=0D +.align 3=0D +=0D +.global ASM_PFX(InternalSyncCompareExchange32)=0D +.global ASM_PFX(InternalSyncCompareExchange64)=0D +.global ASM_PFX(InternalSyncIncrement)=0D +.global ASM_PFX(InternalSyncDecrement)=0D +=0D +//=0D +// ompare and xchange a 32-bit value.=0D +//=0D +// @param a0 : Pointer to 32-bit value.=0D +// @param a1 : Compare value.=0D +// @param a2 : Exchange value.=0D +//=0D +ASM_PFX (InternalSyncCompareExchange32):=0D + lr.w a3, (a0) // Load the value from a0 and make=0D + // the reservation of address.=0D + bne a3, a1, exit=0D + sc.w a3, a2, (a0) // Write the value back to the address.=0D + mv a3, a1=0D +exit:=0D + mv a0, a3=0D + ret=0D +=0D +.global ASM_PFX(InternalSyncCompareExchange64)=0D +=0D +//=0D +// Compare and xchange a 64-bit value.=0D +//=0D +// @param a0 : Pointer to 64-bit value.=0D +// @param a1 : Compare value.=0D +// @param a2 : Exchange value.=0D +//=0D +ASM_PFX (SyncCompareExchange64):=0D + lr.d a3, (a0) // Load the value from a0 and make=0D + // the reservation of address.=0D + bne a3, a1, exit=0D + sc.d a3, a2, (a0) // Write the value back to the address.=0D + mv a3, a1=0D +exit2:=0D + mv a0, a3=0D + ret=0D +=0D +//=0D +// Performs an atomic increment of an 32-bit unsigned integer.=0D +//=0D +// @param a0 : Pointer to 32-bit value.=0D +//=0D +ASM_PFX (InternalSyncIncrement):=0D + li a1, 1=0D + amoadd.w a2, a1, (a0)=0D + mv a0, a2=0D + ret=0D +=0D +//=0D +// Performs an atomic decrement of an 32-bit unsigned integer.=0D +//=0D +// @param a0 : Pointer to 32-bit value.=0D +//=0D +ASM_PFX (InternalSyncDecrement):=0D + li a1, -1=0D + amoadd.w a2, a1, (a0)=0D + mv a0, a2=0D + ret=0D --=20 2.25.0