From: "Aditya Angadi" <aditya.angadi@arm.com>
To: devel@edk2.groups.io
Cc: thomas.abraham@arm.com, ard.biesheuvel@arm.com,
leif@nuviainc.com, Aditya Angadi <aditya.angadi@arm.com>
Subject: [edk2-platforms][PATCH v4 7/9] Platform/ARM/Sgi: Add ACPI tables for RD-Daniel Config-XLR
Date: Tue, 14 Apr 2020 18:22:06 +0530 [thread overview]
Message-ID: <20200414125208.2878-8-aditya.angadi@arm.com> (raw)
In-Reply-To: <20200414125208.2878-1-aditya.angadi@arm.com>
Add Madt, Dsdt and Srat ACPI tables that are specific for RD-Daniel
Config-XLR platform. Reuse the rest of the shared ACPI tables in SgiPkg.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Dsdt.asl | 125 ++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Madt.aslc | 158 ++++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Srat.aslc | 102 +++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf | 84 +++++++++++
| 19 +++
5 files changed, 488 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Dsdt.asl
new file mode 100644
index 000000000000..23ada55ec4a1
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Dsdt.asl
@@ -0,0 +1,125 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+
+ Device (CP00) { // Zeus core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // Zeus core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // Zeus core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // Zeus core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP04) { // Zeus core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP05) { // Zeus core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP06) { // Zeus core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP07) { // Zeus core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP08) { // Zeus core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP09) { // Zeus core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP10) { // Zeus core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP11) { // Zeus core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP12) { // Zeus core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP13) { // Zeus core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP14) { // Zeus core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP15) { // Zeus core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP16) { // Zeus core 16
+ Name (_HID, "ACPI0007")
+ Name (_UID, 16)
+ Name (_STA, 0xF)
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Madt.aslc
new file mode 100644
index 000000000000..986ba2791e12
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Madt.aslc
@@ -0,0 +1,158 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define CHIPS FixedPcdGet32(PcdChipCount)
+#define CORES (FixedPcdGet32 (PcdClusterCount) * \
+ FixedPcdGet32 (PcdCoreCount))
+
+
+// Multiple APIC Description Table
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORES * CHIPS];
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIPS];
+ EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[4];
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ // MADT specific fields
+ 0, // LocalApicAddress
+ 0 // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase,
+ // Efficiency)
+ // Note: The GIC Structure of the primary CPU must be the first entry
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ //Chip 0
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ // Chip 1
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ // Chip 2
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ // Chip 3
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ 0, 3),
+ {
+ // GIC Redistributor
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(0),
+ SIZE_16MB),
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ SIZE_16MB),
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(2),
+ SIZE_16MB),
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(3),
+ SIZE_16MB)
+ },
+ // GIC ITS
+ {
+ EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000),
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Srat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Srat.aslc
new file mode 100644
index 000000000000..fd5eb7ba170e
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Srat.aslc
@@ -0,0 +1,102 @@
+/** @file
+* Static Resource Affinity Table (SRAT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "SgiAcpiHeader.h"
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+
+//
+// Static Resource Affinity Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE Memory[8];
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE Gicc[16];
+} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
+ // Header
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE,
+ EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
+ ),
+ 0x00000001,
+ EFI_ACPI_RESERVED_QWORD
+ },
+ // Memory Affinity
+ {
+ // Chip 0 (2GB and 6GB)
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x0, PcdSystemMemoryBase, PcdSystemMemorySize, 0x00000001),
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x0, PcdDramBlock2Base, PcdDramBlock2Size, 0x00000001),
+
+ // Chip 1 (2GB and 6GB)
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x1, PcdDramBlock1BaseRemote1, PcdDramBlock1SizeRemote1, 0x00000001),
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x1, PcdDramBlock2BaseRemote1, PcdDramBlock2SizeRemote1, 0x00000001),
+
+ // Chip 2 (2GB and 6GB)
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x2, PcdDramBlock1BaseRemote2, PcdDramBlock1SizeRemote2, 0x00000001),
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ 0x2, PcdDramBlock2BaseRemote2, PcdDramBlock2SizeRemote2, 0x00000001),
+
+ // Chip 3 (2GB and 6GB)
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT(
+ 0x3, PcdDramBlock1BaseRemote3, PcdDramBlock1SizeRemote3, 0x00000001),
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT(
+ 0x3, PcdDramBlock2BaseRemote3, PcdDramBlock2SizeRemote3, 0x00000001),
+ },
+ // Processor Affinity
+ {
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x0, 0x00000000, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x0, 0x00000001, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x0, 0x00000002, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x0, 0x00000003, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x1, 0x00000004, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x1, 0x00000005, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x1, 0x00000006, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x1, 0x00000007, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x2, 0x00000008, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x2, 0x00000009, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x2, 0x0000000A, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x2, 0x0000000B, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x3, 0x0000000C, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x3, 0x0000000D, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x3, 0x0000000E, 0x00000001, 0x00000000),
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ 0x3, 0x0000000F, 0x00000001, 0x00000000),
+ },
+};
+
+VOID* CONST ReferenceAcpiTable = &Srat;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf
new file mode 100644
index 000000000000..d05f025b108c
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf
@@ -0,0 +1,84 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2020, ARM Ltd. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RdDanielCfgXlrAcpiTables
+ FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d # gArmSgiAcpiTablesGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ SsdtRos.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Iort.aslc
+ Mcfg.aslc
+ RdDanielCfgXlr/Dsdt.asl
+ RdDanielCfgXlr/Madt.aslc
+ RdDanielCfgXlr/Srat.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmSgiTokenSpaceGuid.PcdDramBlock2Base
+ gArmSgiTokenSpaceGuid.PcdDramBlock2Size
+
+ gArmSgiTokenSpaceGuid.PcdDramBlock1BaseRemote1
+ gArmSgiTokenSpaceGuid.PcdDramBlock1SizeRemote1
+ gArmSgiTokenSpaceGuid.PcdDramBlock2BaseRemote1
+ gArmSgiTokenSpaceGuid.PcdDramBlock2SizeRemote1
+
+ gArmSgiTokenSpaceGuid.PcdDramBlock1BaseRemote2
+ gArmSgiTokenSpaceGuid.PcdDramBlock1SizeRemote2
+ gArmSgiTokenSpaceGuid.PcdDramBlock2BaseRemote2
+ gArmSgiTokenSpaceGuid.PcdDramBlock2SizeRemote2
+
+ gArmSgiTokenSpaceGuid.PcdDramBlock1BaseRemote3
+ gArmSgiTokenSpaceGuid.PcdDramBlock1SizeRemote3
+ gArmSgiTokenSpaceGuid.PcdDramBlock2BaseRemote3
+ gArmSgiTokenSpaceGuid.PcdDramBlock2SizeRemote3
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index ecb0d4eccf24..16077a62f4db 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -100,4 +100,23 @@
EFI_ACPI_RESERVED_DWORD /* DiscoveryRangeLength */ \
}
+// EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE
+#define EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, Base, Length, Flags) \
+ { \
+ 1, sizeof (EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE), ProximityDomain, \
+ EFI_ACPI_RESERVED_WORD, FixedPcdGet64 (Base) & 0xffffffff, \
+ FixedPcdGet64 (Base) >> 32, FixedPcdGet64 (Length) & 0xffffffff, \
+ FixedPcdGet64 (Length) >> 32, EFI_ACPI_RESERVED_DWORD, Flags, \
+ EFI_ACPI_RESERVED_QWORD \
+ }
+
+// EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE
+#define EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \
+ { \
+ 3, sizeof (EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE), ProximityDomain, \
+ ACPIProcessorUID, Flags, ClockDomain \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1
next prev parent reply other threads:[~2020-04-14 12:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 12:51 [edk2-platforms][PATCH v4 0/9]Platform/Arm/Sgi: Add platform support for RD-Daniel Aditya Angadi
2020-04-14 12:52 ` [edk2-platforms][PATCH v4 1/9] Platform/ARM/Sgi: Create individual Platform Description File Aditya Angadi
2020-04-27 11:01 ` [edk2-devel] " Ard Biesheuvel
2020-04-27 14:54 ` Aditya Angadi
2020-04-27 14:55 ` Ard Biesheuvel
2020-05-03 4:49 ` Aditya Angadi
2020-04-14 12:52 ` [edk2-platforms][PATCH v4 2/9] Platform/ARM/Sgi: Move the GIC related ACPI helper macros Aditya Angadi
2020-04-27 11:04 ` [edk2-devel] " Ard Biesheuvel
2020-04-14 12:52 ` [edk2-platforms][PATCH v4 3/9] Platform/ARM/Sgi: Move common platform description to SSDT Aditya Angadi
2020-04-27 11:06 ` [edk2-devel] " Ard Biesheuvel
2020-04-14 12:52 ` [edk2-platforms][PATCH v4 4/9] Platform/ARM/Sgi: Add support for remote numa memory nodes Aditya Angadi
2020-04-28 12:28 ` [edk2-devel] " Ard Biesheuvel
2020-04-28 13:15 ` Aditya Angadi
2020-04-14 12:52 ` [edk2-platforms][PATCH v4 5/9] Platform/ARM/Sgi: Add ACPI tables for Rd-Daniel Config-M Aditya Angadi
2020-04-28 12:30 ` Ard Biesheuvel
2020-04-14 12:52 ` [edk2-platforms][PATCH v4 6/9] Platform/ARM/Sgi: Add initial support for RD-Daniel Config-M platform Aditya Angadi
2020-04-28 12:32 ` Ard Biesheuvel
2020-04-28 13:18 ` Aditya Angadi
2020-04-14 12:52 ` Aditya Angadi [this message]
2020-04-14 12:52 ` [edk2-platforms][PATCH v4 8/9] Platform/ARM/Sgi: Add initial support for RD-Daniel Config-XLR platform Aditya Angadi
2020-04-14 12:52 ` [edk2-platforms][PATCH v4 9/9] Platform/ARM/Sgi: Add SRAT table for RdN1Edge dual-chip platform Aditya Angadi
2020-04-14 13:50 ` [edk2-devel] [edk2-platforms][PATCH v4 0/9]Platform/Arm/Sgi: Add platform support for RD-Daniel Ard Biesheuvel
2020-04-14 14:17 ` Aditya Angadi
2020-04-15 4:34 ` Thomas Abraham
2020-04-22 12:12 ` Aditya Angadi
[not found] ` <16082330BC63CB95.30042@groups.io>
2020-04-26 10:12 ` Aditya Angadi
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