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Received: from VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) by VI1PR04MB4461.eurprd04.prod.outlook.com (2603:10a6:803:70::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2900.28; Tue, 14 Apr 2020 12:15:24 +0000 Received: from VI1PR04MB5933.eurprd04.prod.outlook.com ([fe80::45c4:8846:5327:9513]) by VI1PR04MB5933.eurprd04.prod.outlook.com ([fe80::45c4:8846:5327:9513%7]) with mapi id 15.20.2900.028; Tue, 14 Apr 2020 12:15:24 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [PATCH edk2-platforms v3 13/24] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs Date: Wed, 15 Apr 2020 17:43:31 +0530 Message-ID: <20200415121342.9246-14-pankaj.bansal@oss.nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200415121342.9246-1-pankaj.bansal@oss.nxp.com> References: <20200415121342.9246-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0092.apcprd01.prod.exchangelabs.com (2603:1096:3:15::18) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) Return-Path: pankaj.bansal@oss.nxp.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0092.apcprd01.prod.exchangelabs.com (2603:1096:3:15::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2900.15 via Frontend Transport; Tue, 14 Apr 2020 12:15:21 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 0ecd50cc-7eb3-4ca2-f451-08d7e06d8261 X-MS-TrafficTypeDiagnostic: VI1PR04MB4461:|VI1PR04MB4461: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-Forefront-PRVS: 0373D94D15 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR04MB5933.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10009020)(4636009)(376002)(366004)(346002)(136003)(39850400004)(396003)(1076003)(186003)(8936002)(16526019)(86362001)(110136005)(26005)(478600001)(81156014)(8676002)(6512007)(66946007)(316002)(44832011)(66476007)(66556008)(52116002)(5660300002)(6666004)(2906002)(6486002)(6506007)(956004)(19627235002)(2616005);DIR:OUT;SFP:1101; Received-SPF: None (protection.outlook.com: oss.nxp.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2JyHGD8lJ3SG3hFUkebNzNCzEE7rJwgOhx6osJfN1/BIF4TOL7x2kFhlviyErEoNYTI2x48wCcseQBXcMcBvCu0TlmH7/k1KgYHp+cYE7xw0ENaBZ5kdKMTHN1zTF28/hTKnkwR/LVP3lJFa5jcVs6YJnV3RkH7YoLV4I91D1/Ci/5im5nc9mQinSldqtC54gcQi7hTBMegdA3cdzbN7zwuboKXwuOflBMR9mUeN6PHApDSJByqBmZzsiJ3WRTKVoyVmm3jBUL3xpOnLYvjAT1Iv9D9MDmOo8r67YCM+k8hnTZjDSHMT3/6n1C+mNjaFUC1i6905WxSIcZvdDz3Z+EqzmWxdQiThWutT2UmBZqCQdYjnVCxxR3NnhCSdTgnEJ5nvrvIRln+KF6bE1RA+O/6w04Bx1JqBBB5aNfX0NuhisDGTgqedrqk/F6/Mvc5P X-MS-Exchange-AntiSpam-MessageData: rZm1xzHZBZqgBjuDA96hNSvzPcgRg1hMhdIkVJD3xx1uvKvJjzUPBBcfzFHLT4T8hv8e1rZh4XQNG+Yn6BRbEHJv+ammdJ+DGG+h7GmEGFh5GlPtfIHq0s9CujZBF37EnxTBaqjAD3TzAqdF9CvkOw== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0ecd50cc-7eb3-4ca2-f451-08d7e06d8261 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2020 12:15:24.2357 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Cnr2zg3pDjM3LOfRxKB3vGHoz0CfvYTIax04nU3wi0jAlR7f3EdEzAF2qN3epdzQxMe9Cu0MPjVyu5VVOt4T7A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4461 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Pankaj Bansal The SOC takes primary clocking input from the external signal (a clock generator on board). The input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Therefore, move the clock retrieval APIs to Platform Lib. The Input clock is retrieved from board components in Platform Lib, and passed on to SOC Lib APIs to get the correct clock for an IP (after PLL multiplication). Signed-off-by: Pankaj Bansal --- Notes: - sorted NXP_IP_CLOCK enum alphabetically Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 + Silicon/NXP/Include/Library/SocLib.h | 44 ++= ++++++++++++++ Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 53 ++= ++++++++++++++++++ Silicon/NXP/LS1043A/Include/Soc.h | 11 ++= ++ Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 51 ++= +++++++++++++++++ Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 52 ++= +++++++++++++++++ 6 files changed, 212 insertions(+) diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index 99d89498e0e2..3d38a7e58b91 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -17,6 +17,7 @@ ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/NXP/LS1043A/LS1043A.dec Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Lib= rary/SocLib.h new file mode 100644 index 000000000000..749aa230dec5 --- /dev/null +++ b/Silicon/NXP/Include/Library/SocLib.h @@ -0,0 +1,44 @@ +/** @file + + Copyright 2020 NXP + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SOC_LIB_H__ +#define SOC_LIB_H__ + +#include +#include + +/** + Return the input clock frequency to an IP Module. + This function reads the RCW bits and calculates the PLL multipler/divid= er + values to be applied to various IP modules. + If a module is disabled or doesn't exist on platform, then return zero. + + @param[in] BaseClock Base clock to which PLL multipler/divider values = is + to be applied. + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] Args Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within th= e + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +SocGetClock ( + IN UINT64 BaseClock, + IN NXP_IP_CLOCK ClockType, + IN VA_LIST Args + ); + +#endif // SOC_LIB_H__ diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h b/Silicon/NXP/In= clude/Ppi/NxpPlatformGetClock.h new file mode 100644 index 000000000000..bc086bc5b337 --- /dev/null +++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h @@ -0,0 +1,53 @@ +/** @file +* +* Copyright 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef NXP_PLATFORM_PPI_H__ +#define NXP_PLATFORM_PPI_H__ + +#include + +typedef enum _NXP_IP_CLOCK { + NXP_CORE_CLOCK, + NXP_I2C_CLOCK, + NXP_SYSTEM_CLOCK, + NXP_UART_CLOCK +} NXP_IP_CLOCK; + +/** + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs + + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] ... Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within th= e + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +typedef +UINT64 +(EFIAPI * NXP_PLATFORM_GET_CLOCK)( + IN NXP_IP_CLOCK ClockType, + ... + ); + +typedef struct { + NXP_PLATFORM_GET_CLOCK PlatformGetClock; +} NXP_PLATFORM_GET_CLOCK_PPI; + +extern NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi; + +#endif // NXP_PLATFORM_PPI_H__ + diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Includ= e/Soc.h index 441871757d67..e62de570da8a 100644 --- a/Silicon/NXP/LS1043A/Include/Soc.h +++ b/Silicon/NXP/LS1043A/Include/Soc.h @@ -8,6 +8,8 @@ #ifndef SOC_H__ #define SOC_H__ =20 +#include + /** Soc Memory Map **/ @@ -41,4 +43,13 @@ #define LS1043A_I2C_SIZE 0x10000 #define LS1043A_I2C_NUM_CONTROLLERS 4 =20 +#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS + +/** + Reset Control Word (RCW) Bits +**/ +#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6 + +typedef CCSR_GUR LS1043A_DEVICE_CONFIG; + #endif // SOC_H__ diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformL= ib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c index 718c71bf02eb..7f5872a78cfc 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -12,10 +12,60 @@ **/ =20 #include +#include #include +#include =20 extern VOID SocInit (VOID); =20 +/** + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs + + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] ... Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. + if ClockType is NXP_CORE_CLOCK, then second argum= ent + is interpreted as cluster number and third argume= nt is + interpreted as core number (within the cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +EFIAPI +NxpPlatformGetClock( + IN UINT32 ClockType, + ... + ) +{ + UINT64 Clock; + VA_LIST Args; + + Clock =3D 0; + + VA_START (Args, ClockType); + + switch (ClockType) { + case NXP_SYSTEM_CLOCK: + Clock =3D 100 * 1000 * 1000; // 100 MHz + break; + case NXP_I2C_CLOCK: + case NXP_UART_CLOCK: + Clock =3D NxpPlatformGetClock (NXP_SYSTEM_CLOCK); + Clock =3D SocGetClock (Clock, ClockType, Args); + break; + default: + break; + } + + VA_END (Args); + + return Clock; +} + /** Return the current Boot Mode =20 @@ -69,6 +119,7 @@ PrePeiCoreGetMpCoreInfo ( } =20 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; +NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi =3D { NxpPlatformGetClock = }; =20 EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { { diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index 98ca2e162f7b..480d8d18fb9f 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include =20 /** Calculate the frequency of various controllers and @@ -50,6 +52,56 @@ GetSysInfo ( CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; } =20 +/** + Return the input clock frequency to an IP Module. + This function reads the RCW bits and calculates the PLL multipler/divid= er + values to be applied to various IP modules. + If a module is disabled or doesn't exist on platform, then return zero. + + @param[in] BaseClock Base clock to which PLL multipler/divider values = is + to be applied. + @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP= clock + is to be retrieved. + @param[in] Args Variable argument list which is parsed based on + ClockType. e.g. if the ClockType is NXP_I2C_CLOCK= , then + the second argument will be interpreted as contro= ller + number. e.g. if there are four i2c controllers in= SOC, + then this value can be 0, 1, 2, 3 + e.g. if ClockType is NXP_CORE_CLOCK, then second + argument is interpreted as cluster number and thi= rd + argument is interpreted as core number (within th= e + cluster) + + @return Actual Clock Frequency. Return value 0 should be + interpreted as clock not being provided to IP. +**/ +UINT64 +SocGetClock ( + IN UINT64 BaseClock, + IN NXP_IP_CLOCK ClockType, + IN VA_LIST Args + ) +{ + LS1043A_DEVICE_CONFIG *Dcfg; + UINT32 RcwSr; + UINT64 ReturnValue; + + ReturnValue =3D 0; + Dcfg =3D (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; + + switch (ClockType) { + case NXP_UART_CLOCK: + case NXP_I2C_CLOCK: + RcwSr =3D GurRead ((UINTN)&Dcfg->RcwSr[0]); + ReturnValue =3D BaseClock * SYS_PLL_RAT (RcwSr); + break; + default: + break; + } + + return ReturnValue; +} + /** Function to initialize SoC specific constructs **/ --=20 2.17.1