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Received: from VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) by VI1PR04MB4461.eurprd04.prod.outlook.com (2603:10a6:803:70::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2900.28; Tue, 14 Apr 2020 12:15:05 +0000 Received: from VI1PR04MB5933.eurprd04.prod.outlook.com ([fe80::45c4:8846:5327:9513]) by VI1PR04MB5933.eurprd04.prod.outlook.com ([fe80::45c4:8846:5327:9513%7]) with mapi id 15.20.2900.028; Tue, 14 Apr 2020 12:15:05 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: [PATCH edk2-platforms v3 07/24] Silicon/NXP: remove print information from Soc lib Date: Wed, 15 Apr 2020 17:43:25 +0530 Message-ID: <20200415121342.9246-8-pankaj.bansal@oss.nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200415121342.9246-1-pankaj.bansal@oss.nxp.com> References: <20200415121342.9246-1-pankaj.bansal@oss.nxp.com> X-ClientProxiedBy: SG2PR01CA0092.apcprd01.prod.exchangelabs.com (2603:1096:3:15::18) To VI1PR04MB5933.eurprd04.prod.outlook.com (2603:10a6:803:ec::16) Return-Path: pankaj.bansal@oss.nxp.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from uefi-workstation.ap.freescale.net (92.120.0.69) by SG2PR01CA0092.apcprd01.prod.exchangelabs.com (2603:1096:3:15::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2900.15 via Frontend Transport; Tue, 14 Apr 2020 12:15:02 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [92.120.0.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7b77d88a-8f74-4e4a-6891-08d7e06d7712 X-MS-TrafficTypeDiagnostic: VI1PR04MB4461:|VI1PR04MB4461: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-Forefront-PRVS: 0373D94D15 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR04MB5933.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10009020)(4636009)(376002)(366004)(346002)(136003)(39850400004)(396003)(1076003)(186003)(8936002)(16526019)(86362001)(110136005)(26005)(478600001)(81156014)(8676002)(6512007)(66946007)(316002)(44832011)(66476007)(66556008)(52116002)(5660300002)(6666004)(2906002)(6486002)(6506007)(956004)(19627235002)(2616005);DIR:OUT;SFP:1101; Received-SPF: None (protection.outlook.com: oss.nxp.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aoVPBLAEfhzHybMO3KWSq4k1xxyjMjo3NPc5YIFDR8iIyf1/Q492oZlkJZ8F7qtxS9Hj9X0k4JXifHiwwTyoTM37LOSYgEe2HfEOJPfSgmXE2COkQ0ybSSsE1CYJYHGTNciatQuwMCqzYkL9pB0AAIYjDD6BH8cIqHRK2XWaL3xFqJZbO7W4o6Y0mlohNBVFQWhBCUEEAswnH8MHS4im9cRlFrAGhKtzZ8GjSwhyxGNLecJY2wVyhW8fA14fRA1GlX9WKmX5A+9LLoYa9A0LrQDliEKA03AkGlUU04L3znYiiR+DUnOzPK2t9P7X3I1dcwN0OTXvXQmd/QXWQQ4COXhiHC0Yfe3MwMQnOrm7RwcMsCvnujzI1gHhoWCriSUUJWydJH7Mx91ma9E9xTErVi1UoxCSSt2E+To2wGLs65re487/fqHEDEj/jcc4H5Bn X-MS-Exchange-AntiSpam-MessageData: lyy9ZUSPgKvaCT5mcaXFjmnIyXmtb/kn3WuG7lcXtRDSnxoqIJ/bmfyvplte7f3afNgRMHPEwcnrOfnyu+Zwk90Uap/v62WF5JQBuLpGoGqctjy7v5yotvmt9kBj9zskbI/QOnGbd6Ox8AR6+wSYAw== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7b77d88a-8f74-4e4a-6891-08d7e06d7712 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2020 12:15:05.3984 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: aW8e/4/w5JjHqMKGGDfIGam8ot0zj1gh+NfZgUZYcJEhEEUaKk6DV3m27wFfxVw9I0ZjtDo4Z5NnraY0Q5kOQQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4461 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Pankaj Bansal The Soc info being printed can be removed from SOC lib. We are in the process of implementing PEI Phase. After PEI phase implementation this info would be printed in common PEIM based on the information retrieved from PPIs. e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and core info. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm --- Notes: - remove CpuMaskNext definition Silicon/NXP/Library/SocLib/NxpChassis.h | 26 +--- Silicon/NXP/Library/SocLib/Chassis.c | 144 -------------------- Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 16 +-- 3 files changed, 2 insertions(+), 184 deletions(-) diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/= SocLib/NxpChassis.h index 99f6439d8f35..a11acf71563e 100644 --- a/Silicon/NXP/Library/SocLib/NxpChassis.h +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h @@ -1,7 +1,7 @@ /** @file * Header defining the Base addresses, sizes, flags etc for chassis 1 * -* Copyright 2017-2019 NXP +* Copyright 2017-2020 NXP * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -54,14 +54,6 @@ typedef struct { UINTN SdhcClk; } SOC_CLOCK_INFO; =20 -/* - * Print Soc information - */ -VOID -PrintSoc ( - VOID - ); - /* * Initialize Clock structure */ @@ -79,22 +71,6 @@ SmmuInit ( VOID ); =20 -/* - * Print CPU information - */ -VOID -PrintCpuInfo ( - VOID - ); - -/* - * Dump RCW (Reset Control Word) on console - */ -VOID -PrintRCW ( - VOID - ); - UINT32 InitiatorType ( IN UINT32 Cluster, diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index b8a8118c5e24..adca7b8dd413 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -204,79 +204,6 @@ QoriqCoreToType ( return EFI_NOT_FOUND; /* cannot identify the cluster */ } =20 -STATIC -UINTN -CpuMaskNext ( - IN UINTN Cpu, - IN UINTN Mask - ) -{ - for (Cpu++; !((1 << Cpu) & Mask); Cpu++); - - return Cpu; -} - -/* - * Print CPU information - */ -VOID -PrintCpuInfo ( - VOID - ) -{ - SYS_INFO SysInfo; - UINTN CoreIndex; - UINTN Core; - UINT32 Type; - UINT32 NumCpus; - UINT32 Mask; - CHAR8 *CoreName; - - GetSysInfo (&SysInfo); - DEBUG ((DEBUG_INIT, "Clock Configuration:")); - - NumCpus =3D CpuNumCores (); - Mask =3D CpuMask (); - - for (CoreIndex =3D 0, Core =3D CpuMaskNext(-1, Mask); - CoreIndex < NumCpus; - CoreIndex++, Core =3D CpuMaskNext(Core, Mask)) - { - if (!(CoreIndex % 3)) { - DEBUG ((DEBUG_INIT, "\n ")); - } - - Type =3D TP_ITYP_VERSION (QoriqCoreToType (Core)); - switch (Type) { - case TY_ITYP_VERSION_A7: - CoreName =3D "A7"; - break; - case TY_ITYP_VERSION_A53: - CoreName =3D "A53"; - break; - case TY_ITYP_VERSION_A57: - CoreName =3D "A57"; - break; - case TY_ITYP_VERSION_A72: - CoreName =3D "A72"; - break; - default: - CoreName =3D " Unknown Core "; - } - DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", - Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ)); - } - - DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBu= s / MHZ)); - DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ)); - - if (SysInfo.FreqFman[0] !=3D 0) { - DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[= 0] / MHZ)); - } - - DEBUG ((DEBUG_INIT, "\n")); -} - /* * Return system bus frequency */ @@ -307,77 +234,6 @@ GetSdxcFrequency ( return SocSysInfo.FreqSdhc; } =20 -/* - * Print Soc information - */ -VOID -PrintSoc ( - VOID - ) -{ - CHAR8 Buf[20]; - CCSR_GUR *GurBase; - UINTN Count; - // - // Svr : System Version Register - // - UINTN Svr; - UINTN Ver; - - GurBase =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - - Svr =3D GurRead ((UINTN)&GurBase->Svr); - Ver =3D SVR_SOC_VER (Svr); - - for (Count =3D 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) =3D=3D Ver) { - AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name); - - if (IS_E_PROCESSOR (Svr)) { - AsciiStrCatS (Buf, sizeof (Buf), "E"); - } - break; - } - } - - DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n", - Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr))); - - return; -} - -/* - * Dump RCW (Reset Control Word) on console - */ -VOID -PrintRCW ( - VOID - ) -{ - CCSR_GUR *Base; - UINTN Count; - - Base =3D (VOID *)PcdGet64 (PcdGutsBaseAddr); - - /* - * Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - - DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):")); - for (Count =3D 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) { - UINT32 Rcw =3D SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]); - - if ((Count % 4) =3D=3D 0) { - DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4)); - } - - DEBUG ((DEBUG_INIT, " %08x", Rcw)); - } - - DEBUG ((DEBUG_INIT, "\n")); -} - /* * Setup SMMU in bypass mode * and also set its pagesize diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Librar= y/SocLib/Chassis2/Soc.c index bfb8b8cb339a..687a1d940066 100644 --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c @@ -1,7 +1,7 @@ /** @Soc.c SoC specific Library containg functions to initialize various SoC compon= ents =20 - Copyright 2017-2019 NXP + Copyright 2017-2020 NXP =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -131,10 +131,6 @@ GetSysInfo ( =20 /** Function to initialize SoC specific constructs - CPU Info - SoC Personality - Board Personality - RCW prints **/ VOID SocInit ( @@ -147,16 +143,6 @@ SocInit ( // Early init serial Port to get board information. // SerialPortInitialize (); - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n", - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE_= _)); - - PrintCpuInfo (); - - // - // Print Reset control Word - // - PrintRCW (); - PrintSoc (); =20 return; } --=20 2.17.1