From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.1650.1587388782721785067 for ; Mon, 20 Apr 2020 06:19:43 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=037915fef8=abner.chang@hpe.com) Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03KD60Rh014320; Mon, 20 Apr 2020 13:19:42 GMT Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com with ESMTP id 30g2tkt7s7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Apr 2020 13:19:41 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 385DA9D; Mon, 20 Apr 2020 13:19:41 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 776E83B; Mon, 20 Apr 2020 13:19:39 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Gilbert Chen , Daniel Helmut Schaefer , Leif Lindholm , Bob Feng , Liming Gao Subject: [PATCH v2 1/1] BaseTools: BaseTools changes for RISC-V platform. Date: Mon, 20 Apr 2020 20:41:24 +0800 Message-Id: <20200420124124.6763-2-abner.chang@hpe.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200420124124.6763-1-abner.chang@hpe.com> References: <20200420124124.6763-1-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-20_04:2020-04-20,2020-04-20 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 suspectscore=0 impostorscore=0 mlxscore=0 spamscore=0 clxscore=1011 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004200114 Content-Transfer-Encoding: quoted-printable BaseTools changes for building EDK2 RISC-V platform. The changes made to build_rule.template is to avoid build errors caused by GCC5 tool chain. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Co-authored-by: Daniel Helmut Schaefer Reviewed-by: Leif Lindholm Cc: Bob Feng Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- BaseTools/Source/C/Common/PeCoffLib.h | 9 + BaseTools/Source/C/GenFw/elf_common.h | 62 ++++ .../C/Include/IndustryStandard/PeImage.h | 6 + BaseTools/Source/C/Common/BasePeCoff.c | 15 +- BaseTools/Source/C/Common/PeCoffLoaderEx.c | 86 ++++++ BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++- BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +- BaseTools/Source/C/GenFw/Elf64Convert.c | 282 +++++++++++++++++- BaseTools/Conf/tools_def.template | 53 +++- BaseTools/Source/Python/Common/DataType.py | 5 +- BaseTools/Source/Python/build/buildoptions.py | 6 +- 11 files changed, 638 insertions(+), 19 deletions(-) diff --git a/BaseTools/Source/C/Common/PeCoffLib.h b/BaseTools/Source/C/Com= mon/PeCoffLib.h index 2fb2265e80..dd38f442f9 100644 --- a/BaseTools/Source/C/Common/PeCoffLib.h +++ b/BaseTools/Source/C/Common/PeCoffLib.h @@ -2,6 +2,7 @@ Function prototypes and defines on Memory Only PE COFF loader=0D =0D Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D + Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -25,6 +26,14 @@ #define IMAGE_ERROR_FAILED_RELOCATION 9=0D #define IMAGE_ERROR_FAILED_ICACHE_FLUSH 10=0D =0D +//=0D +// Macro definitions for RISC-V architecture.=0D +//=0D +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))=0D +#define RISCV_IMM_BITS 12=0D +#define RISCV_IMM_REACH (1LL<=0D Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D +Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All= rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D =0D @@ -178,6 +179,8 @@ typedef struct { #define EM_X86_64 62 /* Advanced Micro Devices x86-64 */=0D #define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */= =0D #define EM_AARCH64 183 /* ARM 64bit Architecture */=0D +#define EM_RISCV64 243 /* 64bit RISC-V Architecture */=0D +#define EM_RISCV 244 /* 32bit RISC-V Architecture */=0D =0D /* Non-standard or deprecated. */=0D #define EM_486 6 /* Intel i486. */=0D @@ -979,5 +982,64 @@ typedef struct { #define R_X86_64_GOTPCRELX 41 /* Load from 32 bit signed pc relative of= fset to GOT entry without REX prefix, relaxable. */=0D #define R_X86_64_REX_GOTPCRELX 42 /* Load from 32 bit signed pc relativ= e offset to GOT entry with REX prefix, relaxable. */=0D =0D +/*=0D + * RISC-V relocation types=0D + */=0D +=0D +/* Relocation types used by the dynamic linker */=0D +#define R_RISCV_NONE 0=0D +#define R_RISCV_32 1=0D +#define R_RISCV_64 2=0D +#define R_RISCV_RELATIVE 3=0D +#define R_RISCV_COPY 4=0D +#define R_RISCV_JUMP_SLOT 5=0D +#define R_RISCV_TLS_DTPMOD32 6=0D +#define R_RISCV_TLS_DTPMOD64 7=0D +#define R_RISCV_TLS_DTPREL32 8=0D +#define R_RISCV_TLS_DTPREL64 9=0D +#define R_RISCV_TLS_TPREL32 10=0D +#define R_RISCV_TLS_TPREL64 11=0D =0D +/* Relocation types not used by the dynamic linker */=0D +#define R_RISCV_BRANCH 16=0D +#define R_RISCV_JAL 17=0D +#define R_RISCV_CALL 18=0D +#define R_RISCV_CALL_PLT 19=0D +#define R_RISCV_GOT_HI20 20=0D +#define R_RISCV_TLS_GOT_HI20 21=0D +#define R_RISCV_TLS_GD_HI20 22=0D +#define R_RISCV_PCREL_HI20 23=0D +#define R_RISCV_PCREL_LO12_I 24=0D +#define R_RISCV_PCREL_LO12_S 25=0D +#define R_RISCV_HI20 26=0D +#define R_RISCV_LO12_I 27=0D +#define R_RISCV_LO12_S 28=0D +#define R_RISCV_TPREL_HI20 29=0D +#define R_RISCV_TPREL_LO12_I 30=0D +#define R_RISCV_TPREL_LO12_S 31=0D +#define R_RISCV_TPREL_ADD 32=0D +#define R_RISCV_ADD8 33=0D +#define R_RISCV_ADD16 34=0D +#define R_RISCV_ADD32 35=0D +#define R_RISCV_ADD64 36=0D +#define R_RISCV_SUB8 37=0D +#define R_RISCV_SUB16 38=0D +#define R_RISCV_SUB32 39=0D +#define R_RISCV_SUB64 40=0D +#define R_RISCV_GNU_VTINHERIT 41=0D +#define R_RISCV_GNU_VTENTRY 42=0D +#define R_RISCV_ALIGN 43=0D +#define R_RISCV_RVC_BRANCH 44=0D +#define R_RISCV_RVC_JUMP 45=0D +#define R_RISCV_RVC_LUI 46=0D +#define R_RISCV_GPREL_I 47=0D +#define R_RISCV_GPREL_S 48=0D +#define R_RISCV_TPREL_I 49=0D +#define R_RISCV_TPREL_S 50=0D +#define R_RISCV_RELAX 51=0D +#define R_RISCV_SUB6 52=0D +#define R_RISCV_SET6 53=0D +#define R_RISCV_SET8 54=0D +#define R_RISCV_SET16 55=0D +#define R_RISCV_SET32 56=0D #endif /* !_SYS_ELF_COMMON_H_ */=0D diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTo= ols/Source/C/Include/IndustryStandard/PeImage.h index 44037d13f3..f17b8ee19b 100644 --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h @@ -6,6 +6,7 @@ =0D Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -41,6 +42,7 @@ #define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only=0D #define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/T= humb 2 Little Endian=0D #define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Lit= tle Endian=0D +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA=0D =0D //=0D // Support old names for backward compatible=0D @@ -50,6 +52,7 @@ #define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64=0D #define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT=0D #define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64=0D +#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64=0D =0D #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ=0D #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE=0D @@ -504,7 +507,10 @@ typedef struct { #define EFI_IMAGE_REL_BASED_HIGHADJ 4=0D #define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5=0D #define EFI_IMAGE_REL_BASED_ARM_MOV32A 5=0D +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5=0D #define EFI_IMAGE_REL_BASED_ARM_MOV32T 7=0D +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7=0D +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8=0D #define EFI_IMAGE_REL_BASED_IA64_IMM64 9=0D #define EFI_IMAGE_REL_BASED_DIR64 10=0D =0D diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Co= mmon/BasePeCoff.c index e7566b383b..62fbb2985c 100644 --- a/BaseTools/Source/C/Common/BasePeCoff.c +++ b/BaseTools/Source/C/Common/BasePeCoff.c @@ -4,6 +4,7 @@ =0D Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
=0D Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D +Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -59,6 +60,14 @@ PeCoffLoaderRelocateArmImage ( IN UINT64 Adjust=0D );=0D =0D +RETURN_STATUS=0D +PeCoffLoaderRelocateRiscVImage (=0D + IN UINT16 *Reloc,=0D + IN OUT CHAR8 *Fixup,=0D + IN OUT CHAR8 **FixupData,=0D + IN UINT64 Adjust=0D + );=0D +=0D STATIC=0D RETURN_STATUS=0D PeCoffLoaderGetPeHeader (=0D @@ -174,7 +183,8 @@ Returns: ImageContext->Machine !=3D EFI_IMAGE_MACHINE_X64 && \=0D ImageContext->Machine !=3D EFI_IMAGE_MACHINE_ARMT && \=0D ImageContext->Machine !=3D EFI_IMAGE_MACHINE_EBC && \=0D - ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64) {=0D + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && \=0D + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64) {=0D if (ImageContext->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) {=0D //=0D // There are two types of ARM images. Pure ARM and ARM/Thumb.=0D @@ -802,6 +812,9 @@ Returns: case EFI_IMAGE_MACHINE_ARMT:=0D Status =3D PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupDa= ta, Adjust);=0D break;=0D + case EFI_IMAGE_MACHINE_RISCV64:=0D + Status =3D PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupD= ata, Adjust);=0D + break;=0D default:=0D Status =3D RETURN_UNSUPPORTED;=0D break;=0D diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/= C/Common/PeCoffLoaderEx.c index e367836b96..588b3a2f84 100644 --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c @@ -3,6 +3,7 @@ IA32 and X64 Specific relocation fixups =0D Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
=0D Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D +Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D --*/=0D @@ -61,6 +62,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define IMM64_SIGN_INST_WORD_POS_X 27=0D #define IMM64_SIGN_VAL_POS_X 63=0D =0D +UINT32 *RiscVHi20Fixup =3D NULL;=0D +=0D RETURN_STATUS=0D PeCoffLoaderRelocateIa32Image (=0D IN UINT16 *Reloc,=0D @@ -93,6 +96,89 @@ Returns: return RETURN_UNSUPPORTED;=0D }=0D =0D +/*++=0D +=0D +Routine Description:=0D +=0D + Performs an RISC-V specific relocation fixup=0D +=0D +Arguments:=0D +=0D + Reloc - Pointer to the relocation record=0D +=0D + Fixup - Pointer to the address to fix up=0D +=0D + FixupData - Pointer to a buffer to log the fixups=0D +=0D + Adjust - The offset to adjust the fixup=0D +=0D +Returns:=0D +=0D + Status code=0D +=0D +--*/=0D +RETURN_STATUS=0D +PeCoffLoaderRelocateRiscVImage (=0D + IN UINT16 *Reloc,=0D + IN OUT CHAR8 *Fixup,=0D + IN OUT CHAR8 **FixupData,=0D + IN UINT64 Adjust=0D + )=0D +{=0D + UINT32 Value;=0D + UINT32 Value2;=0D + UINT32 OrgValue;=0D +=0D + OrgValue =3D *(UINT32 *) Fixup;=0D + OrgValue =3D OrgValue;=0D + switch ((*Reloc) >> 12) {=0D + case EFI_IMAGE_REL_BASED_RISCV_HI20:=0D + RiscVHi20Fixup =3D (UINT32 *) Fixup;=0D + break;=0D +=0D + case EFI_IMAGE_REL_BASED_RISCV_LOW12I:=0D + if (RiscVHi20Fixup !=3D NULL) {=0D + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);=0D + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));=0D + if (Value2 & (RISCV_IMM_REACH/2)) {=0D + Value2 |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D + Value +=3D Value2;=0D + Value +=3D (UINT32)Adjust;=0D + Value2 =3D RISCV_CONST_HIGH_PART (Value);=0D + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \=0D + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12));=0D + *(UINT32 *)Fixup =3D (RV_X (Value, 0, 12) << 20) | \=0D + (RV_X (*(UINT32 *)Fixup, 0, 20));=0D + }=0D + RiscVHi20Fixup =3D NULL;=0D + break;=0D +=0D + case EFI_IMAGE_REL_BASED_RISCV_LOW12S:=0D + if (RiscVHi20Fixup !=3D NULL) {=0D + Value =3D (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);=0D + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 = *)Fixup, 25, 7) << 5));=0D + if (Value2 & (RISCV_IMM_REACH/2)) {=0D + Value2 |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D + Value +=3D Value2;=0D + Value +=3D (UINT32)Adjust;=0D + Value2 =3D RISCV_CONST_HIGH_PART (Value);=0D + *(UINT32 *)RiscVHi20Fixup =3D (RV_X (Value2, 12, 20) << 12) | \=0D + (RV_X (*(UINT32 *)RiscVHi20Fixu= p, 0, 12));=0D + Value2 =3D *(UINT32 *)Fixup & 0x01fff07f;=0D + Value &=3D RISCV_IMM_REACH - 1;=0D + *(UINT32 *)Fixup =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) |= (RV_X(Value, 5, 7) << 25)));=0D + }=0D + RiscVHi20Fixup =3D NULL;=0D + break;=0D +=0D + default:=0D + return EFI_UNSUPPORTED;=0D +=0D + }=0D + return RETURN_SUCCESS;=0D +}=0D =0D /**=0D Pass in a pointer to an ARM MOVT or MOVW immediate instruction and=0D diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source= /C/GenFv/GenFvInternalLib.c index daebfe894c..d29a891c9c 100644 --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c @@ -4,6 +4,7 @@ This file contains the internal functions required to gener= ate a Firmware Volume Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
=0D Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D Portions Copyright (c) 2016 HP Development Company, L.P.
=0D +Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -37,6 +38,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000=0D =0D BOOLEAN mArm =3D FALSE;=0D +BOOLEAN mRiscV =3D FALSE;=0D STATIC UINT32 MaxFfsAlignment =3D 0;=0D BOOLEAN VtfFileFlag =3D FALSE;=0D =0D @@ -2291,6 +2293,104 @@ Returns: return EFI_SUCCESS;=0D }=0D =0D +EFI_STATUS=0D +UpdateRiscvResetVectorIfNeeded (=0D + MEMORY_FILE *FvImage,=0D + FV_INFO *FvInfo=0D + )=0D +/*++=0D +=0D +Routine Description:=0D + This parses the FV looking for SEC and patches that address into the=0D + beginning of the FV header.=0D +=0D + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h=0D +=0D +Arguments:=0D + FvImage Memory file for the FV memory image/=0D + FvInfo Information read from INF file.=0D +=0D +Returns:=0D +=0D + EFI_SUCCESS Function Completed successfully.=0D + EFI_ABORTED Error encountered.=0D + EFI_INVALID_PARAMETER A required parameter was NULL.=0D + EFI_NOT_FOUND PEI Core file not found.=0D +=0D +--*/=0D +{=0D + EFI_STATUS Status;=0D + UINT16 MachineType;=0D + EFI_FILE_SECTION_POINTER SecPe32;=0D + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;=0D +=0D + UINT32 bSecCore;=0D + UINT32 tmp;=0D +=0D +=0D + //=0D + // Verify input parameters=0D + //=0D + if (FvImage =3D=3D NULL || FvInfo =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D + //=0D + // Initialize FV library=0D + //=0D + InitializeFvLib (FvImage->FileImage, FvInfo->Size);=0D +=0D + //=0D + // Find the Sec Core=0D + //=0D + Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FI= LETYPE_SECURITY_CORE, &SecPe32);=0D + if(EFI_ERROR(Status)) {=0D + printf("skip because Secutiry Core not found\n");=0D + return EFI_SUCCESS;=0D + }=0D +=0D + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);=0D +=0D + Status =3D GetCoreMachineType(SecPe32, &MachineType);=0D + if(EFI_ERROR(Status)) {=0D + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type f= or SEC core.");=0D + return EFI_ABORTED;=0D + }=0D +=0D + if (MachineType !=3D EFI_IMAGE_MACHINE_RISCV64) {=0D + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Mac= hine type is not RiscV.");=0D + return EFI_ABORTED;=0D + }=0D +=0D + Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32,= &SecCoreEntryAddress);=0D + if(EFI_ERROR(Status)) {=0D + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point ad= dress for SEC Core.");=0D + return EFI_ABORTED;=0D + }=0D +=0D + VerboseMsg("SecCore entry point Address =3D 0x%llX", (unsigned long long= ) SecCoreEntryAddress);=0D + VerboseMsg("BaseAddress =3D 0x%llX", (unsigned long long) FvInfo->BaseAd= dress);=0D + bSecCore =3D (UINT32)(SecCoreEntryAddress - FvInfo->BaseAddress);=0D + VerboseMsg("offset =3D 0x%llX", bSecCore);=0D +=0D + if(bSecCore > 0x0fffff) {=0D + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of= start of the FV");=0D + return EFI_ABORTED;=0D + }=0D +=0D + tmp =3D bSecCore;=0D + bSecCore =3D 0;=0D + //J-type=0D + bSecCore =3D (tmp&0x100000)<<11; //imm[20] at bit[31]=0D + bSecCore |=3D (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]=0D + bSecCore |=3D (tmp&0x000800)<<9; //imm[11] at bit[20]=0D + bSecCore |=3D (tmp&0x0FF000); //imm[19:12] at bit[19:12]=0D + bSecCore |=3D 0x6F; //JAL opcode=0D +=0D + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D EFI_STATUS=0D GetPe32Info (=0D IN UINT8 *Pe32,=0D @@ -2383,7 +2483,8 @@ Returns: // Verify machine type is supported=0D //=0D if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && (*MachineType !=3D EF= I_IMAGE_MACHINE_X64) && (*MachineType !=3D EFI_IMAGE_MACHINE_EBC) &&=0D - (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D EFI= _IMAGE_MACHINE_AARCH64)) {=0D + (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D EFI= _IMAGE_MACHINE_AARCH64) &&=0D + (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64)) {=0D Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE3= 2 file.");=0D return EFI_UNSUPPORTED;=0D }=0D @@ -2826,7 +2927,8 @@ Returns: Error (NULL, 0, 4002, "Resource", "FV space is full, cannot add pad = file between the last file and the VTF file.");=0D goto Finish;=0D }=0D - if (!mArm) {=0D +=0D + if (!mArm && !mRiscV) {=0D //=0D // Update reset vector (SALE_ENTRY for IPF)=0D // Now for IA32 and IA64 platform, the fv which has bsf file must ha= ve the=0D @@ -2861,6 +2963,22 @@ Returns: FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea= der->HeaderLength / sizeof (UINT16));=0D }=0D =0D + if (mRiscV) {=0D + //=0D + // Update RISCV reset vector.=0D + //=0D + Status =3D UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDa= taInfo);=0D + if (EFI_ERROR (Status)) {=0D + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector= for RISC-V.");=0D + goto Finish;=0D + }=0D + //=0D + // Update Checksum for FvHeader=0D + //=0D + FvHeader->Checksum =3D 0;=0D + FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea= der->HeaderLength / sizeof (UINT16));=0D + }=0D +=0D //=0D // Update FV Alignment attribute to the largest alignment of all the FFS= files in the FV=0D //=0D @@ -3448,6 +3566,10 @@ Returns: mArm =3D TRUE;=0D }=0D =0D + if (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_RISCV64) {=0D + mRiscV =3D TRUE;=0D + }=0D +=0D //=0D // Keep Image Context for PE image in FV=0D //=0D @@ -3601,7 +3723,7 @@ Returns: ImageContext.DestinationAddress =3D NewPe32BaseAddress;=0D Status =3D PeCoffLoaderRelocateImage (&ImageC= ontext);=0D if (EFI_ERROR (Status)) {=0D - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on reb= ase of %s", FileName);=0D + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on reb= ase of %s Status=3D%d", FileName, Status);=0D free ((VOID *) MemoryImagePointer);=0D return Status;=0D }=0D diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/G= enFw/Elf32Convert.c index 46089ff370..7f351287a9 100644 --- a/BaseTools/Source/C/GenFw/Elf32Convert.c +++ b/BaseTools/Source/C/GenFw/Elf32Convert.c @@ -3,6 +3,7 @@ Elf32 Convert solution =0D Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
=0D Portions copyright (c) 2013, ARM Ltd. All rights reserved.
=0D +Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -141,8 +142,8 @@ InitializeElf32 ( Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN= ");=0D return FALSE;=0D }=0D - if (!((mEhdr->e_machine =3D=3D EM_386) || (mEhdr->e_machine =3D=3D EM_AR= M))) {=0D - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_386 or EM_A= RM");=0D + if (!((mEhdr->e_machine =3D=3D EM_386) || (mEhdr->e_machine =3D=3D EM_AR= M) || (mEhdr->e_machine =3D=3D EM_RISCV))) {=0D + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf32 machi= ne.");=0D return FALSE;=0D }=0D if (mEhdr->e_version !=3D EV_CURRENT) {=0D diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index d623dce1f9..4ed6b4477e 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -3,6 +3,7 @@ Elf64 convert solution =0D Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
=0D Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.
=0D +Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -122,6 +123,13 @@ STATIC UINT32 mHiiRsrcOffset; STATIC UINT32 mRelocOffset;=0D STATIC UINT32 mDebugOffset;=0D =0D +//=0D +// Used for RISC-V relocations.=0D +//=0D +STATIC UINT8 *mRiscVPass1Targ =3D NULL;=0D +STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL;=0D +STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0;=0D +=0D //=0D // Initialization Function=0D //=0D @@ -153,8 +161,8 @@ InitializeElf64 ( Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN= ");=0D return FALSE;=0D }=0D - if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D EM= _AARCH64))) {=0D - Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64 or E= M_AARCH64");=0D + if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D EM= _AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64))) {=0D + Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 machi= ne.");=0D return FALSE;=0D }=0D if (mEhdr->e_version !=3D EV_CURRENT) {=0D @@ -452,6 +460,147 @@ EmitGOTRelocations ( mGOTMaxCoffEntries =3D 0;=0D mGOTNumCoffEntries =3D 0;=0D }=0D +//=0D +// RISC-V 64 specific Elf WriteSection function.=0D +//=0D +STATIC=0D +VOID=0D +WriteSectionRiscV64 (=0D + Elf_Rela *Rel,=0D + UINT8 *Targ,=0D + Elf_Shdr *SymShdr,=0D + Elf_Sym *Sym=0D + )=0D +{=0D + UINT32 Value;=0D + UINT32 Value2;=0D +=0D + switch (ELF_R_TYPE(Rel->r_info)) {=0D + case R_RISCV_NONE:=0D + break;=0D +=0D + case R_RISCV_32:=0D + *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_a= ddr + mCoffSectionsOffset[Sym->st_shndx]);=0D + break;=0D +=0D + case R_RISCV_64:=0D + *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSections= Offset[Sym->st_shndx];=0D + break;=0D +=0D + case R_RISCV_HI20:=0D + mRiscVPass1Targ =3D Targ;=0D + mRiscVPass1Sym =3D SymShdr;=0D + mRiscVPass1SymSecIndex =3D Sym->st_shndx;=0D + break;=0D +=0D + case R_RISCV_LO12_I:=0D + if (mRiscVPass1Sym =3D=3D SymShdr && mRiscVPass1Targ !=3D NULL && mRis= cVPass1SymSecIndex =3D=3D Sym->st_shndx && mRiscVPass1SymSecIndex !=3D 0) {= =0D + Value =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20) << 12);= =0D + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D + if (Value2 & (RISCV_IMM_REACH/2)) {=0D + Value2 |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D + Value +=3D Value2;=0D + Value =3D Value - (UINT32)SymShdr->sh_addr + mCoffSectionsOffset[Sym= ->st_shndx];=0D + Value2 =3D RISCV_CONST_HIGH_PART (Value);=0D + *(UINT32 *)mRiscVPass1Targ =3D (RV_X (Value2, 12, 20) << 12) | \=0D + (RV_X (*(UINT32 *)mRiscVPass1Targ, 0, 12));=0D + *(UINT32 *)Targ =3D (RV_X (Value, 0, 12) << 20) | \=0D + (RV_X (*(UINT32 *)Targ, 0, 20));=0D + }=0D + mRiscVPass1Sym =3D NULL;=0D + mRiscVPass1Targ =3D NULL;=0D + mRiscVPass1SymSecIndex =3D 0;=0D + break;=0D +=0D + case R_RISCV_LO12_S:=0D + if (mRiscVPass1Sym =3D=3D SymShdr && mRiscVPass1Targ !=3D NULL && mRis= cVPass1SymSecIndex =3D=3D Sym->st_shndx && mRiscVPass1SymSecIndex !=3D 0) {= =0D + Value =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20) << 12);= =0D + Value2 =3D (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5) | (RV_X(*(UINT32 *)T= arg, 25, 7) << 5));=0D + if (Value2 & (RISCV_IMM_REACH/2)) {=0D + Value2 |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D + Value +=3D Value2;=0D + Value =3D Value - (UINT32)SymShdr->sh_addr + mCoffSectionsOffset[Sym= ->st_shndx];=0D + Value2 =3D RISCV_CONST_HIGH_PART (Value);=0D + *(UINT32 *)mRiscVPass1Targ =3D (RV_X (Value2, 12, 20) << 12) | \=0D + (RV_X (*(UINT32 *)mRiscVPass1Targ, 0, 12)= );=0D + Value2 =3D *(UINT32 *)Targ & 0x01fff07f;=0D + Value &=3D RISCV_IMM_REACH - 1;=0D + *(UINT32 *)Targ =3D Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (R= V_X(Value, 5, 7) << 25)));=0D + }=0D + mRiscVPass1Sym =3D NULL;=0D + mRiscVPass1Targ =3D NULL;=0D + mRiscVPass1SymSecIndex =3D 0;=0D + break;=0D +=0D + case R_RISCV_PCREL_HI20:=0D + mRiscVPass1Targ =3D Targ;=0D + mRiscVPass1Sym =3D SymShdr;=0D + mRiscVPass1SymSecIndex =3D Sym->st_shndx;=0D +=0D + Value =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D + break;=0D +=0D + case R_RISCV_PCREL_LO12_I:=0D + if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas= s1SymSecIndex !=3D 0) {=0D + int i;=0D + Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D + if(Value & (RISCV_IMM_REACH/2)) {=0D + Value |=3D ~(RISCV_IMM_REACH-1);=0D + }=0D + Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff= set[mRiscVPass1SymSecIndex];=0D + if(-2048 > (INT32)Value) {=0D + i =3D (((INT32)Value * -1) / 4096);=0D + Value2 -=3D i;=0D + Value +=3D 4096 * i;=0D + if(-2048 > (INT32)Value) {=0D + Value2 -=3D 1;=0D + Value +=3D 4096;=0D + }=0D + }=0D + else if( 2047 < (INT32)Value) {=0D + i =3D (Value / 4096);=0D + Value2 +=3D i;=0D + Value -=3D 4096 * i;=0D + if(2047 < (INT32)Value) {=0D + Value2 +=3D 1;=0D + Value -=3D 4096;=0D + }=0D + }=0D +=0D + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Tar= g, 0, 20));=0D + *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U= INT32 *)mRiscVPass1Targ, 0, 12));=0D + }=0D + mRiscVPass1Sym =3D NULL;=0D + mRiscVPass1Targ =3D NULL;=0D + mRiscVPass1SymSecIndex =3D 0;=0D + break;=0D +=0D + case R_RISCV_ADD64:=0D + case R_RISCV_SUB64:=0D + case R_RISCV_ADD32:=0D + case R_RISCV_SUB32:=0D + case R_RISCV_BRANCH:=0D + case R_RISCV_JAL:=0D + case R_RISCV_GPREL_I:=0D + case R_RISCV_GPREL_S:=0D + case R_RISCV_CALL:=0D + case R_RISCV_RVC_BRANCH:=0D + case R_RISCV_RVC_JUMP:=0D + case R_RISCV_RELAX:=0D + case R_RISCV_SUB6:=0D + case R_RISCV_SET6:=0D + case R_RISCV_SET8:=0D + case R_RISCV_SET16:=0D + case R_RISCV_SET32:=0D + break;=0D +=0D + default:=0D + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported EL= F EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_= info));=0D + }=0D +}=0D =0D //=0D // Elf functions interface implementation=0D @@ -481,6 +630,7 @@ ScanSections64 ( switch (mEhdr->e_machine) {=0D case EM_X86_64:=0D case EM_AARCH64:=0D + case EM_RISCV64:=0D mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADERS64);=0D break;=0D default:=0D @@ -690,6 +840,11 @@ ScanSections64 ( NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_AARCH64;=0D NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M= AGIC;=0D break;=0D + case EM_RISCV64:=0D + NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_RISCV64;=0D + NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M= AGIC;=0D + break;=0D +=0D default:=0D VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_m= achine);=0D NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_X64;=0D @@ -894,12 +1049,18 @@ WriteSections64 ( SymName =3D (const UINT8 *)"";=0D }=0D =0D - Error (NULL, 0, 3000, "Invalid",=0D - "%s: Bad definition for symbol '%s'@%#llx or unsupported = symbol type. "=0D - "For example, absolute and undefined symbols are not supp= orted.",=0D - mInImageName, SymName, Sym->st_value);=0D + //=0D + // Skip error on EM_RISCV64 becasue no symble name is built=0D + // from RISC-V toolchain.=0D + //=0D + if (mEhdr->e_machine !=3D EM_RISCV64) {=0D + Error (NULL, 0, 3000, "Invalid",=0D + "%s: Bad definition for symbol '%s'@%#llx or unsupporte= d symbol type. "=0D + "For example, absolute and undefined symbols are not su= pported.",=0D + mInImageName, SymName, Sym->st_value);=0D =0D - exit(EXIT_FAILURE);=0D + exit(EXIT_FAILURE);=0D + }=0D }=0D SymShdr =3D GetShdrByIndex(Sym->st_shndx);=0D =0D @@ -1151,6 +1312,11 @@ WriteSections64 ( default:=0D Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupp= orted ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE= (Rel->r_info));=0D }=0D + } else if (mEhdr->e_machine =3D=3D EM_RISCV64) {=0D + //=0D + // Write section for RISC-V 64 architecture.=0D + //=0D + WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym);=0D } else {=0D Error (NULL, 0, 3000, "Invalid", "Not a supported machine type")= ;=0D }=0D @@ -1170,6 +1336,7 @@ WriteRelocations64 ( UINT32 Index;=0D EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;=0D EFI_IMAGE_DATA_DIRECTORY *Dir;=0D + UINT32 RiscVRelType;=0D =0D for (Index =3D 0; Index < mEhdr->e_shnum; Index++) {=0D Elf_Shdr *RelShdr =3D GetShdrByIndex(Index);=0D @@ -1276,6 +1443,107 @@ WriteRelocations64 ( default:=0D Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s= unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF= _R_TYPE(Rel->r_info));=0D }=0D + } else if (mEhdr->e_machine =3D=3D EM_RISCV64) {=0D + RiscVRelType =3D ELF_R_TYPE(Rel->r_info);=0D + switch (RiscVRelType) {=0D + case R_RISCV_NONE:=0D + break;=0D +=0D + case R_RISCV_32:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_HIGHLOW);=0D + break;=0D +=0D + case R_RISCV_64:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_DIR64);=0D + break;=0D +=0D + case R_RISCV_HI20:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_RISCV_HI20);=0D + break;=0D +=0D + case R_RISCV_LO12_I:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_RISCV_LOW12I);=0D + break;=0D +=0D + case R_RISCV_LO12_S:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_RISCV_LOW12S);=0D + break;=0D +=0D + case R_RISCV_ADD64:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_ABSOLUTE);=0D + break;=0D +=0D + case R_RISCV_SUB64:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_ABSOLUTE);=0D + break;=0D +=0D + case R_RISCV_ADD32:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_ABSOLUTE);=0D + break;=0D +=0D + case R_RISCV_SUB32:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_ABSOLUTE);=0D + break;=0D +=0D + case R_RISCV_BRANCH:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_ABSOLUTE);=0D + break;=0D +=0D + case R_RISCV_JAL:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_ABSOLUTE);=0D + break;=0D +=0D + case R_RISCV_GPREL_I:=0D + case R_RISCV_GPREL_S:=0D + case R_RISCV_CALL:=0D + case R_RISCV_RVC_BRANCH:=0D + case R_RISCV_RVC_JUMP:=0D + case R_RISCV_RELAX:=0D + case R_RISCV_SUB6:=0D + case R_RISCV_SET6:=0D + case R_RISCV_SET8:=0D + case R_RISCV_SET16:=0D + case R_RISCV_SET32:=0D + case R_RISCV_PCREL_HI20:=0D + case R_RISCV_PCREL_LO12_I:=0D + break;=0D +=0D + default:=0D + Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s u= nsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R= _TYPE(Rel->r_info));=0D + }=0D } else {=0D Error (NULL, 0, 3000, "Not Supported", "This tool does not sup= port relocations for ELF with e_machine %u (processor type).", (unsigned) m= Ehdr->e_machine);=0D }=0D diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 88d7ab8cab..be09a2a8f7 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -3,7 +3,7 @@ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= =0D # Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
=0D # Copyright (c) 2015, Hewlett-Packard Development Company, L.P.
=0D -# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
=0D +# (C) Copyright 2020, Hewlett Packard Enterprise Development LP
=0D # Copyright (c) Microsoft Corporation=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -267,11 +267,12 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # Intel(r) ACPI Compiler from=0D # https://acpica.org/downloads=0D # GCC5 -Linux,Windows- Requires:=0D -# GCC 5 with LTO support, targeting x86_64-lin= ux-gnu, aarch64-linux-gnu, or arm-linux-gnueabi=0D +# GCC 5 with LTO support, targeting x86_64-lin= ux-gnu, aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu=0D # Optional:=0D # Required to build platforms or ACPI tables:= =0D # Intel(r) ACPI Compiler from=0D # https://acpica.org/downloads=0D +#=0D # CLANG35 -Linux,Windows- Requires:=0D # Clang v3.5 or later, and GNU binutils target= ing aarch64-linux-gnu or arm-linux-gnueabi=0D # Optional:=0D @@ -1946,6 +1947,7 @@ DEFINE GCC_IA32_RC_FLAGS =3D -I binary -O e= lf32-i386 -B i386 DEFINE GCC_X64_RC_FLAGS =3D -I binary -O elf64-x86-64 -B= i386 --rename-section .data=3D.hii=0D DEFINE GCC_ARM_RC_FLAGS =3D -I binary -O elf32-littlearm -B= arm --rename-section .data=3D.hii=0D DEFINE GCC_AARCH64_RC_FLAGS =3D -I binary -O elf64-littleaarch64 -B= aarch64 --rename-section .data=3D.hii=0D +DEFINE GCC_RISCV64_RC_FLAGS =3D -I binary -O elf64-littleriscv -B= riscv --rename-section .data=3D.hii=0D =0D # GCC Build Flag for included header file list generation=0D DEFINE GCC_DEPS_FLAGS =3D -MMD -MF $@.deps=0D @@ -2020,6 +2022,22 @@ DEFINE GCC5_ARM_ASLDLINK_FLAGS =3D DEF(GCC49_A= RM_ASLDLINK_FLAGS) DEFINE GCC5_AARCH64_ASLDLINK_FLAGS =3D DEF(GCC49_AARCH64_ASLDLINK_FLAGS)= =0D DEFINE GCC5_ASLCC_FLAGS =3D DEF(GCC49_ASLCC_FLAGS) -fno-lto=0D =0D +DEFINE GCC5_RISCV_ALL_CC_FLAGS =3D -g -fshort-wchar -fn= o-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdat= a-sections -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=3D$(BASE_NAME= )Strings -msmall-data-limit=3D0=0D +DEFINE GCC5_RISCV_ALL_DLINK_COMMON =3D -nostdlib -Wl,-n,-q,= --gc-sections -z common-page-size=3D0x40=0D +DEFINE GCC5_RISCV_ALL_DLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_D= LINK_COMMON) -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Wl,-= Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map=0D +DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS =3D -Wl,--defsym=3DPECOF= F_HEADER_SIZE=3D0x220,--script=3D$(EDK_TOOLS_PATH)/Scripts/GccBase.lds=0D +DEFINE GCC5_RISCV_ALL_ASM_FLAGS =3D -c -x assembler -ima= cros $(DEST_DIR_DEBUG)/AutoGen.h=0D +DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE =3D -Wno-tautological-co= mpare -Wno-pointer-compare=0D +=0D +DEFINE GCC5_RISCV_OPENSBI_TYPES =3D -DOPENSBI_EXTERNAL_S= BI_TYPES=3DOpensbiTypes.h=0D +=0D +DEFINE GCC5_RISCV64_ARCH =3D rv64imafdc=0D +DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_CO= MMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable=0D +DEFINE GCC5_RISCV64_CC_FLAGS =3D DEF(GCC5_RISCV_ALL_CC_FLAGS= ) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) DEF(GCC5_RISCV_OPENSBI_TYPES= ) -march=3DDEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-sta= ck-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-unused-but-s= et-variable -fpack-struct=3D8 -mcmodel=3Dmedany -mabi=3Dlp64 -mno-relax=0D +DEFINE GCC5_RISCV64_DLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_FL= AGS) -Wl,-melf64lriscv,--oformat=3Delf64-littleriscv,--no-relax=0D +DEFINE GCC5_RISCV64_DLINK2_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK2_F= LAGS)=0D +DEFINE GCC5_ASM_FLAGS =3D DEF(GCC5_RISCV_ALL_ASM_FLAG= S) -march=3DDEF(GCC5_RISCV64_ARCH) -mcmodel=3Dmedany -mabi=3Dlp64=0D +=0D ##########################################################################= ##########=0D #=0D # GCC 4.8 - This configuration is used to compile under Linux to produce=0D @@ -2464,6 +2482,37 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS =3D -z common-pa= ge-size=3D0x20 NOOPT_GCC5_AARCH64_DLINK_FLAGS =3D DEF(GCC5_AARCH64_DLINK_FLAGS) -O0=0D NOOPT_GCC5_AARCH64_DLINK_XIPFLAGS =3D -z common-page-size=3D0x20 -O0=0D =0D +##########################################################################= ##########=0D +#=0D +# GCC RISC-V This configuration is used to compile under Linux to produce= =0D +# PE/COFF binaries using GCC RISC-V tool chain=0D +#=0D +##########################################################################= ##########=0D +=0D +##################=0D +# GCC5 RISCV64 definitions=0D +##################=0D +*_GCC5_RISCV64_OBJCOPY_PATH =3D ENV(GCC5_RISCV64_PREFIX)objcopy=0D +*_GCC5_RISCV64_CC_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc=0D +*_GCC5_RISCV64_SLINK_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc-ar=0D +*_GCC5_RISCV64_DLINK_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc=0D +*_GCC5_RISCV64_ASLDLINK_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc=0D +*_GCC5_RISCV64_ASM_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc=0D +*_GCC5_RISCV64_PP_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc=0D +*_GCC5_RISCV64_VFRPP_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc=0D +*_GCC5_RISCV64_ASLCC_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc=0D +*_GCC5_RISCV64_ASLPP_PATH =3D ENV(GCC5_RISCV64_PREFIX)gcc=0D +*_GCC5_RISCV64_RC_PATH =3D ENV(GCC5_RISCV64_PREFIX)objcopy=0D +=0D +*_GCC5_RISCV64_ASLCC_FLAGS =3D DEF(GCC_ASLCC_FLAGS)=0D +*_GCC5_RISCV64_ASLDLINK_FLAGS =3D DEF(GCC5_RISCV32_RISCV64_ASLDLINK_= FLAGS)=0D +*_GCC5_RISCV64_ASM_FLAGS =3D DEF(GCC5_ASM_FLAGS)=0D +*_GCC5_RISCV64_CC_FLAGS =3D DEF(GCC5_RISCV64_CC_FLAGS) -save-t= emps=0D +*_GCC5_RISCV64_DLINK_FLAGS =3D DEF(GCC5_RISCV64_DLINK_FLAGS)=0D +*_GCC5_RISCV64_DLINK2_FLAGS =3D DEF(GCC5_RISCV64_DLINK2_FLAGS)=0D +*_GCC5_RISCV64_RC_FLAGS =3D DEF(GCC_RISCV64_RC_FLAGS)=0D +*_GCC5_RISCV64_OBJCOPY_FLAGS =3D=0D +=0D ##########################################################################= ##########=0D #=0D # CLANG35 - This configuration is used to compile under Linux to produce= =0D diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/= Python/Common/DataType.py index 8d80b41089..fb88f20cc4 100644 --- a/BaseTools/Source/Python/Common/DataType.py +++ b/BaseTools/Source/Python/Common/DataType.py @@ -3,6 +3,7 @@ #=0D # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
=0D # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D +# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. = All rights reserved.
=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D ##=0D @@ -52,7 +53,9 @@ TAB_ARCH_ARM =3D 'ARM' TAB_ARCH_EBC =3D 'EBC'=0D TAB_ARCH_AARCH64 =3D 'AARCH64'=0D =0D -ARCH_SET_FULL =3D {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC= , TAB_ARCH_AARCH64, TAB_ARCH_COMMON}=0D +TAB_ARCH_RISCV64 =3D 'RISCV64'=0D +=0D +ARCH_SET_FULL =3D {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC= , TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON}=0D =0D SUP_MODULE_BASE =3D 'BASE'=0D SUP_MODULE_SEC =3D 'SEC'=0D diff --git a/BaseTools/Source/Python/build/buildoptions.py b/BaseTools/Sour= ce/Python/build/buildoptions.py index 61ab2db9a4..094af4e2a8 100644 --- a/BaseTools/Source/Python/build/buildoptions.py +++ b/BaseTools/Source/Python/build/buildoptions.py @@ -3,7 +3,7 @@ #=0D # Copyright (c) 2014, Hewlett-Packard Development Company, L.P.
=0D # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
= =0D -# Copyright (c) 2018, Hewlett Packard Enterprise Development, L.P.
=0D +# Copyright (c) 2018 - 2020, Hewlett Packard Enterprise Development, L.P.=
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -40,8 +40,8 @@ class MyOptionParser(): =0D def GetOption(self):=0D Parser =3D OptionParser(description=3D__copyright__, version=3D__v= ersion__, prog=3D"build.exe", usage=3D"%prog [options] [all|fds|genc|genmak= e|clean|cleanall|cleanlib|modules|libraries|run]")=0D - Parser.add_option("-a", "--arch", action=3D"append", type=3D"choic= e", choices=3D['IA32', 'X64', 'EBC', 'ARM', 'AARCH64'], dest=3D"TargetArch"= ,=0D - help=3D"ARCHS is one of list: IA32, X64, ARM, AARCH64 or EBC, = which overrides target.txt's TARGET_ARCH definition. To specify more archs,= please repeat this option.")=0D + Parser.add_option("-a", "--arch", action=3D"append", type=3D"choic= e", choices=3D['IA32', 'X64', 'EBC', 'ARM', 'AARCH64', 'RISCV64'], dest=3D"= TargetArch",=0D + help=3D"ARCHS is one of list: IA32, X64, ARM, AARCH64, RISCV64= or EBC, which overrides target.txt's TARGET_ARCH definition. To specify mo= re archs, please repeat this option.")=0D Parser.add_option("-p", "--platform", action=3D"callback", type=3D= "string", dest=3D"PlatformFile", callback=3DSingleCheckCallback,=0D help=3D"Build the platform specified by the DSC file name argu= ment, overriding target.txt's ACTIVE_PLATFORM definition.")=0D Parser.add_option("-m", "--module", action=3D"callback", type=3D"s= tring", dest=3D"ModuleFile", callback=3DSingleCheckCallback,=0D --=20 2.25.0