From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by mx.groups.io with SMTP id smtpd.web12.6349.1587574302328501462 for ; Wed, 22 Apr 2020 09:51:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=kweISvY1; spf=pass (domain: nuviainc.com, ip: 209.85.221.67, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f67.google.com with SMTP id x17so2529749wrt.5 for ; Wed, 22 Apr 2020 09:51:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=QZXE12RVJEr3DSl3PwZ7qDEt1+DHEGtIHYGKiRozdEk=; b=kweISvY1oI/qOQntEGQ+izNWwvBtHBxVRMWF1i17w8IJoTlQwsOrWzUus1f34B9Xx1 mSCx4EBUJ6RSe1tX6+kIodinEHCazlV2gSRL5zSq6rawCTHD9erS+ugmvsL74q+uxh7m VwJujbWwjU4XTSLxHpQHi7F4r567WaRwS5GbFv6lBZEmX2UzqELt8kS8yl0DMhk761He Tpz0VCLIq6TaDVy5sEcN2rtc/nGEi6Om1ZVPTmIDAZABdQwzj0NZzACdoDBEwzfnC6jc jg5AL8widy6IJJZGObC40DfXJgaZQum+lnygeYSz7jbdtUkRiLbveRBniN7K6VMMnDcM 8etg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=QZXE12RVJEr3DSl3PwZ7qDEt1+DHEGtIHYGKiRozdEk=; b=cyV81dRAYYLpvGVEFteOUYfGZCFqrAe9v5YeGGYBad+xxOgtZP01ycDM0DXBHQ3ZN6 Z+rmhAzEu68Cj3HqiIGJ3MNJv9bZ9aCeOmcGQJlIY91J7D+BoodzlaoYBKzfW0Hzoq9Z skoDRRwVSrJtkShXC4W+oDgA2SwiwZYY0+Nq8d4neNFo12J4O4Nmr/mha+FlgGIa93sQ RNd4xwqmJHPSW1gvwHX30bmYKdP8ggdJj0yOpHANjYXTv/5sHINivtQcz+jaPtmAA2q+ sf0oDaEfW1L5vP/R7Mp5LZpKnhKncltLMmGHJWJy72O7DIlt9eNTfiI0L7IdGu5QVgpu sEzw== X-Gm-Message-State: AGi0PuaVfTRjkvo1As2OqVur7BgEVxmnm0vusrZQg68AtelkOfc9UmxH E0penKJ3NnHlmf57IfHLlNlivQ== X-Google-Smtp-Source: APiQypJH2x1kWcaFkkCPgKz8fbl+jB9Fjsl3vgvAzFzb/PzyBYNyvDeuTXp3ynPMS++5Elz3ZNkoNg== X-Received: by 2002:a5d:6688:: with SMTP id l8mr32764905wru.179.1587574300804; Wed, 22 Apr 2020 09:51:40 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id g15sm9355471wrp.96.2020.04.22.09.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2020 09:51:40 -0700 (PDT) Date: Wed, 22 Apr 2020 17:51:37 +0100 From: "Leif Lindholm" To: Pankaj Bansal Cc: Meenakshi Aggarwal , Michael D Kinney , devel@edk2.groups.io, Varun Sethi , Samer El-Haj-Mahmoud , Jon Nettleton , Ard Biesheuvel Subject: Re: [PATCH edk2-platforms v3 07/24] Silicon/NXP: remove print information from Soc Message-ID: <20200422165137.GQ14075@vanye> References: <20200415121342.9246-1-pankaj.bansal@oss.nxp.com> <20200415121342.9246-8-pankaj.bansal@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <20200415121342.9246-8-pankaj.bansal@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Apr 15, 2020 at 17:43:25 +0530, Pankaj Bansal wrote: > From: Pankaj Bansal > > The Soc info being printed can be removed from SOC lib. > We are in the process of implementing PEI Phase. > After PEI phase implementation this info would be printed in > common PEIM based on the information retrieved from PPIs. > e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and "cluster" is still misspelled. I can fix that when committing. / Leif > core info. > > Signed-off-by: Pankaj Bansal > Reviewed-by: Leif Lindholm > --- > > Notes: > - remove CpuMaskNext definition > > Silicon/NXP/Library/SocLib/NxpChassis.h | 26 +--- > Silicon/NXP/Library/SocLib/Chassis.c | 144 -------------------- > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 16 +-- > 3 files changed, 2 insertions(+), 184 deletions(-) > > diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h > index 99f6439d8f35..a11acf71563e 100644 > --- a/Silicon/NXP/Library/SocLib/NxpChassis.h > +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h > @@ -1,7 +1,7 @@ > /** @file > * Header defining the Base addresses, sizes, flags etc for chassis 1 > * > -* Copyright 2017-2019 NXP > +* Copyright 2017-2020 NXP > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -54,14 +54,6 @@ typedef struct { > UINTN SdhcClk; > } SOC_CLOCK_INFO; > > -/* > - * Print Soc information > - */ > -VOID > -PrintSoc ( > - VOID > - ); > - > /* > * Initialize Clock structure > */ > @@ -79,22 +71,6 @@ SmmuInit ( > VOID > ); > > -/* > - * Print CPU information > - */ > -VOID > -PrintCpuInfo ( > - VOID > - ); > - > -/* > - * Dump RCW (Reset Control Word) on console > - */ > -VOID > -PrintRCW ( > - VOID > - ); > - > UINT32 > InitiatorType ( > IN UINT32 Cluster, > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c > index b8a8118c5e24..adca7b8dd413 100644 > --- a/Silicon/NXP/Library/SocLib/Chassis.c > +++ b/Silicon/NXP/Library/SocLib/Chassis.c > @@ -204,79 +204,6 @@ QoriqCoreToType ( > return EFI_NOT_FOUND; /* cannot identify the cluster */ > } > > -STATIC > -UINTN > -CpuMaskNext ( > - IN UINTN Cpu, > - IN UINTN Mask > - ) > -{ > - for (Cpu++; !((1 << Cpu) & Mask); Cpu++); > - > - return Cpu; > -} > - > -/* > - * Print CPU information > - */ > -VOID > -PrintCpuInfo ( > - VOID > - ) > -{ > - SYS_INFO SysInfo; > - UINTN CoreIndex; > - UINTN Core; > - UINT32 Type; > - UINT32 NumCpus; > - UINT32 Mask; > - CHAR8 *CoreName; > - > - GetSysInfo (&SysInfo); > - DEBUG ((DEBUG_INIT, "Clock Configuration:")); > - > - NumCpus = CpuNumCores (); > - Mask = CpuMask (); > - > - for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask); > - CoreIndex < NumCpus; > - CoreIndex++, Core = CpuMaskNext(Core, Mask)) > - { > - if (!(CoreIndex % 3)) { > - DEBUG ((DEBUG_INIT, "\n ")); > - } > - > - Type = TP_ITYP_VERSION (QoriqCoreToType (Core)); > - switch (Type) { > - case TY_ITYP_VERSION_A7: > - CoreName = "A7"; > - break; > - case TY_ITYP_VERSION_A53: > - CoreName = "A53"; > - break; > - case TY_ITYP_VERSION_A57: > - CoreName = "A57"; > - break; > - case TY_ITYP_VERSION_A72: > - CoreName = "A72"; > - break; > - default: > - CoreName = " Unknown Core "; > - } > - DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", > - Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ)); > - } > - > - DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ)); > - DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ)); > - > - if (SysInfo.FreqFman[0] != 0) { > - DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ)); > - } > - > - DEBUG ((DEBUG_INIT, "\n")); > -} > - > /* > * Return system bus frequency > */ > @@ -307,77 +234,6 @@ GetSdxcFrequency ( > return SocSysInfo.FreqSdhc; > } > > -/* > - * Print Soc information > - */ > -VOID > -PrintSoc ( > - VOID > - ) > -{ > - CHAR8 Buf[20]; > - CCSR_GUR *GurBase; > - UINTN Count; > - // > - // Svr : System Version Register > - // > - UINTN Svr; > - UINTN Ver; > - > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - > - Svr = GurRead ((UINTN)&GurBase->Svr); > - Ver = SVR_SOC_VER (Svr); > - > - for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { > - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) { > - AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name); > - > - if (IS_E_PROCESSOR (Svr)) { > - AsciiStrCatS (Buf, sizeof (Buf), "E"); > - } > - break; > - } > - } > - > - DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n", > - Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr))); > - > - return; > -} > - > -/* > - * Dump RCW (Reset Control Word) on console > - */ > -VOID > -PrintRCW ( > - VOID > - ) > -{ > - CCSR_GUR *Base; > - UINTN Count; > - > - Base = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - > - /* > - * Display the RCW, so that no one gets confused as to what RCW > - * we're actually using for this boot. > - */ > - > - DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):")); > - for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) { > - UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]); > - > - if ((Count % 4) == 0) { > - DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4)); > - } > - > - DEBUG ((DEBUG_INIT, " %08x", Rcw)); > - } > - > - DEBUG ((DEBUG_INIT, "\n")); > -} > - > /* > * Setup SMMU in bypass mode > * and also set its pagesize > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > index bfb8b8cb339a..687a1d940066 100644 > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > @@ -1,7 +1,7 @@ > /** @Soc.c > SoC specific Library containg functions to initialize various SoC components > > - Copyright 2017-2019 NXP > + Copyright 2017-2020 NXP > > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -131,10 +131,6 @@ GetSysInfo ( > > /** > Function to initialize SoC specific constructs > - CPU Info > - SoC Personality > - Board Personality > - RCW prints > **/ > VOID > SocInit ( > @@ -147,16 +143,6 @@ SocInit ( > // Early init serial Port to get board information. > // > SerialPortInitialize (); > - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n", > - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__)); > - > - PrintCpuInfo (); > - > - // > - // Print Reset control Word > - // > - PrintRCW (); > - PrintSoc (); > > return; > } > -- > 2.17.1 >