* [PATCH v2 1/3] MdeModulePkg/Logo
2020-04-26 14:40 [PATCH v2 0/3] MdeModulePkg changes for RISC-V edk2 port Abner Chang
@ 2020-04-26 14:40 ` Abner Chang
2020-04-26 14:40 ` [PATCH v2 2/3] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
2020-04-26 14:40 ` [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
2 siblings, 0 replies; 6+ messages in thread
From: Abner Chang @ 2020-04-26 14:40 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Gilbert Chen, Leif Lindholm, Zhichao Gao, Ray Ni
Add RISCV64 Arch.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Zhichao Gao <zhichao.gao@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdeModulePkg/Logo/Logo.inf | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf
index 018202582e..70a66cae98 100644
--- a/MdeModulePkg/Logo/Logo.inf
+++ b/MdeModulePkg/Logo/Logo.inf
@@ -2,6 +2,8 @@
# The default logo bitmap picture shown on setup screen, which is corresponding to gEfiDefaultBmpLogoGuid.
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -19,7 +21,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Binaries]
--
2.25.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
2020-04-26 14:40 [PATCH v2 0/3] MdeModulePkg changes for RISC-V edk2 port Abner Chang
2020-04-26 14:40 ` [PATCH v2 1/3] MdeModulePkg/Logo Abner Chang
@ 2020-04-26 14:40 ` Abner Chang
2020-05-25 1:49 ` [edk2-devel] " Guomin Jiang
2020-04-26 14:40 ` [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
2 siblings, 1 reply; 6+ messages in thread
From: Abner Chang @ 2020-04-26 14:40 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Gilbert Chen, Leif Lindholm, Hao A Wu, Liming Gao
Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Hao A Wu <hao.a.wu@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
index 942eda235c..8bf5035a69 100644
--- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
@@ -5,6 +5,7 @@
# the capsule runtime services are ready.
#
# Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -21,20 +22,20 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources]
CapsuleService.c
CapsuleService.h
-[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64]
+[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
SaveLongModeContext.c
-[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64]
+[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
CapsuleCache.c
-[Sources.Ia32, Sources.X64, Sources.EBC]
+[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
CapsuleReset.c
[Sources.ARM, Sources.AARCH64]
--
2.25.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [edk2-devel] [PATCH v2 2/3] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
2020-04-26 14:40 ` [PATCH v2 2/3] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
@ 2020-05-25 1:49 ` Guomin Jiang
0 siblings, 0 replies; 6+ messages in thread
From: Guomin Jiang @ 2020-05-25 1:49 UTC (permalink / raw)
To: devel@edk2.groups.io, abner.chang@hpe.com
Cc: Gilbert Chen, Leif Lindholm, Wu, Hao A, Gao, Liming
The patch is good to me.
Reviewed-by: Guomin Jiang <guomin.jiang@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abner
> Chang
> Sent: Sunday, April 26, 2020 10:40 PM
> To: devel@edk2.groups.io
> Cc: abner.chang@hpe.com; Gilbert Chen <gilbert.chen@hpe.com>; Leif
> Lindholm <leif.lindholm@linaro.org>; Wu, Hao A <hao.a.wu@intel.com>;
> Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-devel] [PATCH v2 2/3] MdeModulePkg/CapsuleRuntimeDxe:
> Add RISCV64 arch.
>
> Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> Acked-by: Hao A Wu <hao.a.wu@intel.com>
>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> .../Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git
> a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> index 942eda235c..8bf5035a69 100644
> ---
> a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +++
> b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> @@ -5,6 +5,7 @@
> # the capsule runtime services are ready.
>
> #
>
> # Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights
> reserved.<BR>
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> ##
>
> @@ -21,20 +22,20 @@
> #
>
> # The following information is for reference only and not required by the
> build tools.
>
> #
>
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
>
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
>
> #
>
>
>
> [Sources]
>
> CapsuleService.c
>
> CapsuleService.h
>
>
>
> -[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64]
>
> +[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64,
> Sources.RISCV64]
>
> SaveLongModeContext.c
>
>
>
> -[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64]
>
> +[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64,
> Sources.RISCV64]
>
> CapsuleCache.c
>
>
>
> -[Sources.Ia32, Sources.X64, Sources.EBC]
>
> +[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
>
> CapsuleReset.c
>
>
>
> [Sources.ARM, Sources.AARCH64]
>
> --
> 2.25.0
>
>
> -=-=-=-=-=-=
> Groups.io Links: You receive all messages sent to this group.
>
> View/Reply Online (#58149): https://edk2.groups.io/g/devel/message/58149
> Mute This Topic: https://groups.io/mt/73284218/4399222
> Group Owner: devel+owner@edk2.groups.io
> Unsubscribe: https://edk2.groups.io/g/devel/unsub
> [guomin.jiang@intel.com]
> -=-=-=-=-=-=
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
2020-04-26 14:40 [PATCH v2 0/3] MdeModulePkg changes for RISC-V edk2 port Abner Chang
2020-04-26 14:40 ` [PATCH v2 1/3] MdeModulePkg/Logo Abner Chang
2020-04-26 14:40 ` [PATCH v2 2/3] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
@ 2020-04-26 14:40 ` Abner Chang
2020-04-29 11:45 ` [edk2-devel] " Dandan Bi
2 siblings, 1 reply; 6+ messages in thread
From: Abner Chang @ 2020-04-26 14:40 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Gilbert Chen, Leif Lindholm, Dandan Bi, Liming Gao
Implementation of RISC-V DxeIPL.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 6 +-
.../Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 74 +++++++++++++++++++
2 files changed, 79 insertions(+), 1 deletion(-)
create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index 98bc17fc9d..3f17028546 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -7,6 +7,7 @@
#
# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +26,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64
#
[Sources]
@@ -49,6 +50,9 @@
[Sources.ARM, Sources.AARCH64]
Arm/DxeLoadFunc.c
+[Sources.RISCV64]
+ RiscV64/DxeLoadFunc.c
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
new file mode 100644
index 0000000000..2ce52eb0ec
--- /dev/null
+++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
@@ -0,0 +1,74 @@
+/** @file
+ RISC-V specific functionality for DxeLoad.
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "DxeIpl.h"
+
+/**
+ Transfers control to DxeCore.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+HandOffToDxeCore (
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+ VOID *BaseOfStack;
+ VOID *TopOfStack;
+ EFI_STATUS Status;
+ //
+ //
+ // Allocate 128KB for the Stack
+ //
+ BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
+ if (BaseOfStack == NULL) {
+ DEBUG((DEBUG_ERROR, "%a: Can't allocate memory for stack.", __FUNCTION__));
+ ASSERT(FALSE);
+ }
+
+ //
+ // Compute the top of the stack we were allocated. Pre-allocate a UINTN
+ // for safety.
+ //
+ TopOfStack = (VOID *)((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
+ TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
+
+ //
+ // End of PEI phase signal
+ //
+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
+ if (EFI_ERROR (Status)) {
+ DEBUG((DEBUG_ERROR, "%a: Fail to signal End of PEI event.", __FUNCTION__));
+ ASSERT(FALSE);
+ }
+ //
+ // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
+ //
+ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE);
+
+ DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at %x\n", BaseOfStack, TopOfStack));
+
+ //
+ // Transfer the control to the entry point of DxeCore.
+ //
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
+ HobList.Raw,
+ NULL,
+ TopOfStack
+ );
+}
+
--
2.25.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [edk2-devel] [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
2020-04-26 14:40 ` [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
@ 2020-04-29 11:45 ` Dandan Bi
0 siblings, 0 replies; 6+ messages in thread
From: Dandan Bi @ 2020-04-29 11:45 UTC (permalink / raw)
To: devel@edk2.groups.io, abner.chang@hpe.com
Cc: Gilbert Chen, Leif Lindholm, Gao, Liming
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
Thanks,
Dandan
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Sunday, April 26, 2020 10:40 PM
> To: devel@edk2.groups.io
> Cc: abner.chang@hpe.com; Gilbert Chen <gilbert.chen@hpe.com>; Leif
> Lindholm <leif.lindholm@linaro.org>; Bi, Dandan <dandan.bi@intel.com>;
> Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-devel] [PATCH v2 3/3] MdeModulePkg/DxeIplPeim : RISC-V
> platform level DxeIPL
>
> Implementation of RISC-V DxeIPL.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
> Cc: Dandan Bi <dandan.bi@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 6 +-
> .../Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 74 +++++++++++++++++++
> 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644
> MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> index 98bc17fc9d..3f17028546 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> @@ -7,6 +7,7 @@
> # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> #
> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>+# Copyright
> (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> # # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -25,7 +26,7 @@
> # # The following information is for reference only and not required by the
> build tools. #-# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build
> only) AARCH64+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for
> build only) AARCH64 RISCV64 # [Sources]@@ -49,6 +50,9 @@
> [Sources.ARM, Sources.AARCH64] Arm/DxeLoadFunc.c
> +[Sources.RISCV64]+ RiscV64/DxeLoadFunc.c+ [Packages]
> MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.decdiff --git
> a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> new file mode 100644
> index 0000000000..2ce52eb0ec
> --- /dev/null
> +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
> @@ -0,0 +1,74 @@
> +/** @file+ RISC-V specific functionality for DxeLoad.++ Copyright (c) 2020,
> Hewlett Packard Enterprise Development LP. All rights reserved.<BR>++
> SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#include
> "DxeIpl.h"++/**+ Transfers control to DxeCore.++ This function performs a
> CPU architecture specific operations to execute+ the entry point of DxeCore
> with the parameters of HobList.+ It also installs EFI_END_OF_PEI_PPI to
> signal the end of PEI phase.++ @param DxeCoreEntryPoint The entry
> point of DxeCore.+ @param HobList The start of HobList passed to
> DxeCore.++**/+VOID+HandOffToDxeCore (+ IN EFI_PHYSICAL_ADDRESS
> DxeCoreEntryPoint,+ IN EFI_PEI_HOB_POINTERS HobList+ )+{+ VOID
> *BaseOfStack;+ VOID *TopOfStack;+ EFI_STATUS
> Status;+ //+ //+ // Allocate 128KB for the Stack+ //+ BaseOfStack =
> AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));+ if (BaseOfStack ==
> NULL) {+ DEBUG((DEBUG_ERROR, "%a: Can't allocate memory for stack.",
> __FUNCTION__));+ ASSERT(FALSE);+ }++ //+ // Compute the top of the
> stack we were allocated. Pre-allocate a UINTN+ // for safety.+ //+
> TopOfStack = (VOID *)((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES
> (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);+ TopOfStack =
> ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);++ //+ // End of
> PEI phase signal+ //+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);+
> if (EFI_ERROR (Status)) {+ DEBUG((DEBUG_ERROR, "%a: Fail to signal End of
> PEI event.", __FUNCTION__));+ ASSERT(FALSE);+ }+ //+ // Update the
> contents of BSP stack HOB to reflect the real stack info passed to DxeCore.+
> //+ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack,
> STACK_SIZE);++ DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack
> pointer at %x\n", BaseOfStack, TopOfStack));++ //+ // Transfer the control
> to the entry point of DxeCore.+ //+ SwitchStack (+
> (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,+
> HobList.Raw,+ NULL,+ TopOfStack+ );+}+--
> 2.25.0
>
>
> -=-=-=-=-=-=
> Groups.io Links: You receive all messages sent to this group.
>
> View/Reply Online (#58150): https://edk2.groups.io/g/devel/message/58150
> Mute This Topic: https://groups.io/mt/73284221/1768738
> Group Owner: devel+owner@edk2.groups.io
> Unsubscribe: https://edk2.groups.io/g/devel/unsub [dandan.bi@intel.com]
> -=-=-=-=-=-=
^ permalink raw reply [flat|nested] 6+ messages in thread