From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.2024.1588210683909188472 for ; Wed, 29 Apr 2020 18:38:04 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: chasel.chiu@intel.com) IronPort-SDR: aBRwayfr/26aKdbpgKcwJZWJzX05f5ENRDGSR+k+j3D4Ogul5GLIX1nVvIoUol56huSUZhpsdQ FGRtsQ8SDsjA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 18:38:02 -0700 IronPort-SDR: GbOAdHRx48QBF2I9a9wOGZVdg+vjevErCOs3sHV/CJV9ByF5H9isMP+8D2PSd6M0rfaatlmBYh b4RAOcK9GAoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,333,1583222400"; d="scan'208";a="261611817" Received: from cchiu4-mobl1.gar.corp.intel.com ([10.215.151.72]) by orsmga006.jf.intel.com with ESMTP; 29 Apr 2020 18:38:00 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Maurice Ma , Nate DeSimone , Star Zeng Subject: [PATCH] IntelFsp2Pkg: Support Multi-Phase silicon initialization. Date: Thu, 30 Apr 2020 09:37:45 +0800 Message-Id: <20200430013745.18528-1-chasel.chiu@intel.com> X-Mailer: git-send-email 2.13.3.windows.1 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698 To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Cc: Maurice Ma Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h index 16f43a1273..3474bac1de 100644 --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -1,8 +1,8 @@ /** @file Intel FSP Header File definition from Intel Firmware Support Package External - Architecture Specification v2.0. + Architecture Specification v2.0 and above. - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -110,6 +110,12 @@ typedef struct { /// Byte 0x44: The offset for the API to initialize the CPU and chipset. /// UINT32 FspSiliconInitEntryOffset; + /// + /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization. + /// This value is only valid if FSP HeaderRevision is >= 5. + /// If the value is set to 0x00000000, then this API is not available in this component. + /// + UINT32 FspMultiPhaseSiInitEntryOffset; } FSP_INFO_HEADER; /// -- 2.13.3.windows.1