* [PATCH edk2-platforms v2 0/2] move obsolete platform drivers out of core edk2
@ 2020-04-30 8:25 Ard Biesheuvel
2020-04-30 8:25 ` [PATCH edk2-platforms v2 1/2] Platform/ARM/VExpressPkg: incorporate PL180 driver Ard Biesheuvel
2020-04-30 8:25 ` [PATCH edk2-platforms v2 2/2] Platform/ARM/JunoPkg: incorporate SiI3132 SATA controller driver Ard Biesheuvel
0 siblings, 2 replies; 5+ messages in thread
From: Ard Biesheuvel @ 2020-04-30 8:25 UTC (permalink / raw)
To: devel; +Cc: leif, Ard Biesheuvel
This is a followup to two patches I sent out separately yesterday, and to
the subsequent discussion regarding annotating obsolete drivers as unfit
for reuse if they don't follow the UEFI driver model.
Changes since v1:
- use gEmbeddedMmcHostProtocolGuid not gEdkiiMmcHostProtocolGuid
- add WARNING comment blocks to all files to document the fact that these
files are only kept for sentimental reasons
Ard Biesheuvel (2):
Platform/ARM/VExpressPkg: incorporate PL180 driver
Platform/ARM/JunoPkg: incorporate SiI3132 SATA controller driver
Platform/ARM/JunoPkg/ArmJuno.dec | 3 +
Platform/ARM/JunoPkg/ArmJuno.dsc | 2 +-
Platform/ARM/JunoPkg/ArmJuno.fdf | 2 +-
.../Drivers/SataSiI3132Dxe/ComponentName.c | 179 ++++
.../Drivers/SataSiI3132Dxe/SataSiI3132.c | 546 ++++++++++++
.../Drivers/SataSiI3132Dxe/SataSiI3132.h | 286 ++++++
.../Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf | 38 +
.../SataSiI3132Dxe/SiI3132AtaPassThru.c | 834 ++++++++++++++++++
.../ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc | 6 +-
.../ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf | 2 +-
.../VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 6 +-
.../VExpressPkg/ArmVExpress-FVP-AArch64.fdf | 2 +-
Platform/ARM/VExpressPkg/ArmVExpressPkg.dec | 4 +
.../Drivers/PL180MciDxe/PL180Mci.c | 570 ++++++++++++
.../Drivers/PL180MciDxe/PL180Mci.h | 169 ++++
.../Drivers/PL180MciDxe/PL180MciDxe.inf | 53 ++
16 files changed, 2692 insertions(+), 10 deletions(-)
create mode 100644 Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/ComponentName.c
create mode 100644 Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c
create mode 100644 Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h
create mode 100644 Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
create mode 100644 Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c
create mode 100644 Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c
create mode 100644 Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.h
create mode 100644 Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH edk2-platforms v2 1/2] Platform/ARM/VExpressPkg: incorporate PL180 driver
2020-04-30 8:25 [PATCH edk2-platforms v2 0/2] move obsolete platform drivers out of core edk2 Ard Biesheuvel
@ 2020-04-30 8:25 ` Ard Biesheuvel
2020-04-30 10:06 ` [edk2-devel] " Philippe Mathieu-Daudé
2020-04-30 8:25 ` [PATCH edk2-platforms v2 2/2] Platform/ARM/JunoPkg: incorporate SiI3132 SATA controller driver Ard Biesheuvel
1 sibling, 1 reply; 5+ messages in thread
From: Ard Biesheuvel @ 2020-04-30 8:25 UTC (permalink / raw)
To: devel; +Cc: leif, Ard Biesheuvel
The PL180 SD host controller driver is only used on emulated ARM
platforms, uses an obsolete version of the MMC host protocol and
does not adhere to the UEFI driver model.
Given the above, let's just move it into VExpressPkg where it
belongs.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
---
Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc | 6 +-
Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf | 2 +-
Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 6 +-
Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf | 2 +-
Platform/ARM/VExpressPkg/ArmVExpressPkg.dec | 4 +
Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c | 570 ++++++++++++++++++++
Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.h | 169 ++++++
Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf | 53 ++
8 files changed, 804 insertions(+), 8 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc b/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc
index 2f8021d3eabc..6dad31026aa5 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc
@@ -146,8 +146,8 @@ [PcdsFixedAtBuild.common]
#
# PL180 MMC/SD card controller
#
- gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
- gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
+ gArmVExpressTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
+ gArmVExpressTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
#
@@ -249,7 +249,7 @@ [Components.common]
# Multimedia Card Interface
#
EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
- ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+ Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
# SMSC LAN 9118
EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf b/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf
index 082f80d9996d..64da1102ff07 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf
@@ -103,7 +103,7 @@ [FV.FvMain]
# Multimedia Card Interface
#
INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
- INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+ INF Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
#
# Filesystems
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
index 63d79a488500..a6f536a33228 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
@@ -151,8 +151,8 @@ [PcdsFixedAtBuild.common]
!endif
## PL180 MMC/SD card controller
- gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
- gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
+ gArmVExpressTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
+ gArmVExpressTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
#
# ARM Generic Interrupt Controller
@@ -290,7 +290,7 @@ [Components.common]
# Multimedia Card Interface
#
EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
- ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+ Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
#
# Platform Driver
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
index 8f49ed3dba3c..f18ead75eaec 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
@@ -139,7 +139,7 @@ [FV.FvMain]
# Multimedia Card Interface
#
INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
- INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+ INF Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
#
# SMBIOS Support
diff --git a/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec b/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
index a659cda2e44a..a4e9bfd73eb6 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
+++ b/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
@@ -52,3 +52,7 @@ [PcdsFixedAtBuild.common]
#
gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|""|VOID*|0x00000006
gArmVExpressTokenSpaceGuid.PcdAndroidFastbootProductName|""|VOID*|0x00000007
+
+ ## PL180 MCI
+ gArmVExpressTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000009
+ gArmVExpressTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x0000000A
diff --git a/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c
new file mode 100644
index 000000000000..8526bb41600e
--- /dev/null
+++ b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c
@@ -0,0 +1,570 @@
+/** @file
+ This file implement the MMC Host Protocol for the ARM PrimeCell PL180.
+
+ WARNING:
+ This driver fails to follow the UEFI driver model without a good
+ reason, and only remains in the tree because it is still used by
+ a small number of platforms. It will removed when no longer used.
+ New platforms should not use it, and no one should use this as
+ reference code for developing new drivers.
+
+ Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PL180Mci.h"
+
+#include <Library/DevicePathLib.h>
+#include <Library/BaseMemoryLib.h>
+
+EFI_MMC_HOST_PROTOCOL *gpMmcHost;
+
+// Untested ...
+//#define USE_STREAM
+
+#define MMCI0_BLOCKLEN 512
+#define MMCI0_POW2_BLOCKLEN 9
+#define MMCI0_TIMEOUT 1000
+
+#define SYS_MCI_CARDIN BIT0
+#define SYS_MCI_WPROT BIT1
+
+BOOLEAN
+MciIsPowerOn (
+ VOID
+ )
+{
+ return ((MmioRead32 (MCI_POWER_CONTROL_REG) & MCI_POWER_ON) == MCI_POWER_ON);
+}
+
+EFI_STATUS
+MciInitialize (
+ VOID
+ )
+{
+ MCI_TRACE ("MciInitialize()");
+ return EFI_SUCCESS;
+}
+
+BOOLEAN
+MciIsCardPresent (
+ IN EFI_MMC_HOST_PROTOCOL *This
+ )
+{
+ return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_CARDIN);
+}
+
+BOOLEAN
+MciIsReadOnly (
+ IN EFI_MMC_HOST_PROTOCOL *This
+ )
+{
+ return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_WPROT);
+}
+
+// Convert block size to 2^n
+STATIC
+UINT32
+GetPow2BlockLen (
+ IN UINT32 BlockLen
+ )
+{
+ UINTN Loop;
+ UINTN Pow2BlockLen;
+
+ Loop = 0x8000;
+ Pow2BlockLen = 15;
+ do {
+ Loop = (Loop >> 1) & 0xFFFF;
+ Pow2BlockLen--;
+ } while (Pow2BlockLen && (!(Loop & BlockLen)));
+
+ return Pow2BlockLen;
+}
+
+VOID
+MciPrepareDataPath (
+ IN UINTN TransferDirection
+ )
+{
+ // Set Data Length & Data Timer
+ MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);
+ MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN);
+
+#ifndef USE_STREAM
+ //Note: we are using a hardcoded BlockLen (==512). If we decide to use a variable size, we could
+ // compute the pow2 of BlockLen with the above function GetPow2BlockLen ()
+ MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));
+#else
+ MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | MCI_DATACTL_STREAM_TRANS);
+#endif
+}
+
+EFI_STATUS
+MciSendCommand (
+ IN EFI_MMC_HOST_PROTOCOL *This,
+ IN MMC_CMD MmcCmd,
+ IN UINT32 Argument
+ )
+{
+ UINT32 Status;
+ UINT32 Cmd;
+ UINTN RetVal;
+ UINTN CmdCtrlReg;
+ UINT32 DoneMask;
+
+ RetVal = EFI_SUCCESS;
+
+ if ((MmcCmd == MMC_CMD17) || (MmcCmd == MMC_CMD11)) {
+ MciPrepareDataPath (MCI_DATACTL_CARD_TO_CONT);
+ } else if ((MmcCmd == MMC_CMD24) || (MmcCmd == MMC_CMD20)) {
+ MciPrepareDataPath (MCI_DATACTL_CONT_TO_CARD);
+ } else if (MmcCmd == MMC_CMD6) {
+ MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);
+ MmioWrite32 (MCI_DATA_LENGTH_REG, 64);
+#ifndef USE_STREAM
+ MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | GetPow2BlockLen (64));
+#else
+ MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | MCI_DATACTL_STREAM_TRANS);
+#endif
+ } else if (MmcCmd == MMC_ACMD51) {
+ MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);
+ /* SCR register is 8 bytes long. */
+ MmioWrite32 (MCI_DATA_LENGTH_REG, 8);
+#ifndef USE_STREAM
+ MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | GetPow2BlockLen (8));
+#else
+ MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | MCI_DATACTL_STREAM_TRANS);
+#endif
+ }
+
+ // Create Command for PL180
+ Cmd = (MMC_GET_INDX (MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLE;
+ if (MmcCmd & MMC_CMD_WAIT_RESPONSE) {
+ Cmd |= MCI_CPSM_WAIT_RESPONSE;
+ }
+
+ if (MmcCmd & MMC_CMD_LONG_RESPONSE) {
+ Cmd |= MCI_CPSM_LONG_RESPONSE;
+ }
+
+ // Clear Status register static flags
+ MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
+
+ // Write to command argument register
+ MmioWrite32 (MCI_ARGUMENT_REG, Argument);
+
+ // Write to command register
+ MmioWrite32 (MCI_COMMAND_REG, Cmd);
+
+ DoneMask = (Cmd & MCI_CPSM_WAIT_RESPONSE)
+ ? (MCI_STATUS_CMD_RESPEND | MCI_STATUS_CMD_ERROR)
+ : (MCI_STATUS_CMD_SENT | MCI_STATUS_CMD_ERROR);
+ do {
+ Status = MmioRead32 (MCI_STATUS_REG);
+ } while (! (Status & DoneMask));
+
+ if ((Status & MCI_STATUS_CMD_ERROR)) {
+ // Clear Status register error flags
+ MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_STATUS_CMD_ERROR);
+
+ if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {
+ DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));
+ RetVal = EFI_NO_RESPONSE;
+ } else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) {
+ //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status));
+ RetVal = EFI_TIMEOUT;
+ } else if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {
+ // The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status.
+ RetVal = EFI_CRC_ERROR;
+ }
+ }
+
+ // Disable Command Path
+ CmdCtrlReg = MmioRead32 (MCI_COMMAND_REG);
+ MmioWrite32 (MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLE));
+ return RetVal;
+}
+
+EFI_STATUS
+MciReceiveResponse (
+ IN EFI_MMC_HOST_PROTOCOL *This,
+ IN MMC_RESPONSE_TYPE Type,
+ IN UINT32* Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ( (Type == MMC_RESPONSE_TYPE_R1)
+ || (Type == MMC_RESPONSE_TYPE_R1b)
+ || (Type == MMC_RESPONSE_TYPE_R3)
+ || (Type == MMC_RESPONSE_TYPE_R6)
+ || (Type == MMC_RESPONSE_TYPE_R7))
+ {
+ Buffer[0] = MmioRead32 (MCI_RESPONSE3_REG);
+ } else if (Type == MMC_RESPONSE_TYPE_R2) {
+ Buffer[0] = MmioRead32 (MCI_RESPONSE0_REG);
+ Buffer[1] = MmioRead32 (MCI_RESPONSE1_REG);
+ Buffer[2] = MmioRead32 (MCI_RESPONSE2_REG);
+ Buffer[3] = MmioRead32 (MCI_RESPONSE3_REG);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MciReadBlockData (
+ IN EFI_MMC_HOST_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Length,
+ IN UINT32* Buffer
+ )
+{
+ UINTN Loop;
+ UINTN Finish;
+ UINTN Status;
+ EFI_STATUS RetVal;
+ UINTN DataCtrlReg;
+ EFI_TPL Tpl;
+
+ RetVal = EFI_SUCCESS;
+
+ // Read data from the RX FIFO
+ Loop = 0;
+ if (Length < MMCI0_BLOCKLEN) {
+ Finish = Length / 4;
+ } else {
+ Finish = MMCI0_BLOCKLEN / 4;
+ }
+
+ // Raise the TPL at the highest level to disable Interrupts.
+ Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+ do {
+ // Read the Status flags
+ Status = MmioRead32 (MCI_STATUS_REG);
+
+ // Do eight reads if possible else a single read
+ if (Status & MCI_STATUS_CMD_RXFIFOHALFFULL) {
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ } else if (Status & MCI_STATUS_CMD_RXDATAAVAILBL) {
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);
+ Loop++;
+ } else {
+ //Check for error conditions and timeouts
+ if (Status & MCI_STATUS_CMD_DATATIMEOUT) {
+ DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
+ RetVal = EFI_TIMEOUT;
+ break;
+ } else if (Status & MCI_STATUS_CMD_DATACRCFAIL) {
+ DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
+ RetVal = EFI_CRC_ERROR;
+ break;
+ } else if (Status & MCI_STATUS_CMD_START_BIT_ERROR) {
+ DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
+ RetVal = EFI_NO_RESPONSE;
+ break;
+ }
+ }
+ //clear RX over run flag
+ if(Status & MCI_STATUS_CMD_RXOVERRUN) {
+ MmioWrite32(MCI_CLEAR_STATUS_REG, MCI_STATUS_CMD_RXOVERRUN);
+ }
+ } while ((Loop < Finish));
+
+ // Restore Tpl
+ gBS->RestoreTPL (Tpl);
+
+ // Clear Status flags
+ MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
+
+ //Disable Data path
+ DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);
+ MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));
+
+ return RetVal;
+}
+
+EFI_STATUS
+MciWriteBlockData (
+ IN EFI_MMC_HOST_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Length,
+ IN UINT32* Buffer
+ )
+{
+ UINTN Loop;
+ UINTN Finish;
+ UINTN Timer;
+ UINTN Status;
+ EFI_STATUS RetVal;
+ UINTN DataCtrlReg;
+ EFI_TPL Tpl;
+
+ RetVal = EFI_SUCCESS;
+
+ // Write the data to the TX FIFO
+ Loop = 0;
+ Finish = MMCI0_BLOCKLEN / 4;
+ Timer = MMCI0_TIMEOUT * 100;
+
+ // Raise the TPL at the highest level to disable Interrupts.
+ Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+ do {
+ // Read the Status flags
+ Status = MmioRead32 (MCI_STATUS_REG);
+
+ // Do eight writes if possible else a single write
+ if (Status & MCI_STATUS_CMD_TXFIFOHALFEMPTY) {
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ } else if (!(Status & MCI_STATUS_CMD_TXFIFOFULL)) {
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);
+ Loop++;
+ } else {
+ // Check for error conditions and timeouts
+ if (Status & MCI_STATUS_CMD_DATATIMEOUT) {
+ DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
+ RetVal = EFI_TIMEOUT;
+ goto Exit;
+ } else if (Status & MCI_STATUS_CMD_DATACRCFAIL) {
+ DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status));
+ RetVal = EFI_CRC_ERROR;
+ goto Exit;
+ } else if (Status & MCI_STATUS_CMD_TX_UNDERRUN) {
+ DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status, Loop));
+ RetVal = EFI_BUFFER_TOO_SMALL;
+ ASSERT(0);
+ goto Exit;
+ }
+ }
+ } while (Loop < Finish);
+
+ // Restore Tpl
+ gBS->RestoreTPL (Tpl);
+
+ // Wait for FIFO to drain
+ Timer = MMCI0_TIMEOUT * 60;
+ Status = MmioRead32 (MCI_STATUS_REG);
+#ifndef USE_STREAM
+ // Single block
+ while (((Status & MCI_STATUS_TXDONE) != MCI_STATUS_TXDONE) && Timer) {
+#else
+ // Stream
+ while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) {
+#endif
+ NanoSecondDelay(10);
+ Status = MmioRead32 (MCI_STATUS_REG);
+ Timer--;
+ }
+
+ // Clear Status flags
+ MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
+
+ if (Timer == 0) {
+ DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): Data End timeout Number of words written 0x%x\n", Loop));
+ RetVal = EFI_TIMEOUT;
+ }
+
+Exit:
+ // Disable Data path
+ DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG);
+ MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK));
+ return RetVal;
+}
+
+EFI_STATUS
+MciNotifyState (
+ IN EFI_MMC_HOST_PROTOCOL *This,
+ IN MMC_STATE State
+ )
+{
+ UINT32 Data32;
+
+ switch (State) {
+ case MmcInvalidState:
+ ASSERT (0);
+ break;
+ case MmcHwInitializationState:
+ // If device already turn on then restart it
+ Data32 = MmioRead32 (MCI_POWER_CONTROL_REG);
+ if ((Data32 & 0x2) == MCI_POWER_UP) {
+ MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOff MCI");
+
+ // Turn off
+ MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0);
+ MmioWrite32 (MCI_POWER_CONTROL_REG, 0);
+ MicroSecondDelay (100);
+ }
+
+ MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOn MCI");
+ // Setup clock
+ // - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz
+ MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);
+
+ // Set the voltage
+ MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_OPENDRAIN | (15<<2));
+ MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP);
+ MicroSecondDelay (10);
+ MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON);
+ MicroSecondDelay (100);
+
+ // Set Data Length & Data Timer
+ MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFF);
+ MmioWrite32 (MCI_DATA_LENGTH_REG, 8);
+
+ ASSERT ((MmioRead32 (MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);
+ break;
+ case MmcIdleState:
+ MCI_TRACE ("MciNotifyState(MmcIdleState)");
+ break;
+ case MmcReadyState:
+ MCI_TRACE ("MciNotifyState(MmcReadyState)");
+ break;
+ case MmcIdentificationState:
+ MCI_TRACE ("MciNotifyState (MmcIdentificationState)");
+ break;
+ case MmcStandByState:{
+ volatile UINT32 PwrCtrlReg;
+ MCI_TRACE ("MciNotifyState (MmcStandByState)");
+
+ // Enable MCICMD push-pull drive
+ PwrCtrlReg = MmioRead32 (MCI_POWER_CONTROL_REG);
+ //Disable Open Drain output
+ PwrCtrlReg &= ~ (MCI_POWER_OPENDRAIN);
+ MmioWrite32 (MCI_POWER_CONTROL_REG, PwrCtrlReg);
+
+ // Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled)
+ //
+ // Note: Increasing clock speed causes TX FIFO under-run errors.
+ // So careful when optimising this driver for higher performance.
+ //
+ MmioWrite32(MCI_CLOCK_CONTROL_REG,0x02 | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);
+ // Set MMCI0 clock to 24MHz (by bypassing the divider)
+ //MmioWrite32(MCI_CLOCK_CONTROL_REG,MCI_CLOCK_BYPASS | MCI_CLOCK_ENABLE);
+ break;
+ }
+ case MmcTransferState:
+ //MCI_TRACE ("MciNotifyState(MmcTransferState)");
+ break;
+ case MmcSendingDataState:
+ MCI_TRACE ("MciNotifyState(MmcSendingDataState)");
+ break;
+ case MmcReceiveDataState:
+ MCI_TRACE ("MciNotifyState(MmcReceiveDataState)");
+ break;
+ case MmcProgrammingState:
+ MCI_TRACE ("MciNotifyState(MmcProgrammingState)");
+ break;
+ case MmcDisconnectState:
+ MCI_TRACE ("MciNotifyState(MmcDisconnectState)");
+ break;
+ default:
+ ASSERT (0);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_GUID mPL180MciDevicePathGuid = EFI_CALLER_ID_GUID;
+
+EFI_STATUS
+MciBuildDevicePath (
+ IN EFI_MMC_HOST_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
+
+ NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
+ CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mPL180MciDevicePathGuid);
+
+ *DevicePath = NewDevicePathNode;
+ return EFI_SUCCESS;
+}
+
+EFI_MMC_HOST_PROTOCOL gMciHost = {
+ MMC_HOST_PROTOCOL_REVISION,
+ MciIsCardPresent,
+ MciIsReadOnly,
+ MciBuildDevicePath,
+ MciNotifyState,
+ MciSendCommand,
+ MciReceiveResponse,
+ MciReadBlockData,
+ MciWriteBlockData
+};
+
+EFI_STATUS
+PL180MciDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL180\n",
+ MCI_PERIPH_ID_REG0));
+
+ // Check if this is a PL180
+ if (MmioRead8 (MCI_PERIPH_ID_REG0) != MCI_PERIPH_ID0 ||
+ MmioRead8 (MCI_PERIPH_ID_REG1) != MCI_PERIPH_ID1 ||
+ MmioRead8 (MCI_PERIPH_ID_REG2) != MCI_PERIPH_ID2 ||
+ MmioRead8 (MCI_PCELL_ID_REG0) != MCI_PCELL_ID0 ||
+ MmioRead8 (MCI_PCELL_ID_REG1) != MCI_PCELL_ID1 ||
+ MmioRead8 (MCI_PCELL_ID_REG2) != MCI_PCELL_ID2 ||
+ MmioRead8 (MCI_PCELL_ID_REG3) != MCI_PCELL_ID3) {
+
+ DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL180"
+ " failed\n", MCI_PERIPH_ID_REG0));
+ return EFI_NOT_FOUND;
+ }
+
+ Handle = NULL;
+
+ MCI_TRACE ("PL180MciDxeInitialize()");
+
+ //Publish Component Name, BlockIO protocol interfaces
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEmbeddedMmcHostProtocolGuid, &gMciHost,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.h b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.h
new file mode 100644
index 000000000000..5d5acd603d00
--- /dev/null
+++ b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.h
@@ -0,0 +1,169 @@
+/** @file
+ Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.
+
+ WARNING:
+ This driver fails to follow the UEFI driver model without a good
+ reason, and only remains in the tree because it is still used by
+ a small number of platforms. It will removed when no longer used.
+ New platforms should not use it, and no one should use this as
+ reference code for developing new drivers.
+
+ Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PL180_MCI_H
+#define __PL180_MCI_H
+
+#include <Uefi.h>
+
+#include <Protocol/MmcHost.h>
+
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+
+#define PL180_MCI_DXE_VERSION 0x10
+
+#define MCI_SYSCTL FixedPcdGet32 (PcdPL180MciBaseAddress)
+
+#define MCI_POWER_CONTROL_REG (MCI_SYSCTL + 0x000)
+#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL + 0x004)
+#define MCI_ARGUMENT_REG (MCI_SYSCTL + 0x008)
+#define MCI_COMMAND_REG (MCI_SYSCTL + 0x00C)
+#define MCI_RESPCMD_REG (MCI_SYSCTL + 0x010)
+#define MCI_RESPONSE3_REG (MCI_SYSCTL + 0x014)
+#define MCI_RESPONSE2_REG (MCI_SYSCTL + 0x018)
+#define MCI_RESPONSE1_REG (MCI_SYSCTL + 0x01C)
+#define MCI_RESPONSE0_REG (MCI_SYSCTL + 0x020)
+#define MCI_DATA_TIMER_REG (MCI_SYSCTL + 0x024)
+#define MCI_DATA_LENGTH_REG (MCI_SYSCTL + 0x028)
+#define MCI_DATA_CTL_REG (MCI_SYSCTL + 0x02C)
+#define MCI_DATA_COUNTER (MCI_SYSCTL + 0x030)
+#define MCI_STATUS_REG (MCI_SYSCTL + 0x034)
+#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038)
+#define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C)
+#define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040)
+#define MCI_SELECT_REG (MCI_SYSCTL + 0x044)
+#define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048)
+#define MCI_FIFO_REG (MCI_SYSCTL + 0x080)
+#define MCI_PERIPH_ID_REG0 (MCI_SYSCTL + 0xFE0)
+#define MCI_PERIPH_ID_REG1 (MCI_SYSCTL + 0xFE4)
+#define MCI_PERIPH_ID_REG2 (MCI_SYSCTL + 0xFE8)
+#define MCI_PERIPH_ID_REG3 (MCI_SYSCTL + 0xFEC)
+#define MCI_PCELL_ID_REG0 (MCI_SYSCTL + 0xFF0)
+#define MCI_PCELL_ID_REG1 (MCI_SYSCTL + 0xFF4)
+#define MCI_PCELL_ID_REG2 (MCI_SYSCTL + 0xFF8)
+#define MCI_PCELL_ID_REG3 (MCI_SYSCTL + 0xFFC)
+
+#define MCI_PERIPH_ID0 0x80
+#define MCI_PERIPH_ID1 0x11
+#define MCI_PERIPH_ID2 0x04
+#define MCI_PERIPH_ID3 0x00
+#define MCI_PCELL_ID0 0x0D
+#define MCI_PCELL_ID1 0xF0
+#define MCI_PCELL_ID2 0x05
+#define MCI_PCELL_ID3 0xB1
+
+#define MCI_POWER_OFF 0
+#define MCI_POWER_UP BIT1
+#define MCI_POWER_ON (BIT1 | BIT0)
+#define MCI_POWER_OPENDRAIN BIT6
+#define MCI_POWER_ROD BIT7
+
+#define MCI_CLOCK_ENABLE BIT8
+#define MCI_CLOCK_POWERSAVE BIT9
+#define MCI_CLOCK_BYPASS BIT10
+#define MCI_CLOCK_WIDEBUS BIT11
+
+#define MCI_STATUS_CMD_CMDCRCFAIL BIT0
+#define MCI_STATUS_CMD_DATACRCFAIL BIT1
+#define MCI_STATUS_CMD_CMDTIMEOUT BIT2
+#define MCI_STATUS_CMD_DATATIMEOUT BIT3
+#define MCI_STATUS_CMD_TX_UNDERRUN BIT4
+#define MCI_STATUS_CMD_RXOVERRUN BIT5
+#define MCI_STATUS_CMD_RESPEND BIT6
+#define MCI_STATUS_CMD_SENT BIT7
+#define MCI_STATUS_CMD_DATAEND BIT8
+#define MCI_STATUS_CMD_START_BIT_ERROR BIT9
+#define MCI_STATUS_CMD_DATABLOCKEND BIT10
+#define MCI_STATUS_CMD_ACTIVE BIT11
+#define MCI_STATUS_CMD_TXACTIVE BIT12
+#define MCI_STATUS_CMD_RXACTIVE BIT13
+#define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14
+#define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15
+#define MCI_STATUS_CMD_TXFIFOFULL BIT16
+#define MCI_STATUS_CMD_RXFIFOFULL BIT17
+#define MCI_STATUS_CMD_TXFIFOEMPTY BIT18
+#define MCI_STATUS_CMD_RXFIFOEMPTY BIT19
+#define MCI_STATUS_CMD_TXDATAAVAILBL BIT20
+#define MCI_STATUS_CMD_RXDATAAVAILBL BIT21
+
+#define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
+#define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)
+#define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
+ | MCI_STATUS_CMD_DATATIMEOUT \
+ | MCI_STATUS_CMD_RXOVERRUN \
+ | MCI_STATUS_CMD_START_BIT_ERROR )
+#define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \
+ | MCI_STATUS_CMD_DATATIMEOUT \
+ | MCI_STATUS_CMD_TX_UNDERRUN )
+#define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \
+ | MCI_STATUS_CMD_CMDTIMEOUT \
+ | MCI_STATUS_CMD_START_BIT_ERROR )
+
+#define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \
+ | MCI_STATUS_CMD_SENT \
+ | MCI_STATUS_CMD_ERROR )
+
+#define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \
+ | MCI_STATUS_READ_ERROR )
+
+#define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \
+ | MCI_STATUS_WRITE_ERROR )
+
+#define MCI_CLR_ALL_STATUS (BIT11 - 1)
+
+#define MCI_DATACTL_DISABLE_MASK 0xFE
+#define MCI_DATACTL_ENABLE BIT0
+#define MCI_DATACTL_CONT_TO_CARD 0
+#define MCI_DATACTL_CARD_TO_CONT BIT1
+#define MCI_DATACTL_BLOCK_TRANS 0
+#define MCI_DATACTL_STREAM_TRANS BIT2
+#define MCI_DATACTL_DMA_DISABLED 0
+#define MCI_DATACTL_DMA_ENABLE BIT3
+
+#define INDX_MASK 0x3F
+
+#define MCI_CPSM_WAIT_RESPONSE BIT6
+#define MCI_CPSM_LONG_RESPONSE BIT7
+#define MCI_CPSM_LONG_INTERRUPT BIT8
+#define MCI_CPSM_LONG_PENDING BIT9
+#define MCI_CPSM_ENABLE BIT10
+
+#define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))
+
+EFI_STATUS
+EFIAPI
+MciGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ );
+
+EFI_STATUS
+EFIAPI
+MciGetControllerName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ );
+
+#endif
diff --git a/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
new file mode 100644
index 000000000000..761f63b90fc4
--- /dev/null
+++ b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
@@ -0,0 +1,53 @@
+#/** @file
+# INF file for the MMC Host Protocol implementation for the ARM PrimeCell PL180.
+#
+# WARNING:
+# This driver fails to follow the UEFI driver model without a good
+# reason, and only remains in the tree because it is still used by
+# a small number of platforms. It will removed when no longer used.
+# New platforms should not use it, and no one should use this as
+# reference code for developing new drivers.
+#
+# Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PL180MciDxe
+ FILE_GUID = 09831032-6fa3-4484-af4f-0a000a8d3a82
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = PL180MciDxeInitialize
+
+[Sources.common]
+ PL180Mci.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiLib
+ UefiDriverEntryPoint
+ BaseMemoryLib
+ ArmLib
+ IoLib
+ TimerLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEmbeddedMmcHostProtocolGuid
+
+[Pcd]
+ gArmVExpressTokenSpaceGuid.PcdPL180SysMciRegAddress
+ gArmVExpressTokenSpaceGuid.PcdPL180MciBaseAddress
+
+[Depex]
+ gEfiCpuArchProtocolGuid
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH edk2-platforms v2 2/2] Platform/ARM/JunoPkg: incorporate SiI3132 SATA controller driver
2020-04-30 8:25 [PATCH edk2-platforms v2 0/2] move obsolete platform drivers out of core edk2 Ard Biesheuvel
2020-04-30 8:25 ` [PATCH edk2-platforms v2 1/2] Platform/ARM/VExpressPkg: incorporate PL180 driver Ard Biesheuvel
@ 2020-04-30 8:25 ` Ard Biesheuvel
1 sibling, 0 replies; 5+ messages in thread
From: Ard Biesheuvel @ 2020-04-30 8:25 UTC (permalink / raw)
To: devel; +Cc: leif, Ard Biesheuvel
Juno is the only user of the SiI3132 SATA controller driver, which
is not quite fit for reuse in its current state. So incorporate it
into JunoPkg so we will be able to drop it from the core EDK2
repository.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
---
Platform/ARM/JunoPkg/ArmJuno.dec | 3 +
Platform/ARM/JunoPkg/ArmJuno.dsc | 2 +-
Platform/ARM/JunoPkg/ArmJuno.fdf | 2 +-
Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/ComponentName.c | 179 +++++
Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c | 546 +++++++++++++
Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h | 286 +++++++
Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf | 38 +
Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c | 834 ++++++++++++++++++++
8 files changed, 1888 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/JunoPkg/ArmJuno.dec b/Platform/ARM/JunoPkg/ArmJuno.dec
index 27fe75790721..cfb4e4ec3735 100644
--- a/Platform/ARM/JunoPkg/ArmJuno.dec
+++ b/Platform/ARM/JunoPkg/ArmJuno.dec
@@ -55,3 +55,6 @@ [PcdsFixedAtBuild.common]
# For a list of mode numbers look in HdLcdArmJuno.c
gArmJunoTokenSpaceGuid.PcdArmHdLcdMaxMode|0|UINT32|0x00000017
+ gArmJunoTokenSpaceGuid.PcdSataSiI3132FeaturePMPSupport|FALSE|BOOLEAN|0x00000018
+ gArmJunoTokenSpaceGuid.PcdSataSiI3132FeatureDirectCommandIssuing|FALSE|BOOLEAN|0x00000019
+
diff --git a/Platform/ARM/JunoPkg/ArmJuno.dsc b/Platform/ARM/JunoPkg/ArmJuno.dsc
index 954faca1bbfa..1c39da4897ed 100644
--- a/Platform/ARM/JunoPkg/ArmJuno.dsc
+++ b/Platform/ARM/JunoPkg/ArmJuno.dsc
@@ -314,7 +314,7 @@ [Components.common]
# SATA Controller
#
MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
- EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
+ Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
#
# NVMe boot devices
diff --git a/Platform/ARM/JunoPkg/ArmJuno.fdf b/Platform/ARM/JunoPkg/ArmJuno.fdf
index 7c128b2c5bff..d771cbf35790 100644
--- a/Platform/ARM/JunoPkg/ArmJuno.fdf
+++ b/Platform/ARM/JunoPkg/ArmJuno.fdf
@@ -184,7 +184,7 @@ [FV.FvMain]
# SATA Controller
#
INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
- INF EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
+ INF Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
#
# NVMe boot devices
diff --git a/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/ComponentName.c b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/ComponentName.c
new file mode 100644
index 000000000000..2af70359f84e
--- /dev/null
+++ b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/ComponentName.c
@@ -0,0 +1,179 @@
+/** @file
+ UEFI Component Name(2) protocol implementation for Silicon Image I3132 SATA controller
+
+ WARNING:
+ This driver fails to follow the UEFI driver model without a good
+ reason, and only remains in the tree because it is still used by
+ a small number of platforms. It will removed when no longer used.
+ New platforms should not use it, and no one should use this as
+ reference code for developing new drivers.
+
+ Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SataSiI3132.h"
+
+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSataSiI3132ComponentName = {
+ SataSiI3132ComponentNameGetDriverName,
+ SataSiI3132ComponentNameGetControllerName,
+ "eng"
+};
+
+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SataSiI3132ComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SataSiI3132ComponentNameGetControllerName,
+ "en"
+};
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataSiI3132DriverNameTable[] = {
+ { "eng;en", L"Pci SATA Silicon Image 3132 Driver" },
+ { NULL , NULL }
+};
+
+
+/**
+ Retrieves a Unicode string that is the user readable name of the driver.
+
+ This function retrieves the user readable name of a driver in the form of a
+ Unicode string. If the driver specified by This has a user readable name in
+ the language specified by Language, then a pointer to the driver name is
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+ by This does not support the language specified by Language,
+ then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified
+ in RFC 4646 or ISO 639-2 language code format.
+
+ @param DriverName[out] A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by
+ This and the language specified by Language was
+ returned in DriverName.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SataSiI3132ComponentNameGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ )
+{
+ return LookupUnicodeString2 (
+ Language,
+ This->SupportedLanguages,
+ mSataSiI3132DriverNameTable,
+ DriverName,
+ (BOOLEAN)(This == &gSataSiI3132ComponentName)
+ );
+}
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by a driver.
+
+ This function retrieves the user readable name of the controller specified by
+ ControllerHandle and ChildHandle in the form of a Unicode string. If the
+ driver specified by This has a user readable name in the language specified by
+ Language, then a pointer to the controller name is returned in ControllerName,
+ and EFI_SUCCESS is returned. If the driver specified by This is not currently
+ managing the controller specified by ControllerHandle and ChildHandle,
+ then EFI_UNSUPPORTED is returned. If the driver specified by This does not
+ support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param ControllerHandle[in] The handle of a controller that the driver
+ specified by This is managing. This handle
+ specifies the controller whose name is to be
+ returned.
+
+ @param ChildHandle[in] The handle of the child controller to retrieve
+ the name of. This is an optional parameter that
+ may be NULL. It will be NULL for device
+ drivers. It will also be NULL for a bus drivers
+ that wish to retrieve the name of the bus
+ controller. It will not be NULL for a bus
+ driver that wishes to retrieve the name of a
+ child controller.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified in
+ RFC 4646 or ISO 639-2 language code format.
+
+ @param ControllerName[out] A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ controller specified by ControllerHandle and
+ ChildHandle in the language specified by
+ Language from the point of view of the driver
+ specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in
+ the language specified by Language for the
+ driver specified by This was returned in
+ DriverName.
+
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+ EFI_HANDLE.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by
+ ControllerHandle and ChildHandle.
+
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SataSiI3132ComponentNameGetControllerName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ )
+{
+ return EFI_UNSUPPORTED;
+}
diff --git a/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c
new file mode 100644
index 000000000000..ae63449bdddc
--- /dev/null
+++ b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.c
@@ -0,0 +1,546 @@
+/** @file
+ PCIe Sata support for the Silicon Image I3132
+
+ WARNING:
+ This driver fails to follow the UEFI driver model without a good
+ reason, and only remains in the tree because it is still used by
+ a small number of platforms. It will removed when no longer used.
+ New platforms should not use it, and no one should use this as
+ reference code for developing new drivers.
+
+ Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SataSiI3132.h"
+
+#include <IndustryStandard/Acpi10.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/BaseLib.h>
+
+#define ACPI_SPECFLAG_PREFETCHABLE 0x06
+
+EFI_DRIVER_BINDING_PROTOCOL
+gSataSiI3132DriverBinding = {
+ SataSiI3132DriverBindingSupported,
+ SataSiI3132DriverBindingStart,
+ SataSiI3132DriverBindingStop,
+ 0x30,
+ NULL,
+ NULL
+};
+
+EFI_STATUS
+SataSiI3132PortConstructor (
+ IN SATA_SI3132_INSTANCE *SataSiI3132Instance,
+ IN UINTN Index
+ )
+{
+ EFI_STATUS Status;
+ SATA_SI3132_PORT *Port;
+ VOID *HostPRB;
+ EFI_PHYSICAL_ADDRESS PhysAddrHostPRB;
+ VOID *PciAllocMappingPRB;
+ UINTN NumberOfBytes;
+
+ Port = &(SataSiI3132Instance->Ports[Index]);
+
+ Port->Index = Index;
+ Port->RegBase = Index * 0x2000;
+ Port->Instance = SataSiI3132Instance;
+ InitializeListHead (&(Port->Devices));
+
+ NumberOfBytes = sizeof (SATA_SI3132_PRB);
+ Status = SataSiI3132Instance->PciIo->AllocateBuffer (
+ SataSiI3132Instance->PciIo, AllocateAnyPages, EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (NumberOfBytes), &HostPRB, 0
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Check the alignment of the PCI Buffer
+ ASSERT (((UINTN)HostPRB & (0x1000 - 1)) == 0);
+ Status = SataSiI3132Instance->PciIo->Map (
+ SataSiI3132Instance->PciIo, EfiPciIoOperationBusMasterCommonBuffer, HostPRB,
+ &NumberOfBytes, &PhysAddrHostPRB, &PciAllocMappingPRB
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Port->HostPRB = HostPRB;
+ Port->PhysAddrHostPRB = PhysAddrHostPRB;
+ Port->PciAllocMappingPRB = PciAllocMappingPRB;
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+SataSiI3132Constructor (
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ OUT SATA_SI3132_INSTANCE** SataSiI3132Instance
+ )
+{
+ SATA_SI3132_INSTANCE *Instance;
+ EFI_ATA_PASS_THRU_MODE *AtaPassThruMode;
+
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Instance = (SATA_SI3132_INSTANCE*)AllocateZeroPool (sizeof (SATA_SI3132_INSTANCE));
+ if (Instance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Instance->Signature = SATA_SII3132_SIGNATURE;
+ Instance->PciIo = PciIo;
+
+ AtaPassThruMode = (EFI_ATA_PASS_THRU_MODE*)AllocatePool (sizeof (EFI_ATA_PASS_THRU_MODE));
+ AtaPassThruMode->Attributes = EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL | EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL;
+ AtaPassThruMode->IoAlign = 0x1000;
+
+ // Initialize SiI3132 ports
+ SataSiI3132PortConstructor (Instance, 0);
+ SataSiI3132PortConstructor (Instance, 1);
+
+ // Set ATA Pass Thru Protocol
+ Instance->AtaPassThruProtocol.Mode = AtaPassThruMode;
+ Instance->AtaPassThruProtocol.PassThru = SiI3132AtaPassThru;
+ Instance->AtaPassThruProtocol.GetNextPort = SiI3132GetNextPort;
+ Instance->AtaPassThruProtocol.GetNextDevice = SiI3132GetNextDevice;
+ Instance->AtaPassThruProtocol.BuildDevicePath = SiI3132BuildDevicePath;
+ Instance->AtaPassThruProtocol.GetDevice = SiI3132GetDevice;
+ Instance->AtaPassThruProtocol.ResetPort = SiI3132ResetPort;
+ Instance->AtaPassThruProtocol.ResetDevice = SiI3132ResetDevice;
+
+ *SataSiI3132Instance = Instance;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SiI3132SoftResetCommand (
+ IN SATA_SI3132_PORT *Port,
+ OUT UINT32* Signature
+ )
+{
+ EFI_STATUS Status;
+ EFI_ATA_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_ATA_STATUS_BLOCK Asb;
+ EFI_ATA_COMMAND_BLOCK Acb;
+ CONST UINT16 PortMultiplierPort = 0;
+
+ ZeroMem (&Acb, sizeof (EFI_ATA_COMMAND_BLOCK));
+
+ Acb.Reserved1[1] = 0;
+
+ Packet.Asb = &Asb;
+ Packet.Acb = &Acb;
+ Packet.Timeout = 100000;
+ Packet.Protocol = EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET;
+
+ Status = SiI3132AtaPassThruCommand (Port->Instance, Port, PortMultiplierPort, &Packet, 0);
+
+ if (Status == EFI_SUCCESS) {
+ *Signature = (Asb.AtaCylinderHigh << 24) | (Asb.AtaCylinderLow << 16) |
+ (Asb.AtaSectorNumber << 8 ) | (Asb.AtaSectorCount);
+ }
+ return Status;
+}
+
+EFI_STATUS
+SataSiI3132PortInitialization (
+ IN SATA_SI3132_PORT *Port
+ )
+{
+ UINT32 Value32;
+ SATA_SI3132_DEVICE* Device;
+ UINT32 Signature;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL* PciIo;
+
+ Status = SiI3132HwResetPort (Port);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ PciIo = Port->Instance->PciIo;
+
+ // Is a device is present ?
+ Status = SATA_PORT_READ32 (Port->RegBase + SII3132_PORT_SSTATUS_REG, &Value32);
+ if (!EFI_ERROR (Status) && (Value32 & 0x3)) {
+ // Do a soft reset to see if it is a port multiplier
+ SATA_TRACE ("SataSiI3132PortInitialization: soft reset - it is a port multiplier\n");
+ Status = SiI3132SoftResetCommand (Port, &Signature);
+ if (!EFI_ERROR (Status)) {
+ if (Signature == SII3132_PORT_SIGNATURE_PMP) {
+ SATA_TRACE ("SataSiI3132PortInitialization(): a Port Multiplier is present");
+ if (FeaturePcdGet (PcdSataSiI3132FeaturePMPSupport)) {
+ ASSERT (0); // Not supported yet
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+ } else if (Signature == SII3132_PORT_SIGNATURE_ATAPI) {
+ ASSERT (0); // Not supported yet
+ SATA_TRACE ("SataSiI3132PortInitialization(): an ATAPI device is present");
+ return EFI_UNSUPPORTED;
+ } else if (Signature == SII3132_PORT_SIGNATURE_ATA) {
+ SATA_TRACE ("SataSiI3132PortInitialization(): an ATA device is present");
+ } else {
+ SATA_TRACE ("SataSiI3132PortInitialization(): Present device unknown!");
+ ASSERT (0); // Not supported
+ return EFI_UNSUPPORTED;
+ }
+
+ // Create Device
+ Device = (SATA_SI3132_DEVICE*)AllocatePool (sizeof (SATA_SI3132_DEVICE));
+ Device->Index = Port->Index; //TODO: Could need to be fixed when SATA Port Multiplier support
+ Device->Port = Port;
+ Device->BlockSize = 0;
+
+ // Attached the device to the Sata Port
+ InsertTailList (&Port->Devices, &Device->Link);
+
+ SATA_TRACE ("SataSiI3132PortInitialization(): Port Ready");
+ }
+ }
+ return Status;
+}
+
+EFI_STATUS
+SataSiI3132Initialization (
+ IN SATA_SI3132_INSTANCE* SataSiI3132Instance
+ )
+{
+ UINTN Index;
+ EFI_PCI_IO_PROTOCOL* PciIo;
+
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PciIo = SataSiI3132Instance->PciIo;
+
+ // Turn Off GPIO
+ SATA_GLOBAL_WRITE32 (SII3132_GLOBAL_FLASHADDR_REG, 0x0);
+
+ // Clear Global Control Register
+ SATA_GLOBAL_WRITE32 (SII3132_GLOBAL_CONTROL_REG, 0x0);
+
+ for (Index = 0; Index < SATA_SII3132_MAXPORT; Index++) {
+ SataSiI3132PortInitialization (&(SataSiI3132Instance->Ports[Index]));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Test to see if this driver supports ControllerHandle.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to test.
+ @param RemainingDevicePath Not used.
+
+ @return EFI_SUCCESS This driver supports this device.
+ @return EFI_UNSUPPORTED This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+SataSiI3132DriverBindingSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 PciID;
+
+ //
+ // Test whether there is PCI IO Protocol attached on the controller handle.
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ PCI_VENDOR_ID_OFFSET,
+ 1,
+ &PciID
+ );
+ if (EFI_ERROR (Status)) {
+ Status = EFI_UNSUPPORTED;
+ goto ON_EXIT;
+ }
+
+ //
+ // Test whether the controller belongs to SATA Mass Storage type
+ //
+ if (PciID != ((SATA_SII3132_DEVICE_ID << 16) | SATA_SII3132_VENDOR_ID)) {
+ Status = EFI_UNSUPPORTED;
+ }
+
+ON_EXIT:
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+
+ return Status;
+}
+
+BOOLEAN mbStarted = FALSE;
+
+/**
+ Starting the Pci SATA Driver.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to test.
+ @param RemainingDevicePath Not used.
+
+ @return EFI_SUCCESS supports this device.
+ @return EFI_UNSUPPORTED do not support this device.
+ @return EFI_DEVICE_ERROR cannot be started due to device Error.
+ @return EFI_OUT_OF_RESOURCES cannot allocate resources.
+
+**/
+EFI_STATUS
+EFIAPI
+SataSiI3132DriverBindingStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Supports;
+ UINT64 OriginalPciAttributes;
+ BOOLEAN PciAttributesSaved;
+ UINT32 PciID;
+ SATA_SI3132_INSTANCE *SataSiI3132Instance = NULL;
+
+ SATA_TRACE ("SataSiI3132DriverBindingStart()");
+
+ //TODO: Find a nicer way to do it !
+ if (mbStarted) {
+ return EFI_SUCCESS; // Don't restart me !
+ }
+
+ //
+ // Open the PciIo Protocol
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ PciAttributesSaved = FALSE;
+ //
+ // Save original PCI attributes
+ //
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationGet,
+ 0,
+ &OriginalPciAttributes
+ );
+ if (EFI_ERROR (Status)) {
+ goto CLOSE_PCIIO;
+ }
+ PciAttributesSaved = TRUE;
+
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationSupported,
+ 0,
+ &Supports
+ );
+ if (!EFI_ERROR (Status)) {
+ Supports &= EFI_PCI_DEVICE_ENABLE | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
+ }
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "SataSiI3132DriverBindingStart: failed to enable controller\n"));
+ goto CLOSE_PCIIO;
+ }
+
+ //
+ // Get the Pci device class code.
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ PCI_VENDOR_ID_OFFSET,
+ 1,
+ &PciID
+ );
+ if (EFI_ERROR (Status)) {
+ Status = EFI_UNSUPPORTED;
+ goto CLOSE_PCIIO;
+ }
+
+ //
+ // Test whether the controller belongs to SATA Mass Storage type
+ //
+ if (PciID != ((SATA_SII3132_DEVICE_ID << 16) | SATA_SII3132_VENDOR_ID)) {
+ Status = EFI_UNSUPPORTED;
+ goto CLOSE_PCIIO;
+ }
+
+ // Create SiI3132 Sata Instance
+ Status = SataSiI3132Constructor (PciIo, &SataSiI3132Instance);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Initialize SiI3132 Sata Controller
+ Status = SataSiI3132Initialization (SataSiI3132Instance);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Install Ata Pass Thru Protocol
+ Status = gBS->InstallProtocolInterface (
+ &Controller,
+ &gEfiAtaPassThruProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &(SataSiI3132Instance->AtaPassThruProtocol)
+ );
+ if (EFI_ERROR (Status)) {
+ goto FREE_POOL;
+ }
+
+/* //
+ // Create event to stop the HC when exit boot service.
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ EhcExitBootService,
+ Ehc,
+ &gEfiEventExitBootServicesGuid,
+ &Ehc->ExitBootServiceEvent
+ );
+ if (EFI_ERROR (Status)) {
+ goto UNINSTALL_USBHC;
+ }*/
+
+ mbStarted = TRUE;
+
+ SATA_TRACE ("SataSiI3132DriverBindingStart() Success!");
+ return EFI_SUCCESS;
+
+FREE_POOL:
+ //TODO: Free SATA Instance
+
+CLOSE_PCIIO:
+ if (PciAttributesSaved) {
+ //
+ // Restore original PCI attributes
+ //
+ PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationSet,
+ OriginalPciAttributes,
+ NULL
+ );
+ }
+
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+
+ return Status;
+}
+
+/**
+ Stop this driver on ControllerHandle. Support stopping any child handles
+ created by this driver.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to stop driver on.
+ @param NumberOfChildren Number of Children in the ChildHandleBuffer.
+ @param ChildHandleBuffer List of handles for the children we need to stop.
+
+ @return EFI_SUCCESS Success.
+ @return EFI_DEVICE_ERROR Fail.
+
+**/
+EFI_STATUS
+EFIAPI
+SataSiI3132DriverBindingStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ )
+{
+ SATA_TRACE ("SataSiI3132DriverBindingStop()");
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Entry point of this driver
+
+ @param ImageHandle Handle of driver image
+ @param SystemTable Point to EFI_SYSTEM_TABLE
+
+ @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource
+ @retval EFI_DEVICE_ERROR Can not install the protocol instance
+ @retval EFI_SUCCESS Success to initialize the Pci host bridge.
+**/
+EFI_STATUS
+EFIAPI
+InitializeSataSiI3132 (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ SATA_TRACE ("InitializeSataSiI3132 ()");
+
+ return EfiLibInstallDriverBindingComponentName2 (
+ ImageHandle,
+ SystemTable,
+ &gSataSiI3132DriverBinding,
+ ImageHandle,
+ &gSataSiI3132ComponentName,
+ &gSataSiI3132ComponentName2
+ );
+}
diff --git a/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h
new file mode 100644
index 000000000000..94cccd88de78
--- /dev/null
+++ b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h
@@ -0,0 +1,286 @@
+/** @file
+ Header containing the structure specific to the Silicon Image I3132 Sata PCI card
+
+ WARNING:
+ This driver fails to follow the UEFI driver model without a good
+ reason, and only remains in the tree because it is still used by
+ a small number of platforms. It will removed when no longer used.
+ New platforms should not use it, and no one should use this as
+ reference code for developing new drivers.
+
+ Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SATASII3132_H
+#define __SATASII3132_H
+
+#include <PiDxe.h>
+
+#include <Protocol/AtaPassThru.h>
+#include <Protocol/PciIo.h>
+
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <IndustryStandard/Pci.h>
+
+#define SATA_SII3132_DEVICE_ID 0x3132
+#define SATA_SII3132_VENDOR_ID 0x1095
+
+#define SII3132_PORT_SIGNATURE_PMP 0x96690101
+#define SII3132_PORT_SIGNATURE_ATAPI 0xEB140101
+#define SII3132_PORT_SIGNATURE_ATA 0x00000101
+
+/*
+ * Silicon Image SiI3132 Registers
+ */
+#define SII3132_GLOBAL_CONTROL_REG 0x40
+#define SII3132_GLOBAL_FLASHADDR_REG 0x70
+
+#define SII3132_PORT_STATUS_REG 0x1000
+#define SII3132_PORT_CONTROLSET_REG 0x1000
+#define SII3132_PORT_CONTROLCLEAR_REG 0x1004
+#define SII3132_PORT_INTSTATUS_REG 0x1008
+#define SII3132_PORT_ENABLEINT_REG 0x1010
+#define SII3132_PORT_INTCLEAR_REG 0x1014
+#define SII3132_PORT_32BITACTIVADDR_REG 0x101C
+#define SII3132_PORT_CMDEXECFIFO_REG 0x1020
+#define SII3132_PORT_CMDERROR_REG 0x1024
+#define SII3132_PORT_ERRCOUNTDECODE 0x1040
+#define SII3132_PORT_ERRCOUNTCRC 0x1044
+#define SII3132_PORT_ERRCOUNTHANDSHAKE 0x1048
+#define SII3132_PORT_SLOTSTATUS_REG 0x1800
+#define SII3132_PORT_CMDACTIV_REG 0x1C00
+#define SII3132_PORT_SSTATUS_REG 0x1F04
+
+#define SII3132_PORT_CONTROL_RESET (1 << 0)
+#define SII3132_PORT_DEVICE_RESET (1 << 1)
+#define SII3132_PORT_CONTROL_INT (1 << 2)
+#define SII3132_PORT_CONTROL_32BITACTIVATION (1 << 10)
+
+#define SII3132_PORT_STATUS_PORTREADY 0x80000000
+
+#define SII3132_PORT_INT_CMDCOMPL (1 << 0)
+#define SII3132_PORT_INT_CMDERR (1 << 1)
+#define SII3132_PORT_INT_PORTRDY (1 << 2)
+
+#define SATA_SII3132_MAXPORT 2
+
+#define PRB_CTRL_ATA 0x0
+#define PRB_CTRL_PROT_OVERRIDE 0x1
+#define PRB_CTRL_RESTRANSMIT 0x2
+#define PRB_CTRL_EXT_CMD 0x4
+#define PRB_CTRL_RCV 0x8
+#define PRB_CTRL_PKT_READ 0x10
+#define PRB_CTRL_PKT_WRITE 0x20
+#define PRB_CTRL_INT_MASK 0x40
+#define PRB_CTRL_SRST 0x80
+
+#define PRB_PROT_PACKET 0x01
+#define PRB_PROT_LEGACY_QUEUE 0x02
+#define PRB_PROT_NATIVE_QUEUE 0x04
+#define PRB_PROT_READ 0x08
+#define PRB_PROT_WRITE 0x10
+#define PRB_PROT_TRANSPARENT 0x20
+
+#define SGE_XCF (1 << 28)
+#define SGE_DRD (1 << 29)
+#define SGE_LNK (1 << 30)
+#define SGE_TRM 0x80000000
+
+typedef struct _SATA_SI3132_SGE {
+ UINT32 DataAddressLow;
+ UINT32 DataAddressHigh;
+ UINT32 DataCount;
+ UINT32 Attributes;
+} SATA_SI3132_SGE;
+
+typedef struct _SATA_SI3132_FIS {
+ UINT8 FisType;
+ UINT8 Control;
+ UINT8 Command;
+ UINT8 Features;
+ UINT8 Fis[5 * 4];
+} SATA_SI3132_FIS;
+
+typedef struct _SATA_SI3132_PRB {
+ UINT16 Control;
+ UINT16 ProtocolOverride;
+ UINT32 RecTransCount;
+ SATA_SI3132_FIS Fis;
+ SATA_SI3132_SGE Sge[2];
+} SATA_SI3132_PRB;
+
+typedef struct _SATA_SI3132_DEVICE {
+ LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
+ UINTN Index;
+ struct _SATA_SI3132_PORT *Port; //Parent Port
+ UINT32 BlockSize;
+} SATA_SI3132_DEVICE;
+
+typedef struct _SATA_SI3132_PORT {
+ UINTN Index;
+ UINTN RegBase;
+ struct _SATA_SI3132_INSTANCE *Instance;
+
+ //TODO: Support Port multiplier
+ LIST_ENTRY Devices;
+
+ SATA_SI3132_PRB* HostPRB;
+ EFI_PHYSICAL_ADDRESS PhysAddrHostPRB;
+ VOID* PciAllocMappingPRB;
+} SATA_SI3132_PORT;
+
+typedef struct _SATA_SI3132_INSTANCE {
+ UINTN Signature;
+
+ SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT];
+
+ EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol;
+
+ EFI_PCI_IO_PROTOCOL *PciIo;
+} SATA_SI3132_INSTANCE;
+
+#define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', '2')
+#define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE)
+
+#define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value)
+#define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); }
+
+#define SATA_PORT_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, Value)
+#define SATA_PORT_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, &Value32); }
+
+#define SATA_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_SATA: " txt "\n"))
+
+extern EFI_COMPONENT_NAME_PROTOCOL gSataSiI3132ComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2;
+
+/*
+ * Component Name Protocol Functions
+ */
+EFI_STATUS
+EFIAPI
+SataSiI3132ComponentNameGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ );
+
+EFI_STATUS
+EFIAPI
+SataSiI3132ComponentNameGetControllerName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ );
+
+EFI_STATUS SiI3132HwResetPort (SATA_SI3132_PORT *Port);
+
+/*
+ * Driver Binding Protocol Functions
+ */
+EFI_STATUS
+EFIAPI
+SataSiI3132DriverBindingSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+EFI_STATUS
+EFIAPI
+SataSiI3132DriverBindingStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+EFI_STATUS
+EFIAPI
+SataSiI3132DriverBindingStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+SiI3132AtaPassThruCommand (
+ IN SATA_SI3132_INSTANCE *pSataSiI3132Instance,
+ IN SATA_SI3132_PORT *pSataPort,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
+ );
+
+/**
+ * EFI ATA Pass Thru Protocol
+ */
+EFI_STATUS
+EFIAPI
+SiI3132AtaPassThru (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
+ );
+
+EFI_STATUS
+EFIAPI
+SiI3132GetNextPort (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT16 *Port
+ );
+
+EFI_STATUS
+EFIAPI
+SiI3132GetNextDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN OUT UINT16 *PortMultiplierPort
+ );
+
+EFI_STATUS
+EFIAPI
+SiI3132BuildDevicePath (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ );
+
+EFI_STATUS
+EFIAPI
+SiI3132GetDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT16 *Port,
+ OUT UINT16 *PortMultiplierPort
+ );
+
+EFI_STATUS
+EFIAPI
+SiI3132ResetPort (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port
+ );
+
+EFI_STATUS
+EFIAPI
+SiI3132ResetDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort
+ );
+
+#endif
diff --git a/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
new file mode 100644
index 000000000000..a73b3bc168a8
--- /dev/null
+++ b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
@@ -0,0 +1,38 @@
+#/** @file
+# INF file for the Silicon Image I3132 SATA controller
+#
+# Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 1.27
+ BASE_NAME = SataSiI3132Dxe
+ FILE_GUID = 1df18da0-a18b-11df-8c3a-0002a5d5c51b
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializeSataSiI3132
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/ARM/JunoPkg/ArmJuno.dec
+
+[LibraryClasses]
+ MemoryAllocationLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Sources]
+ ComponentName.c
+ SataSiI3132.c
+ SiI3132AtaPassThru.c
+
+[Protocols]
+ gEfiPciIoProtocolGuid # CONSUMED
+ gEfiAtaPassThruProtocolGuid # PRODUCED
+
+[Pcd]
+ gArmJunoTokenSpaceGuid.PcdSataSiI3132FeaturePMPSupport
+ gArmJunoTokenSpaceGuid.PcdSataSiI3132FeatureDirectCommandIssuing
diff --git a/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c
new file mode 100644
index 000000000000..5727f7511df8
--- /dev/null
+++ b/Platform/ARM/JunoPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c
@@ -0,0 +1,834 @@
+/** @file
+
+ WARNING:
+ This driver fails to follow the UEFI driver model without a good
+ reason, and only remains in the tree because it is still used by
+ a small number of platforms. It will removed when no longer used.
+ New platforms should not use it, and no one should use this as
+ reference code for developing new drivers.
+
+ Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SataSiI3132.h"
+
+#include <IndustryStandard/Atapi.h>
+#include <Library/DevicePathLib.h>
+
+SATA_SI3132_DEVICE*
+GetSataDevice (
+ IN SATA_SI3132_INSTANCE* SataInstance,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort
+) {
+ LIST_ENTRY *List;
+ SATA_SI3132_PORT *SataPort;
+ SATA_SI3132_DEVICE *SataDevice;
+
+ if (Port >= SATA_SII3132_MAXPORT) {
+ return NULL;
+ }
+
+ SataPort = &(SataInstance->Ports[Port]);
+ List = SataPort->Devices.ForwardLink;
+
+ while (List != &SataPort->Devices) {
+ SataDevice = (SATA_SI3132_DEVICE*)List;
+ if (SataDevice->Index == PortMultiplierPort) {
+ return SataDevice;
+ }
+ List = List->ForwardLink;
+ }
+ return NULL;
+}
+
+EFI_STATUS
+EFIAPI
+SiI3132AtaPassThruCommand (
+ IN SATA_SI3132_INSTANCE *SataSiI3132Instance,
+ IN SATA_SI3132_PORT *SataPort,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
+ )
+{
+ SATA_SI3132_DEVICE *SataDevice;
+ EFI_PHYSICAL_ADDRESS PhysInDataBuffer;
+ UINTN InDataBufferLength = 0;
+ EFI_PHYSICAL_ADDRESS PhysOutDataBuffer;
+ UINTN OutDataBufferLength;
+ CONST UINTN EmptySlot = 0;
+ UINTN Control = PRB_CTRL_ATA;
+ UINTN Protocol = 0;
+ UINT32 Value32, Error, Timeout = 0;
+ CONST UINT32 IrqMask = (SII3132_PORT_INT_CMDCOMPL | SII3132_PORT_INT_CMDERR) << 16;
+ EFI_STATUS Status;
+ VOID* PciAllocMapping = NULL;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+
+ PciIo = SataSiI3132Instance->PciIo;
+ ZeroMem (SataPort->HostPRB, sizeof (SATA_SI3132_PRB));
+
+ // Construct Si3132 PRB
+ switch (Packet->Protocol) {
+ case EFI_ATA_PASS_THRU_PROTOCOL_ATA_HARDWARE_RESET:
+ ASSERT (0); //TODO: Implement me!
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET:
+ SATA_TRACE ("SiI3132AtaPassThru() EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET");
+ Control = PRB_CTRL_SRST;
+
+ if (FeaturePcdGet (PcdSataSiI3132FeaturePMPSupport)) {
+ SataPort->HostPRB->Fis.Control = 0x0F;
+ }
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_ATA_NON_DATA:
+ ASSERT (0); //TODO: Implement me!
+ break;
+
+ // There is no difference for SiI3132 between PIO and DMA invokation
+ case EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_IN:
+ case EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_IN:
+ // Fixup the size for block transfer. Following UEFI Specification, 'InTransferLength' should
+ // be in number of bytes. But for most data transfer commands, the value is in number of blocks
+ if (Packet->Acb->AtaCommand == ATA_CMD_IDENTIFY_DRIVE) {
+ InDataBufferLength = Packet->InTransferLength;
+ } else {
+ SataDevice = GetSataDevice (SataSiI3132Instance, SataPort->Index, PortMultiplierPort);
+ if (!SataDevice || (SataDevice->BlockSize == 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InDataBufferLength = Packet->InTransferLength * SataDevice->BlockSize;
+ }
+
+ Status = PciIo->Map (
+ PciIo, EfiPciIoOperationBusMasterWrite,
+ Packet->InDataBuffer, &InDataBufferLength, &PhysInDataBuffer, &PciAllocMapping
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Construct SGEs (32-bit system)
+ SataPort->HostPRB->Sge[0].DataAddressLow = (UINT32)PhysInDataBuffer;
+ SataPort->HostPRB->Sge[0].DataAddressHigh = (UINT32)(PhysInDataBuffer >> 32);
+ SataPort->HostPRB->Sge[0].Attributes = SGE_TRM; // Only one SGE
+ SataPort->HostPRB->Sge[0].DataCount = InDataBufferLength;
+
+ // Copy the Ata Command Block
+ CopyMem (&SataPort->HostPRB->Fis, Packet->Acb, sizeof (EFI_ATA_COMMAND_BLOCK));
+
+ // Fixup the FIS
+ SataPort->HostPRB->Fis.FisType = 0x27; // Register - Host to Device FIS
+ SataPort->HostPRB->Fis.Control = 1 << 7; // Is a command
+ if (FeaturePcdGet (PcdSataSiI3132FeaturePMPSupport)) {
+ SataPort->HostPRB->Fis.Control |= PortMultiplierPort & 0xFF;
+ }
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_OUT:
+ case EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_OUT:
+ SataDevice = GetSataDevice (SataSiI3132Instance, SataPort->Index, PortMultiplierPort);
+ if (!SataDevice || (SataDevice->BlockSize == 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Fixup the size for block transfer. Following UEFI Specification, 'InTransferLength' should
+ // be in number of bytes. But for most data transfer commands, the value is in number of blocks
+ OutDataBufferLength = Packet->OutTransferLength * SataDevice->BlockSize;
+
+ Status = PciIo->Map (
+ PciIo, EfiPciIoOperationBusMasterRead,
+ Packet->OutDataBuffer, &OutDataBufferLength, &PhysOutDataBuffer, &PciAllocMapping
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Construct SGEs (32-bit system)
+ SataPort->HostPRB->Sge[0].DataAddressLow = (UINT32)PhysOutDataBuffer;
+ SataPort->HostPRB->Sge[0].DataAddressHigh = (UINT32)(PhysOutDataBuffer >> 32);
+ SataPort->HostPRB->Sge[0].Attributes = SGE_TRM; // Only one SGE
+ SataPort->HostPRB->Sge[0].DataCount = OutDataBufferLength;
+
+ // Copy the Ata Command Block
+ CopyMem (&SataPort->HostPRB->Fis, Packet->Acb, sizeof (EFI_ATA_COMMAND_BLOCK));
+
+ // Fixup the FIS
+ SataPort->HostPRB->Fis.FisType = 0x27; // Register - Host to Device FIS
+ SataPort->HostPRB->Fis.Control = 1 << 7; // Is a command
+ if (FeaturePcdGet (PcdSataSiI3132FeaturePMPSupport)) {
+ SataPort->HostPRB->Fis.Control |= PortMultiplierPort & 0xFF;
+ }
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_DMA:
+ ASSERT (0); //TODO: Implement me!
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_DMA_QUEUED:
+ ASSERT (0); //TODO: Implement me!
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_DIAGNOSTIC:
+ ASSERT (0); //TODO: Implement me!
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_RESET:
+ ASSERT (0); //TODO: Implement me!
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_FPDMA:
+ ASSERT (0); //TODO: Implement me!
+ break;
+ case EFI_ATA_PASS_THRU_PROTOCOL_RETURN_RESPONSE:
+ ASSERT (0); //TODO: Implement me!
+ break;
+ default:
+ ASSERT (0);
+ break;
+ }
+
+ SataPort->HostPRB->Control = Control;
+ SataPort->HostPRB->ProtocolOverride = Protocol;
+
+ // Clear IRQ
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_INTSTATUS_REG, IrqMask);
+
+ if (!FeaturePcdGet (PcdSataSiI3132FeatureDirectCommandIssuing)) {
+ // Indirect Command Issuance
+
+ //TODO: Find which slot is free (maybe use the Cmd FIFO)
+ //SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_CMDEXECFIFO_REG, &EmptySlot);
+
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_CMDACTIV_REG + (EmptySlot * 8),
+ (UINT32)(SataPort->PhysAddrHostPRB & 0xFFFFFFFF));
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_CMDACTIV_REG + (EmptySlot * 8) + 4,
+ (UINT32)((SataPort->PhysAddrHostPRB >> 32) & 0xFFFFFFFF));
+ } else {
+ // Direct Command Issuance
+ Status = PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, // Bar 1
+ SataPort->RegBase + (EmptySlot * 0x80),
+ sizeof (SATA_SI3132_PRB) / 4,
+ SataPort->HostPRB);
+ ASSERT_EFI_ERROR (Status);
+
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_CMDEXECFIFO_REG, EmptySlot);
+ }
+
+#if 0
+ // Could need to be implemented if we run multiple command in parallel to know which slot has been completed
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_SLOTSTATUS_REG, &Value32);
+ Timeout = Packet->Timeout;
+ while (!Timeout && !Value32) {
+ gBS->Stall (1);
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_SLOTSTATUS_REG, &Value32);
+ Timeout--;
+ }
+#else
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_INTSTATUS_REG, &Value32);
+ if (!Packet->Timeout) {
+ while (!(Value32 & IrqMask)) {
+ gBS->Stall (1);
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_INTSTATUS_REG, &Value32);
+ }
+ } else {
+ Timeout = Packet->Timeout;
+ while (Timeout && !(Value32 & IrqMask)) {
+ gBS->Stall (1);
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_INTSTATUS_REG, &Value32);
+ Timeout--;
+ }
+ }
+#endif
+ // Fill Packet Ata Status Block
+ Status = PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, // Bar 1
+ SataPort->RegBase + 0x08,
+ sizeof (EFI_ATA_STATUS_BLOCK) / 4,
+ Packet->Asb);
+ ASSERT_EFI_ERROR (Status);
+
+
+ if ((Packet->Timeout != 0) && (Timeout == 0)) {
+ DEBUG ((EFI_D_ERROR, "SiI3132AtaPassThru() Err:Timeout\n"));
+ //ASSERT (0);
+ return EFI_TIMEOUT;
+ } else if (Value32 & (SII3132_PORT_INT_CMDERR << 16)) {
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_CMDERROR_REG, &Error);
+ DEBUG ((EFI_D_ERROR, "SiI3132AtaPassThru() CmdErr:0x%X (SiI3132 Err:0x%X)\n", Value32, Error));
+ ASSERT (0);
+ return EFI_DEVICE_ERROR;
+ } else if (Value32 & (SII3132_PORT_INT_CMDCOMPL << 16)) {
+ // Clear Command Complete
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_INTSTATUS_REG, SII3132_PORT_INT_CMDCOMPL << 16);
+
+ if (PciAllocMapping) {
+ Status = PciIo->Unmap (PciIo, PciAllocMapping);
+ ASSERT (!EFI_ERROR (Status));
+ }
+
+ // If the command was ATA_CMD_IDENTIFY_DRIVE then we need to update the BlockSize
+ if (Packet->Acb->AtaCommand == ATA_CMD_IDENTIFY_DRIVE) {
+ ATA_IDENTIFY_DATA *IdentifyData = (ATA_IDENTIFY_DATA*)Packet->InDataBuffer;
+
+ // Get the corresponding Block Device
+ SataDevice = GetSataDevice (SataSiI3132Instance, SataPort->Index, PortMultiplierPort);
+
+ // Check logical block size
+ if ((IdentifyData->phy_logic_sector_support & BIT12) != 0) {
+ ASSERT (SataDevice != NULL);
+ SataDevice->BlockSize = (UINT32) (((IdentifyData->logic_sector_size_hi << 16) |
+ IdentifyData->logic_sector_size_lo) * sizeof (UINT16));
+ } else {
+ SataDevice->BlockSize = 0x200;
+ }
+ }
+ return EFI_SUCCESS;
+ } else {
+ ASSERT (0);
+ return EFI_DEVICE_ERROR;
+ }
+}
+
+/**
+ Sends an ATA command to an ATA device that is attached to the ATA controller. This function
+ supports both blocking I/O and non-blocking I/O. The blocking I/O functionality is required,
+ and the non-blocking I/O functionality is optional.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number of the ATA device to send the command.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to send the command.
+ If there is no port multiplier, then specify 0.
+ @param[in,out] Packet A pointer to the ATA command to send to the ATA device specified by Port
+ and PortMultiplierPort.
+ @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking
+ I/O is performed. If Event is NULL, then blocking I/O is performed. If
+ Event is not NULL and non blocking I/O is supported, then non-blocking
+ I/O is performed, and Event will be signaled when the ATA command completes.
+
+ @retval EFI_SUCCESS The ATA command was sent by the host. For bi-directional commands,
+ InTransferLength bytes were transferred from InDataBuffer. For write and
+ bi-directional commands, OutTransferLength bytes were transferred by OutDataBuffer.
+ @retval EFI_BAD_BUFFER_SIZE The ATA command was not executed. The number of bytes that could be transferred
+ is returned in InTransferLength. For write and bi-directional commands,
+ OutTransferLength bytes were transferred by OutDataBuffer.
+ @retval EFI_NOT_READY The ATA command could not be sent because there are too many ATA commands
+ already queued. The caller may retry again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the ATA command.
+ @retval EFI_INVALID_PARAMETER Port, PortMultiplierPort, or the contents of Acb are invalid. The ATA
+ command was not sent, so no additional status information is available.
+
+**/
+EFI_STATUS
+EFIAPI
+SiI3132AtaPassThru (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
+ )
+{
+ SATA_SI3132_INSTANCE *SataSiI3132Instance;
+ SATA_SI3132_DEVICE *SataDevice;
+ SATA_SI3132_PORT *SataPort;
+
+ SataSiI3132Instance = INSTANCE_FROM_ATAPASSTHRU_THIS (This);
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ SataDevice = GetSataDevice (SataSiI3132Instance, Port, PortMultiplierPort);
+ if (!SataDevice) {
+ return EFI_INVALID_PARAMETER;
+ }
+ SataPort = SataDevice->Port;
+
+ DEBUG ((EFI_D_INFO, "SiI3132AtaPassThru(%d,%d) : AtaCmd:0x%X Prot:%d\n", Port, PortMultiplierPort,
+ Packet->Acb->AtaCommand, Packet->Protocol));
+
+ return SiI3132AtaPassThruCommand (SataSiI3132Instance, SataPort, PortMultiplierPort, Packet, Event);
+}
+
+/**
+ Used to retrieve the list of legal port numbers for ATA devices on an ATA controller.
+ These can either be the list of ports where ATA devices are actually present or the
+ list of legal port numbers for the ATA controller. Regardless, the caller of this
+ function must probe the port number returned to see if an ATA device is actually
+ present at that location on the ATA controller.
+
+ The GetNextPort() function retrieves the port number on an ATA controller. If on input
+ Port is 0xFFFF, then the port number of the first port on the ATA controller is returned
+ in Port and EFI_SUCCESS is returned.
+
+ If Port is a port number that was returned on a previous call to GetNextPort(), then the
+ port number of the next port on the ATA controller is returned in Port, and EFI_SUCCESS
+ is returned. If Port is not 0xFFFF and Port was not returned on a previous call to
+ GetNextPort(), then EFI_INVALID_PARAMETER is returned.
+
+ If Port is the port number of the last port on the ATA controller, then EFI_NOT_FOUND is
+ returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in,out] Port On input, a pointer to the port number on the ATA controller.
+ On output, a pointer to the next port number on the ATA
+ controller. An input value of 0xFFFF retrieves the first port
+ number on the ATA controller.
+
+ @retval EFI_SUCCESS The next port number on the ATA controller was returned in Port.
+ @retval EFI_NOT_FOUND There are no more ports on this ATA controller.
+ @retval EFI_INVALID_PARAMETER Port is not 0xFFFF and Port was not returned on a previous call
+ to GetNextPort().
+
+**/
+EFI_STATUS
+EFIAPI
+SiI3132GetNextPort (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT16 *Port
+ )
+{
+ SATA_SI3132_INSTANCE *SataSiI3132Instance;
+ UINTN PrevPort;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ SataSiI3132Instance = INSTANCE_FROM_ATAPASSTHRU_THIS (This);
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PrevPort = *Port;
+
+ if (PrevPort == 0xFFFF) {
+ *Port = 0;
+ } else {
+ if (PrevPort < SATA_SII3132_MAXPORT) {
+ *Port = PrevPort + 1;
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+ }
+ return Status;
+}
+
+/**
+ Used to retrieve the list of legal port multiplier port numbers for ATA devices on a port of an ATA
+ controller. These can either be the list of port multiplier ports where ATA devices are actually
+ present on port or the list of legal port multiplier ports on that port. Regardless, the caller of this
+ function must probe the port number and port multiplier port number returned to see if an ATA
+ device is actually present.
+
+ The GetNextDevice() function retrieves the port multiplier port number of an ATA device
+ present on a port of an ATA controller.
+
+ If PortMultiplierPort points to a port multiplier port number value that was returned on a
+ previous call to GetNextDevice(), then the port multiplier port number of the next ATA device
+ on the port of the ATA controller is returned in PortMultiplierPort, and EFI_SUCCESS is
+ returned.
+
+ If PortMultiplierPort points to 0xFFFF, then the port multiplier port number of the first
+ ATA device on port of the ATA controller is returned in PortMultiplierPort and
+ EFI_SUCCESS is returned.
+
+ If PortMultiplierPort is not 0xFFFF and the value pointed to by PortMultiplierPort
+ was not returned on a previous call to GetNextDevice(), then EFI_INVALID_PARAMETER
+ is returned.
+
+ If PortMultiplierPort is the port multiplier port number of the last ATA device on the port of
+ the ATA controller, then EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number present on the ATA controller.
+ @param[in,out] PortMultiplierPort On input, a pointer to the port multiplier port number of an
+ ATA device present on the ATA controller.
+ If on input a PortMultiplierPort of 0xFFFF is specified,
+ then the port multiplier port number of the first ATA device
+ is returned. On output, a pointer to the port multiplier port
+ number of the next ATA device present on an ATA controller.
+
+ @retval EFI_SUCCESS The port multiplier port number of the next ATA device on the port
+ of the ATA controller was returned in PortMultiplierPort.
+ @retval EFI_NOT_FOUND There are no more ATA devices on this port of the ATA controller.
+ @retval EFI_INVALID_PARAMETER PortMultiplierPort is not 0xFFFF, and PortMultiplierPort was not
+ returned on a previous call to GetNextDevice().
+
+**/
+EFI_STATUS
+EFIAPI
+SiI3132GetNextDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN OUT UINT16 *PortMultiplierPort
+ )
+{
+ SATA_SI3132_INSTANCE *SataSiI3132Instance;
+ SATA_SI3132_PORT *SataPort;
+ SATA_SI3132_DEVICE *SataDevice;
+ LIST_ENTRY *List;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ SataSiI3132Instance = INSTANCE_FROM_ATAPASSTHRU_THIS (This);
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Port >= SATA_SII3132_MAXPORT) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ SataPort = &(SataSiI3132Instance->Ports[Port]);
+
+ if (*PortMultiplierPort == 0xFFFF) {
+ List = SataPort->Devices.ForwardLink;
+ if (List != &SataPort->Devices) {
+ // The list is not empty, return the first device
+ *PortMultiplierPort = ((SATA_SI3132_DEVICE*)List)->Index;
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+ } else {
+ SataDevice = GetSataDevice (SataSiI3132Instance, Port, *PortMultiplierPort);
+ if (SataDevice != NULL) {
+ // We have found the previous port multiplier, return the next one
+ List = SataDevice->Link.ForwardLink;
+ if (List != &SataPort->Devices) {
+ *PortMultiplierPort = ((SATA_SI3132_DEVICE*)List)->Index;
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+ }
+ return Status;
+}
+
+/**
+ Used to allocate and build a device path node for an ATA device on an ATA controller.
+
+ The BuildDevicePath() function allocates and builds a single device node for the ATA
+ device specified by Port and PortMultiplierPort. If the ATA device specified by Port and
+ PortMultiplierPort is not present on the ATA controller, then EFI_NOT_FOUND is returned.
+ If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. If there are not enough
+ resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
+
+ Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of
+ DevicePath are initialized to describe the ATA device specified by Port and PortMultiplierPort,
+ and EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port Port specifies the port number of the ATA device for which a
+ device path node is to be allocated and built.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device for which a
+ device path node is to be allocated and built. If there is no
+ port multiplier, then specify 0.
+ @param[in,out] DevicePath A pointer to a single device path node that describes the ATA
+ device specified by Port and PortMultiplierPort. This function
+ is responsible for allocating the buffer DevicePath with the
+ boot service AllocatePool(). It is the caller's responsibility
+ to free DevicePath when the caller is finished with DevicePath.
+ @retval EFI_SUCCESS The device path node that describes the ATA device specified by
+ Port and PortMultiplierPort was allocated and returned in DevicePath.
+ @retval EFI_NOT_FOUND The ATA device specified by Port and PortMultiplierPort does not
+ exist on the ATA controller.
+ @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath.
+
+**/
+EFI_STATUS
+EFIAPI
+SiI3132BuildDevicePath (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ )
+{
+ SATA_SI3132_INSTANCE *SataSiI3132Instance;
+ SATA_SI3132_DEVICE *SataDevice;
+ EFI_DEVICE_PATH_PROTOCOL *SiI3132DevicePath;
+
+ SATA_TRACE ("SiI3132BuildDevicePath()");
+
+ SataSiI3132Instance = INSTANCE_FROM_ATAPASSTHRU_THIS (This);
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ SataDevice = GetSataDevice (SataSiI3132Instance, Port, PortMultiplierPort);
+ if (SataDevice == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ SiI3132DevicePath = CreateDeviceNode (MESSAGING_DEVICE_PATH, MSG_SATA_DP, sizeof (SATA_DEVICE_PATH));
+ if (SiI3132DevicePath == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ((SATA_DEVICE_PATH*)SiI3132DevicePath)->HBAPortNumber = Port;
+ if (FeaturePcdGet (PcdSataSiI3132FeaturePMPSupport)) {
+ ((SATA_DEVICE_PATH*)SiI3132DevicePath)->PortMultiplierPortNumber = PortMultiplierPort;
+ } else {
+ //Temp:((SATA_DEVICE_PATH*)SiI3132DevicePath)->PortMultiplierPortNumber = SATA_HBA_DIRECT_CONNECT_FLAG;
+ ((SATA_DEVICE_PATH*)SiI3132DevicePath)->PortMultiplierPortNumber = 0;
+ }
+ ((SATA_DEVICE_PATH*)SiI3132DevicePath)->Lun = Port; //TODO: Search information how to define properly LUN (Logical Unit Number)
+
+ *DevicePath = SiI3132DevicePath;
+ return EFI_SUCCESS;
+}
+
+/**
+ Used to translate a device path node to a port number and port multiplier port number.
+
+ The GetDevice() function determines the port and port multiplier port number associated with
+ the ATA device described by DevicePath. If DevicePath is a device path node type that the
+ ATA Pass Thru driver supports, then the ATA Pass Thru driver will attempt to translate the contents
+ DevicePath into a port number and port multiplier port number.
+
+ If this translation is successful, then that port number and port multiplier port number are returned
+ in Port and PortMultiplierPort, and EFI_SUCCESS is returned.
+
+ If DevicePath, Port, or PortMultiplierPort are NULL, then EFI_INVALID_PARAMETER is returned.
+
+ If DevicePath is not a device path node type that the ATA Pass Thru driver supports, then
+ EFI_UNSUPPORTED is returned.
+
+ If DevicePath is a device path node type that the ATA Pass Thru driver supports, but there is not
+ a valid translation from DevicePath to a port number and port multiplier port number, then
+ EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] DevicePath A pointer to the device path node that describes an ATA device on the
+ ATA controller.
+ @param[out] Port On return, points to the port number of an ATA device on the ATA controller.
+ @param[out] PortMultiplierPort On return, points to the port multiplier port number of an ATA device
+ on the ATA controller.
+
+ @retval EFI_SUCCESS DevicePath was successfully translated to a port number and port multiplier
+ port number, and they were returned in Port and PortMultiplierPort.
+ @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+ @retval EFI_INVALID_PARAMETER Port is NULL.
+ @retval EFI_INVALID_PARAMETER PortMultiplierPort is NULL.
+ @retval EFI_UNSUPPORTED This driver does not support the device path node type in DevicePath.
+ @retval EFI_NOT_FOUND A valid translation from DevicePath to a port number and port multiplier
+ port number does not exist.
+**/
+EFI_STATUS
+EFIAPI
+SiI3132GetDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT16 *Port,
+ OUT UINT16 *PortMultiplierPort
+ )
+{
+ SATA_SI3132_INSTANCE *SataSiI3132Instance;
+
+ SATA_TRACE ("SiI3132GetDevice()");
+
+ if (!DevicePath || !Port || !PortMultiplierPort) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((DevicePath->Type != MESSAGING_DEVICE_PATH) || (DevicePath->SubType != MSG_SATA_DP)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ SataSiI3132Instance = INSTANCE_FROM_ATAPASSTHRU_THIS (This);
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (((SATA_DEVICE_PATH*)DevicePath)->Lun >= SATA_SII3132_MAXPORT) {
+ return EFI_NOT_FOUND;
+ }
+
+ if (FeaturePcdGet (PcdSataSiI3132FeaturePMPSupport)) {
+ ASSERT (0); //TODO: Implement me!
+ return EFI_UNSUPPORTED;
+ } else {
+ *Port = ((SATA_DEVICE_PATH*)DevicePath)->Lun;
+ // Return the first Sata Device as there should be only one directly connected
+ *PortMultiplierPort = ((SATA_SI3132_DEVICE*)SataSiI3132Instance->Ports[*Port].Devices.ForwardLink)->Index;
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+SiI3132HwResetPort (
+ IN SATA_SI3132_PORT *SataPort
+ )
+{
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 Value32;
+ UINTN Timeout;
+
+ SATA_TRACE ("SiI3132HwResetPort()");
+
+ PciIo = SataPort->Instance->PciIo;
+
+ // Clear Port Reset
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_CONTROLCLEAR_REG, SII3132_PORT_CONTROL_RESET);
+
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_STATUS_REG, &Value32);
+ ASSERT (!(Value32 & SII3132_PORT_CONTROL_RESET));
+
+ // Initialize error counters
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_ERRCOUNTDECODE, 0);
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_ERRCOUNTCRC, 0);
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_ERRCOUNTHANDSHAKE, 0);
+
+ // Enable interrupts for command completion and command errors
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_ENABLEINT_REG, SII3132_PORT_INT_CMDCOMPL | SII3132_PORT_INT_CMDERR);
+
+ // Clear IRQ
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_ENABLEINT_REG, SII3132_PORT_INT_CMDCOMPL | SII3132_PORT_INT_CMDERR | SII3132_PORT_INT_PORTRDY | (1 << 3));
+
+ // Wait until Port Ready
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_INTSTATUS_REG, &Value32);
+ Timeout = 1000;
+ while ((Timeout > 0) && ((Value32 & SII3132_PORT_INT_PORTRDY) == 0)) {
+ gBS->Stall (1);
+ Timeout--;
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_INTSTATUS_REG, &Value32);
+ }
+ // Clear IRQ
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_INTSTATUS_REG, SII3132_PORT_INT_PORTRDY);
+
+ if (Timeout == 0) {
+ SATA_TRACE ("SiI3132HwResetPort(): Timeout");
+ return EFI_TIMEOUT;
+ } else if ((Value32 & SII3132_PORT_INT_PORTRDY) == 0) {
+ SATA_TRACE ("SiI3132HwResetPort(): Port Not Ready");
+ return EFI_DEVICE_ERROR;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+/**
+ Resets a specific port on the ATA controller. This operation also resets all the ATA devices
+ connected to the port.
+
+ The ResetChannel() function resets an a specific port on an ATA controller. This operation
+ resets all the ATA devices connected to that port. If this ATA controller does not support
+ a reset port operation, then EFI_UNSUPPORTED is returned.
+
+ If a device error occurs while executing that port reset operation, then EFI_DEVICE_ERROR is
+ returned.
+
+ If a timeout occurs during the execution of the port reset operation, then EFI_TIMEOUT is returned.
+
+ If the port reset operation is completed, then EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number on the ATA controller.
+
+ @retval EFI_SUCCESS The ATA controller port was reset.
+ @retval EFI_UNSUPPORTED The ATA controller does not support a port reset operation.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA port.
+ @retval EFI_TIMEOUT A timeout occurred while attempting to reset the ATA port.
+
+**/
+EFI_STATUS
+EFIAPI
+SiI3132ResetPort (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port
+ )
+{
+ SATA_SI3132_INSTANCE *SataSiI3132Instance;
+ SATA_SI3132_PORT *SataPort;
+
+ SATA_TRACE ("SiI3132ResetPort()");
+
+ SataSiI3132Instance = INSTANCE_FROM_ATAPASSTHRU_THIS (This);
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Port >= SATA_SII3132_MAXPORT) {
+ return EFI_UNSUPPORTED;
+ }
+
+ SataPort = &(SataSiI3132Instance->Ports[Port]);
+ return SiI3132HwResetPort (SataPort);
+}
+
+/**
+ Resets an ATA device that is connected to an ATA controller.
+
+ The ResetDevice() function resets the ATA device specified by Port and PortMultiplierPort.
+ If this ATA controller does not support a device reset operation, then EFI_UNSUPPORTED is
+ returned.
+
+ If Port or PortMultiplierPort are not in a valid range for this ATA controller, then
+ EFI_INVALID_PARAMETER is returned.
+
+ If a device error occurs while executing that device reset operation, then EFI_DEVICE_ERROR
+ is returned.
+
+ If a timeout occurs during the execution of the device reset operation, then EFI_TIMEOUT is
+ returned.
+
+ If the device reset operation is completed, then EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port Port represents the port number of the ATA device to be reset.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to reset.
+ If there is no port multiplier, then specify 0.
+ @retval EFI_SUCCESS The ATA device specified by Port and PortMultiplierPort was reset.
+ @retval EFI_UNSUPPORTED The ATA controller does not support a device reset operation.
+ @retval EFI_INVALID_PARAMETER Port or PortMultiplierPort are invalid.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA device
+ specified by Port and PortMultiplierPort.
+ @retval EFI_TIMEOUT A timeout occurred while attempting to reset the ATA device
+ specified by Port and PortMultiplierPort.
+
+**/
+EFI_STATUS
+EFIAPI
+SiI3132ResetDevice (
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort
+ )
+{
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ SATA_SI3132_INSTANCE *SataSiI3132Instance;
+ SATA_SI3132_PORT *SataPort;
+ SATA_SI3132_DEVICE *SataDevice;
+ UINTN Timeout;
+ UINT32 Value32;
+
+ SATA_TRACE ("SiI3132ResetDevice()");
+
+ SataSiI3132Instance = INSTANCE_FROM_ATAPASSTHRU_THIS (This);
+ if (!SataSiI3132Instance) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PciIo = SataSiI3132Instance->PciIo;
+
+ SataDevice = GetSataDevice (SataSiI3132Instance, Port, PortMultiplierPort);
+ if (!SataDevice) {
+ return EFI_INVALID_PARAMETER;
+ }
+ SataPort = SataDevice->Port;
+
+ SATA_PORT_WRITE32 (SataPort->RegBase + SII3132_PORT_CONTROLSET_REG, SII3132_PORT_DEVICE_RESET);
+
+ Timeout = 100;
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_STATUS_REG, &Value32);
+ while ((Timeout > 0) && ((Value32 & SII3132_PORT_DEVICE_RESET) != 0)) {
+ gBS->Stall (1);
+ SATA_PORT_READ32 (SataPort->RegBase + SII3132_PORT_STATUS_REG, &Value32);
+ Timeout--;
+ }
+
+ if (Timeout == 0) {
+ SATA_TRACE ("SiI3132ResetDevice(): Timeout");
+ return EFI_TIMEOUT;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [edk2-devel] [PATCH edk2-platforms v2 1/2] Platform/ARM/VExpressPkg: incorporate PL180 driver
2020-04-30 8:25 ` [PATCH edk2-platforms v2 1/2] Platform/ARM/VExpressPkg: incorporate PL180 driver Ard Biesheuvel
@ 2020-04-30 10:06 ` Philippe Mathieu-Daudé
2020-04-30 10:47 ` Ard Biesheuvel
0 siblings, 1 reply; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-04-30 10:06 UTC (permalink / raw)
To: devel, ard.biesheuvel; +Cc: leif
Hi Ard,
On 4/30/20 10:25 AM, Ard Biesheuvel wrote:
> The PL180 SD host controller driver is only used on emulated ARM
> platforms, uses an obsolete version of the MMC host protocol and
> does not adhere to the UEFI driver model.
>
> Given the above, let's just move it into VExpressPkg where it
> belongs.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
> ---
> Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc | 6 +-
> Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf | 2 +-
> Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 6 +-
> Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf | 2 +-
> Platform/ARM/VExpressPkg/ArmVExpressPkg.dec | 4 +
> Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c | 570 ++++++++++++++++++++
> Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.h | 169 ++++++
> Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf | 53 ++
> 8 files changed, 804 insertions(+), 8 deletions(-)
>
[...]
> diff --git a/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c
> new file mode 100644
> index 000000000000..8526bb41600e
> --- /dev/null
> +++ b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c
> @@ -0,0 +1,570 @@
> +/** @file
> + This file implement the MMC Host Protocol for the ARM PrimeCell PL180.
> +
> + WARNING:
> + This driver fails to follow the UEFI driver model without a good
> + reason, and only remains in the tree because it is still used by
> + a small number of platforms. It will removed when no longer used.
I suppose "It will [be] removed"? (2 other occurrences in this patch).
Otherwise:
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
> + New platforms should not use it, and no one should use this as
> + reference code for developing new drivers.
> +
> + Copyright (c) 2011-2020, ARM Limited. All rights reserved.
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
[...]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [edk2-devel] [PATCH edk2-platforms v2 1/2] Platform/ARM/VExpressPkg: incorporate PL180 driver
2020-04-30 10:06 ` [edk2-devel] " Philippe Mathieu-Daudé
@ 2020-04-30 10:47 ` Ard Biesheuvel
0 siblings, 0 replies; 5+ messages in thread
From: Ard Biesheuvel @ 2020-04-30 10:47 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, devel; +Cc: leif
On 4/30/20 12:06 PM, Philippe Mathieu-Daudé wrote:
> Hi Ard,
>
> On 4/30/20 10:25 AM, Ard Biesheuvel wrote:
>> The PL180 SD host controller driver is only used on emulated ARM
>> platforms, uses an obsolete version of the MMC host protocol and
>> does not adhere to the UEFI driver model.
>>
>> Given the above, let's just move it into VExpressPkg where it
>> belongs.
>>
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
>> ---
>> Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc | 6 +-
>> Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf | 2 +-
>> Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 6 +-
>> Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf | 2 +-
>> Platform/ARM/VExpressPkg/ArmVExpressPkg.dec | 4 +
>> Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c | 570
>> ++++++++++++++++++++
>> Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.h | 169
>> ++++++
>> Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180MciDxe.inf | 53 ++
>> 8 files changed, 804 insertions(+), 8 deletions(-)
>>
> [...]
>> diff --git a/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c
>> b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c
>> new file mode 100644
>> index 000000000000..8526bb41600e
>> --- /dev/null
>> +++ b/Platform/ARM/VExpressPkg/Drivers/PL180MciDxe/PL180Mci.c
>> @@ -0,0 +1,570 @@
>> +/** @file
>> + This file implement the MMC Host Protocol for the ARM PrimeCell PL180.
>> +
>> + WARNING:
>> + This driver fails to follow the UEFI driver model without a good
>> + reason, and only remains in the tree because it is still used by
>> + a small number of platforms. It will removed when no longer used.
>
> I suppose "It will [be] removed"? (2 other occurrences in this patch).
>
Ah yes thanks for spotting that.
> Otherwise:
> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
>
>> + New platforms should not use it, and no one should use this as
>> + reference code for developing new drivers.
>> +
>> + Copyright (c) 2011-2020, ARM Limited. All rights reserved.
>> +
>> + SPDX-License-Identifier: BSD-2-Clause-Patent
>> +
>> +**/
> [...]
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-30 10:47 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-04-30 8:25 [PATCH edk2-platforms v2 0/2] move obsolete platform drivers out of core edk2 Ard Biesheuvel
2020-04-30 8:25 ` [PATCH edk2-platforms v2 1/2] Platform/ARM/VExpressPkg: incorporate PL180 driver Ard Biesheuvel
2020-04-30 10:06 ` [edk2-devel] " Philippe Mathieu-Daudé
2020-04-30 10:47 ` Ard Biesheuvel
2020-04-30 8:25 ` [PATCH edk2-platforms v2 2/2] Platform/ARM/JunoPkg: incorporate SiI3132 SATA controller driver Ard Biesheuvel
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