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X-Microsoft-Antispam-Message-Info: yfcpXbhT9g9vQDk5H4N+1G5wC17tsNx5ctgtqWN/NF4o1JeKNFwGqoTG+rP6CXkaunrc+HawuXcFXjQlNwKxh0vieHYxM7MAfn0lEjpOabCAdD/H/TwzIUjsatA19ftmydlEWt7Zm/0uJlvw4sR8EHBr17wcinKyDLA3lRXu02nBIeUSAHTopM2ZPp76mj6obIiwS3hiTMl3UtGp7X56AoKm9uYHBBok0dph20wCbOgDvQdeoMU4JfhM9Te9iGJrUTIuxc9mnbzqpnss5hk5tyQWcsAjcl0QLZjy48OAcDtwtnNpM36DWylGqKKAyJODmCnQTwidEhdDcSa/aNvYDSkamv8ZqbKiJX+uUCzltaBsPZTZS6ZfIsjub9qlzhgPPIlrrFaNBt73y67f9Ry4F06Fi/twuQWUJCL1CdWqvjEdOLZOBm3rl13ZMeI942Bo X-MS-Exchange-AntiSpam-MessageData: 03jc9JnU6Rdi08dwNRyHhZyACfO80c+0RIB1KKKz3qbPujDDpdESxXr/FkjJ62G7qVfdN/4yLiZi2aObWzfLitRTc/1WSeW/HnuziT51ONvblmF4LyIqNe3+13HAUG7Fmnswmksh3GHIUX5RPloAswRJbmIgwUrukzNhEHCb4tEgfg2rSD0lNZBPQS3o3XUsj9esO18ZE49mvGuTiQhEjBQeQ41Ud8uIuCQoiOE9KbwSbImGovz/orulfiFY8AfMowO7EL4ZvzDZ+CPeXpS3uAi74WV7V7V5jFD8kOJqPk97XCoasOo8OAHbKxLqV49gyfRjzfaOqaS31hguxa1h/qp11Rz2ZNhv5nEOsbZ9GMcBM76hKQMZ0NnzsiH9ntRpGrXYv8Nshb4mF3deJaLXnc1O2KyVv0Rh6KUBBA3uhirh2Mr4HeOgBt98ym1STvGtsTj6FF+IwrwXPLYokbz88BJytPlS0OxeoRzS/1/RZzr7VGZuiMEzRn5ruYpsj7ZOlLuUa0ktSvOUyWAVYpG8FQJKyFFBRGXyFjX5bP96C2aGtTWbr3/6tGpq+rAGVZ4M9OvVlMeB5t3NHZHAXmZDJTupSAhIYN5ZBVpWcVRNjhD/M4U8v/GTHPrLSuG+xDddEcPoIjsj3bUxA2//bAzIRC6YVT6/FXAcjcH8xuiFflX3ldoGx4QOUz6/r0dMypWq02Msm7DglaYQtSMFSU0JK7d7oSuR6vwaP3RXyZyE5a9IrnbXt0WiqUy411zp6U2cloG+M9/tvHfODDRjrDUVrEI54fLIdt6evJtvBJtf4zg= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6ebbbb2a-7392-4d42-6bfa-08d7ecca8b16 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2020 05:51:35.9134 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9mc6lMnSvIbFqm/ky+9hOtXSN7ICYXxYNyWzG5DQ3z6vY4BESvjOkeA+ZbEGiFiwh+fF/eh3EM0p0u0dRxL1Ww== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4429 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Pankaj Bansal RAM retrieval using SMC commands is common to all Layerscape SOCs. Therefore, move it to common MemoryInit Pei Lib. Signed-off-by: Pankaj Bansal --- Notes: V4: - fixed line adds white space error in MemoryInitPeiLib.h - Added SMC_OK and SMC_UOK Macros to denote the return values from SMC calls - Added explanation for SMC_DRAM_BANK_INFO and DRAM_REGION_INFO in MemoryInitPeiLib.h - Modified GetDramSize to check for return value of SMC call against SMC_OK. Also added comments when returning 0 from this function - Modified GetDramRegionsInfo for loop and return values as per Leif's suggestion. Also added DEBUG_ERROR in case of return BUFFER_TOO_SMALL= . - Added SMC_OK in GetDramRegionsInfo - Check for GetDramRegionsInfo return value in MemoryPeim - regios -> regions =20 V3: - sort headers alphabetically - Moved DRAM region retrieval and Total DRAM size retrieval to separate functions - Fixed MemoryPeim function description - Modified check on FoundSystemMem =3D TRUE to check the RAM region aga= inst MemoryPeim function input arguments UefiMemoryBase and UefiMemorySize - (!DramRegions[Index].Size) =3D> (DramRegions[Index].Size =3D=3D 0) - (FoundSystemMem) =3D> (FoundSystemMem =3D=3D TRUE) - Added explanation for starting for loop from the last DRAM region Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 7 +- Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 - Silicon/NXP/Include/DramInfo.h | 38 ---- Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h | 38 ++++ Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 205 +++++++++++++= +++---- Silicon/NXP/Library/SocLib/Chassis.c | 67 ------- 6 files changed, 211 insertions(+), 145 deletions(-) diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silic= on/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf index a5bd39415def..ad2371115b17 100644 --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -18,7 +18,6 @@ [Sources] MemoryInitPeiLib.c =20 - [Packages] ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec @@ -30,6 +29,7 @@ [LibraryClasses] ArmMmuLib ArmPlatformLib + ArmSmcLib DebugLib HobLib PcdLib @@ -40,6 +40,11 @@ [FeaturePcd] gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob =20 +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Lib= rary/SocLib/LS1043aSocLib.inf index b7c7fc78cc8f..99d89498e0e2 100644 --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf @@ -20,7 +20,6 @@ Silicon/NXP/NxpQoriqLs.dec =20 [LibraryClasses] - ArmSmcLib BaseLib DebugLib IoAccessLib diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.= h deleted file mode 100644 index a934aaeff1f5..000000000000 --- a/Silicon/NXP/Include/DramInfo.h +++ /dev/null @@ -1,38 +0,0 @@ -/** @file -* Header defining the structure for Dram Information -* -* Copyright 2019 NXP -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef DRAM_INFO_H_ -#define DRAM_INFO_H_ - -#include - -#define SMC_DRAM_BANK_INFO (0xC200FF12) - -typedef struct { - UINTN BaseAddress; - UINTN Size; -} DRAM_REGION_INFO; - -typedef struct { - UINT32 NumOfDrams; - UINT32 Reserved; - DRAM_REGION_INFO DramRegion[3]; -} DRAM_INFO; - -EFI_STATUS -GetDramBankInfo ( - IN OUT DRAM_INFO *DramInfo - ); - -VOID -UpdateDpaaDram ( - IN OUT DRAM_INFO *DramInfo - ); - -#endif /* DRAM_INFO_H_ */ diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon= /NXP/Library/MemoryInitPei/MemoryInitPeiLib.h new file mode 100644 index 000000000000..7a41f4d226f1 --- /dev/null +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h @@ -0,0 +1,38 @@ +/** @file +* +* Copyright 2020 NXP +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef MEMORY_INIT_PEI_LIB_H_ +#define MEMORY_INIT_PEI_LIB_H_ + +#include + +// Specifies the Maximum regions onto which DDR memory can be mapped in +// a Platform +#define MAX_DRAM_REGIONS 3 + +// Unique SMC call to retrieve the total DDR RAM size installed in system +// and the SOC memory map regions to which DDR RAM is mapped +// This SMC call works in this way: +// x1 =3D -1 : return x0: SMC_OK, x1: total DDR Ram size +// x1 >=3D number of DRAM regions to which DDR RAM is mapped : return x0: = SMC_UNK +// 0 <=3D x1 < number of DRAM regions to which DDR RAM is mapped : return +// x0: SMC_OK, x1: Base address of DRAM region, +// x2: Size of DRAM region +#define SMC_DRAM_BANK_INFO (0xC200FF12) + +// Return values from SMC calls. return values are always in x0 +#define SMC_OK 0 +#define SMC_UNK -1 + +// Regions in SOC memory map to which DDR RAM is mapped. +typedef struct { + UINTN BaseAddress; + UINTN Size; +} DRAM_REGION_INFO; + +#endif // MEMORY_INIT_PEI_LIB_H_ diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon= /NXP/Library/MemoryInitPei/MemoryInitPeiLib.c index 3ea773678667..905d326893e5 100644 --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -12,13 +12,15 @@ =20 #include #include +#include #include #include #include #include #include =20 -#include +#include "MemoryInitPeiLib.h" + =20 VOID BuildMemoryTypeInformationHob ( @@ -44,22 +46,88 @@ InitMmu ( } } =20 -/*++ +STATIC +UINTN +GetDramSize ( + IN VOID + ) +{ + ARM_SMC_ARGS ArmSmcArgs; =20 -Routine Description: + ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; + ArmSmcArgs.Arg1 =3D -1; =20 + ArmCallSmc (&ArmSmcArgs); =20 + if (ArmSmcArgs.Arg0 =3D=3D SMC_OK) { + return ArmSmcArgs.Arg1; + } =20 -Arguments: + // return 0 means no DDR found. + return 0; +} =20 - FileHandle - Handle of the file being invoked. - PeiServices - Describes the list of possible PEI Services. +STATIC +EFI_STATUS +GetDramRegionsInfo ( + OUT DRAM_REGION_INFO *DramRegions, + IN UINT32 NumRegions + ) +{ + ARM_SMC_ARGS ArmSmcArgs; + UINT32 Index; + UINTN RemainingDramSize; + UINTN BaseAddress; + UINTN Size; =20 -Returns: + RemainingDramSize =3D GetDramSize (); + DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", RemainingDramSize)); =20 - Status - EFI_SUCCESS if the boot mode could be set + // Ensure Total Dram Size is valid + ASSERT (RemainingDramSize !=3D 0); =20 ---*/ + for (Index =3D 0; Index < NumRegions; Index++) { + ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; + ArmSmcArgs.Arg1 =3D Index; + + ArmCallSmc (&ArmSmcArgs); + + if (ArmSmcArgs.Arg0 =3D=3D SMC_OK) { + BaseAddress =3D ArmSmcArgs.Arg1; + Size =3D ArmSmcArgs.Arg2; + ASSERT (BaseAddress && Size); + + DramRegions[Index].BaseAddress =3D BaseAddress; + DramRegions[Index].Size =3D Size; + RemainingDramSize -=3D Size; + + DEBUG ((DEBUG_INFO, "DRAM Region[%d]: start 0x%lx, size 0x%lx\n", + Index, BaseAddress, Size)); + + if (RemainingDramSize =3D=3D 0) { + return EFI_SUCCESS; + } + } else { + break; + } + } + + DEBUG ((DEBUG_ERROR, "RemainingDramSize =3D %u !! Ensure that all DDR re= gions " + "have been accounted for\n", RemainingDramSize)); + + return EFI_BUFFER_TOO_SMALL; +} + +/** + Get the installed RAM information. + Initialize MMU and Memory HOBs (Resource Descriptor HOBs) + + @param[in] UefiMemoryBase Base address of region used by UEFI in + permanent memory + @param[in] UefiMemorySize Size of the region used by UEFI in permanent = memory + + @return EFI_SUCCESS Successfuly Initialize MMU and Memory HOBs. +**/ EFI_STATUS EFIAPI MemoryPeim ( @@ -67,11 +135,17 @@ MemoryPeim ( IN UINT64 UefiMemorySize ) { - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; - EFI_PEI_HOB_POINTERS NextHob; - BOOLEAN Found; - DRAM_INFO DramInfo; + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + INT32 Index; + UINTN BaseAddress; + UINTN Size; + UINTN Top; + DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS]; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + UINTN FdBase; + UINTN FdTop; + BOOLEAN FoundSystemMem; + EFI_STATUS Status; =20 // Get Virtual Memory Map from the Platform Library ArmPlatformGetVirtualMemoryMap (&MemoryTable); @@ -94,40 +168,95 @@ MemoryPeim ( EFI_RESOURCE_ATTRIBUTE_TESTED ); =20 - if (GetDramBankInfo (&DramInfo)) { - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n")); - return EFI_UNSUPPORTED; - } + FoundSystemMem =3D FALSE; + ZeroMem (DramRegions, sizeof (DramRegions)); =20 - while (DramInfo.NumOfDrams--) { - // - // Check if the resource for the main system memory has been declared - // - Found =3D FALSE; - NextHob.Raw =3D GetHobList (); - while ((NextHob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, = NextHob.Raw)) !=3D NULL) { - if ((NextHob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SY= STEM_MEMORY) && - (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >=3D NextH= ob.ResourceDescriptor->PhysicalStart) && - (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDes= criptor->ResourceLength <=3D - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo= .DramRegion[DramInfo.NumOfDrams].Size)) - { - Found =3D TRUE; - break; - } - NextHob.Raw =3D GET_NEXT_HOB (NextHob); + Status =3D GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions)); + ASSERT_EFI_ERROR (Status); + + FdBase =3D (UINTN)FixedPcdGet64 (PcdFdBaseAddress); + FdTop =3D FdBase + (UINTN)FixedPcdGet32 (PcdFdSize); + + // Declare memory regions to system + // The DRAM region info is sorted based on the RAM address is SOC memory= map. + // i.e. DramRegions[0] is at lower address, as compared to DramRegions[1= ]. + // The goal to start from last region is to find the topmost RAM region = that + // can contain UEFI DXE region i.e. PcdSystemMemoryUefiRegionSize. + // If UEFI were to allocate any reserved or runtime region, it would be + // allocated from topmost RAM region. + // This ensures that maximum amount of lower RAM (32 bit addresses) are = left + // for OS to allocate to devices that can only work with 32bit physical + // addresses. E.g. legacy devices that need to DMA to 32bit addresses. + for (Index =3D MAX_DRAM_REGIONS - 1; Index >=3D 0; Index--) { + if (DramRegions[Index].Size =3D=3D 0) { + continue; } =20 - if (!Found) { - // Reserved the memory space occupied by the firmware volume + BaseAddress =3D DramRegions[Index].BaseAddress; + Top =3D DramRegions[Index].BaseAddress + DramRegions[Index].Size; + + // EDK2 does not have the concept of boot firmware copied into DRAM. + // To avoid the DXE core to overwrite this area we must create a memor= y + // allocation HOB for the region, but this only works if we split off = the + // underlying resource descriptor as well. + if (FdBase >=3D BaseAddress && FdTop <=3D Top) { + // Update Size + Size =3D FdBase - BaseAddress; + if (Size) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + BaseAddress, + Size + ); + } + // create the System Memory HOB for the firmware BuildResourceDescriptorHob ( EFI_RESOURCE_SYSTEM_MEMORY, ResourceAttributes, - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress, - DramInfo.DramRegion[DramInfo.NumOfDrams].Size + FdBase, + PcdGet32 (PcdFdSize) ); + // Create the System Memory HOB for the remaining region (top of the= FD)s + Size =3D Top - FdTop; + if (Size) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FdTop, + Size + ); + }; + // Mark the memory covering the Firmware Device as boot services dat= a + BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress), + FixedPcdGet32 (PcdFdSize), + EfiBootServicesData); + } else { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + DramRegions[Index].BaseAddress, + DramRegions[Index].Size + ); + } + + if (FoundSystemMem =3D=3D TRUE) { + continue; + } + + Size =3D DramRegions[Index].Size; + + if (FdBase >=3D BaseAddress && FdTop <=3D Top) { + Size -=3D (UINTN)FixedPcdGet32 (PcdFdSize); + } + + if ((UefiMemoryBase >=3D BaseAddress) && (Size >=3D UefiMemorySize)) { + FoundSystemMem =3D TRUE; } } =20 + ASSERT (FoundSystemMem =3D=3D TRUE); + // Build Memory Allocation Hob InitMmu (MemoryTable); =20 diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/Soc= Lib/Chassis.c index 847331a63152..1ef99e8de25f 100644 --- a/Silicon/NXP/Library/SocLib/Chassis.c +++ b/Silicon/NXP/Library/SocLib/Chassis.c @@ -22,7 +22,6 @@ #include #include =20 -#include #include "NxpChassis.h" =20 UINT32 @@ -75,69 +74,3 @@ SmmuInit ( MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); } =20 -UINTN -GetDramSize ( - IN VOID - ) -{ - ARM_SMC_ARGS ArmSmcArgs; - - ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; - ArmSmcArgs.Arg1 =3D -1; - - ArmCallSmc (&ArmSmcArgs); - - if (ArmSmcArgs.Arg0) { - return 0; - } else { - return ArmSmcArgs.Arg1; - } -} - -EFI_STATUS -GetDramBankInfo ( - IN OUT DRAM_INFO *DramInfo - ) -{ - ARM_SMC_ARGS ArmSmcArgs; - UINT32 I; - UINTN DramSize; - - DramSize =3D GetDramSize (); - DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize)); - - // Ensure DramSize has been set - ASSERT (DramSize !=3D 0); - - I =3D 0; - - do { - ArmSmcArgs.Arg0 =3D SMC_DRAM_BANK_INFO; - ArmSmcArgs.Arg1 =3D I; - - ArmCallSmc (&ArmSmcArgs); - if (ArmSmcArgs.Arg0) { - if (I > 0) { - break; - } else { - ASSERT (ArmSmcArgs.Arg0 =3D=3D 0); - } - } - - DramInfo->DramRegion[I].BaseAddress =3D ArmSmcArgs.Arg1; - DramInfo->DramRegion[I].Size =3D ArmSmcArgs.Arg2; - - DramSize -=3D DramInfo->DramRegion[I].Size; - - DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", - I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size= )); - - I++; - } while (DramSize); - - DramInfo->NumOfDrams =3D I; - - DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDra= ms)); - - return EFI_SUCCESS; -} --=20 2.17.1