From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.17390.1589127269924431738 for ; Sun, 10 May 2020 09:14:43 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ashraf.javeed@intel.com) IronPort-SDR: cOszDKNc+W1EYzLaT3Kxkan1If26KAgCde63yyDvmQWAs632ZWsVWjeuNJPWkGYZQsmUNRFFep n8Qs5z9YxOgQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2020 09:14:42 -0700 IronPort-SDR: uEpMd4TyrrvtYPXAM0MnIVA7Gq7Mscg9UXwUURP4fEUBloa1J/v6EHQcMDSlYB0D6HXoVB7K2s exCc+BswOaLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,376,1583222400"; d="scan'208";a="463129679" Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.37]) by fmsmga006.fm.intel.com with ESMTP; 10 May 2020 09:14:40 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Ray Ni , Jian J Wang , Hao A Wu Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/15] MdeModulePkg/PciBusDxe: Enable RelaxedOrdering feature Date: Sun, 10 May 2020 21:44:06 +0530 Message-Id: <20200510161412.13832-10-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200510161412.13832-1-ashraf.javeed@intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1954 https://bugzilla.tianocore.org/show_bug.cgi?id=2194 https://bugzilla.tianocore.org/show_bug.cgi?id=2313 https://bugzilla.tianocore.org/show_bug.cgi?id=2499 https://bugzilla.tianocore.org/show_bug.cgi?id=2500 Add the Program phase feature init routine for RelaxedOrdering PCIe feature. Signed-off-by: Ashraf Javeed Signed-off-by: Ray Ni Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni Cc: Ashraf Javeed --- MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 7 +++++++ 3 files changed, 59 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c index e1f739e..9948e17 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c @@ -56,6 +56,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = { TRUE, { TRUE, TRUE }, { MaxPayloadSizeScan, MaxPayloadSizeProgram } }, { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxReadRequestSize), TRUE, { TRUE, TRUE }, { NULL, MaxReadRequestSizeProgram } }, + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, RelaxedOrdering), + TRUE, { TRUE, TRUE }, { NULL, RelaxedOrderingProgram } }, }; /** @@ -230,6 +232,7 @@ PcieNotifyDeviceState ( PcieDeviceState.MaxPayloadSize = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.MaxPayloadSize; PcieDeviceState.MaxReadRequestSize = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize; + PcieDeviceState.RelaxedOrdering = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering; return mPciePlatformProtocol->NotifyDeviceState ( mPciePlatformProtocol, PciIoDevice->Handle, diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c index a7591e6..5216dac 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c @@ -167,3 +167,52 @@ MaxReadRequestSizeProgram ( return EFI_SUCCESS; } + +/** + Program the PCIe Device Control register Relaxed Ordering field per platform policy. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. + + @retval EFI_SUCCESS The data was read from or written to the PCI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI configuration header of the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. +**/ +EFI_STATUS +RelaxedOrderingProgram ( + IN PCI_IO_DEVICE *PciDevice, + IN UINTN Level, + IN VOID **Context + ) +{ + ASSERT (*Context == NULL); + + if (PciDevice->DeviceState.RelaxedOrdering == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE || + PciDevice->DeviceState.RelaxedOrdering == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO) { + return EFI_SUCCESS; + } + + if (PciDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering != PciDevice->DeviceState.RelaxedOrdering) { + DEBUG (( + DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x\n", + __FUNCTION__, PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, + PciDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering, + PciDevice->DeviceState.RelaxedOrdering + )); + PciDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering = PciDevice->DeviceState.RelaxedOrdering; + + return PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl), + 1, + &PciDevice->PciExpressCapability.DeviceControl.Uint16 + ); + } + return EFI_SUCCESS; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h index 40e28b8..7d70f06 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h @@ -31,4 +31,11 @@ MaxReadRequestSizeProgram ( IN VOID **Context ); +EFI_STATUS +RelaxedOrderingProgram ( + IN PCI_IO_DEVICE *PciDevice, + IN UINTN Level, + IN VOID **Context + ); + #endif -- 2.21.0.windows.1