From: "Javeed, Ashraf" <ashraf.javeed@intel.com>
To: devel@edk2.groups.io
Cc: Ray Ni <ray.ni@intel.com>, Jian J Wang <jian.j.wang@intel.com>,
Hao A Wu <hao.a.wu@intel.com>
Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/15] MdeModulePkg/PciBusDxe: Enable CompletionTimeout feature
Date: Sun, 10 May 2020 21:44:08 +0530 [thread overview]
Message-ID: <20200510161412.13832-12-ashraf.javeed@intel.com> (raw)
In-Reply-To: <20200510161412.13832-1-ashraf.javeed@intel.com>
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase feature init routine for CompletionTimeout
PCIe feature.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Ashraf Javeed <ashraf.javeed@intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 15 +++++++++++++++
3 files changed, 109 insertions(+)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
index 6bf06b0..e6d3363 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
@@ -60,6 +60,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = {
TRUE, { TRUE, TRUE }, { NULL, RelaxedOrderingProgram } },
{ OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, NoSnoop),
TRUE, { TRUE, TRUE }, { NULL, NoSnoopProgram } },
+ { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, CompletionTimeout),
+ TRUE, { TRUE, TRUE }, { NULL, CompletionTimeoutProgram}},
};
/**
@@ -236,6 +238,7 @@ PcieNotifyDeviceState (
PcieDeviceState.MaxReadRequestSize = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize;
PcieDeviceState.RelaxedOrdering = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering;
PcieDeviceState.NoSnoop = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.NoSnoop;
+ PcieDeviceState.CompletionTimeout = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 & 0x1F;
return mPciePlatformProtocol->NotifyDeviceState (
mPciePlatformProtocol,
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
index 6c22feb..ca4052f 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
@@ -267,3 +267,94 @@ NoSnoopProgram (
return EFI_SUCCESS;
}
+/**
+ Program PCIe feature Completion Timeout per the device-specific platform policy.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+ @param Level The level of the PCI device in the heirarchy.
+ Level of root ports is 0.
+ @param Context Pointer to feature specific context.
+
+ @retval EFI_SUCCESS The feature is initialized successfully.
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
+ valid for the PCI configuration header of the PCI controller.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
+**/
+EFI_STATUS
+CompletionTimeoutProgram (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ )
+{
+ PCI_REG_PCIE_DEVICE_CONTROL2 DevicePolicy;
+ UINTN RangeIndex;
+ UINT8 SubRanges;
+
+ if (PciIoDevice->DeviceState.CompletionTimeout == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE ||
+ PciIoDevice->DeviceState.CompletionTimeout == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Interpret the policy value as BIT[0:4] in Device Control 2 Register
+ //
+ DevicePolicy.Uint16 = (UINT16) PciIoDevice->DeviceState.CompletionTimeout;
+
+ //
+ // Ignore when device doesn't support to disable Completion Timeout while the policy requests.
+ //
+ if (PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.CompletionTimeoutDisable == 0 &&
+ DevicePolicy.Bits.CompletionTimeoutDisable == 1) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (DevicePolicy.Bits.CompletionTimeoutValue != 0) {
+ //
+ // Ignore when the policy requests to use a range that's not supported by the device.
+ // RangeIndex is 0 ~ 3 for Range A ~ D.
+ //
+ RangeIndex = DevicePolicy.Bits.CompletionTimeoutValue >> 2;
+ if ((PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.CompletionTimeoutRanges & (1 < RangeIndex)) == 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Ignore when the policy doesn't request one and only one sub-range for a certain range.
+ //
+ SubRanges = (UINT8) (DevicePolicy.Bits.CompletionTimeoutValue & (BIT0 | BIT1));
+ if (SubRanges != BIT0 && SubRanges != BIT1) {
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+
+ if ((PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutDisable
+ != DevicePolicy.Bits.CompletionTimeoutDisable) ||
+ (PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutValue
+ != DevicePolicy.Bits.CompletionTimeoutValue)) {
+ DEBUG ((
+ DEBUG_INFO, " %a [%02d|%02d|%02d]: Disable = %x -> %x, Timeout = %x -> %x.\n",
+ __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber,
+ PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutDisable,
+ DevicePolicy.Bits.CompletionTimeoutDisable,
+ PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutValue,
+ DevicePolicy.Bits.CompletionTimeoutValue
+ ));
+ PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutDisable
+ = DevicePolicy.Bits.CompletionTimeoutDisable;
+ PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutValue
+ = DevicePolicy.Bits.CompletionTimeoutValue;
+
+ return PciIoDevice->PciIo.Pci.Write (
+ &PciIoDevice->PciIo,
+ EfiPciIoWidthUint16,
+ PciIoDevice->PciExpressCapabilityOffset
+ + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2),
+ 1,
+ &PciIoDevice->PciExpressCapability.DeviceControl2.Uint16
+ );
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
index 60b8742..bdb7004 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
@@ -45,4 +45,19 @@ NoSnoopProgram (
IN VOID **Context
);
+/**
+ Program PCIE feature Completion Timeout per the device-specific platform policy.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+
+ @retval EFI_SUCCESS The feature is initialized successfully.
+ @retval EFI_INVALID_PARAMETER The policy is not supported by the device.
+**/
+EFI_STATUS
+CompletionTimeoutProgram (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ );
+
#endif
--
2.21.0.windows.1
next prev parent reply other threads:[~2020-05-10 16:14 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200510161412.13832-1-ashraf.javeed@intel.com>
2020-05-10 16:13 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/15] MdePkg/Protocols: Deprecated the EFI encoded macros Javeed, Ashraf
2020-05-13 8:21 ` Ni, Ray
2020-05-10 16:13 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBusDxe: PciBusDxe Code refactor Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/15] MdeModulePkg/PciBus: Rename Cache PCIe Capability Structure Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/15] MdeModulePkg/PciBusDxe: Refactor the PCIe Bridge enable Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/15] MdeModulePkg/PciBusDxe: Locate PciePlatform/PcieOverride protocol Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/15] MdeModulePkg/PciBusDxe: Add the framework to init PCIe features Javeed, Ashraf
2020-05-13 6:39 ` Ni, Ray
2020-05-13 6:46 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/15] MdeModulePkg/PciBusDxe: Enable MaxPayloadSize feature Javeed, Ashraf
2020-05-13 6:45 ` Ni, Ray
2020-05-13 6:54 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/15] MdeModulePkg/PciBusDxe: Enable MaxReadRequestSize feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/15] MdeModulePkg/PciBusDxe: Enable RelaxedOrdering feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/15] MdeModulePkg/PciBusDxe: Enable NoSnoop feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` Javeed, Ashraf [this message]
2020-05-13 6:49 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/15] MdeModulePkg/PciBusDxe: Enable CompletionTimeout feature Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/15] MdeModulePkg/PciBusDxe: Enable LTR feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-13 7:10 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 13/15] MdeModulePkg/PciBusDxe: Enable AtomicOp feature Javeed, Ashraf
2020-05-13 6:51 ` [edk2-devel] " Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 14/15] MdeModulePkg/PciBusDxe: Enable ExtendedTag feature Javeed, Ashraf
2020-05-13 8:09 ` [edk2-devel] " Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 15/15] MdeModulePkg/PciBusDxe: Enable CommonClockConfiguration feature Javeed, Ashraf
2020-05-13 8:19 ` Ni, Ray
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