From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.17390.1589127269924431738 for ; Sun, 10 May 2020 09:14:46 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ashraf.javeed@intel.com) IronPort-SDR: cIuN+Pvlq4CZF4EUW3GDlwORHJVrEwMcucHK2paipNNl7ZEH20rcQBO3ZyMHsFH8ihAh+IAmL7 D6LVLG13Ettw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2020 09:14:46 -0700 IronPort-SDR: VqFopEYaWL/9e4TivJIjaHRHKM+7usfp55E2CBlPXO6cpn0CTE5wOF8apbNgIs9rjBJWGtjHPE AYM/6iPFV99Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,376,1583222400"; d="scan'208";a="463129694" Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.37]) by fmsmga006.fm.intel.com with ESMTP; 10 May 2020 09:14:44 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Ray Ni , Jian J Wang , Hao A Wu Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/15] MdeModulePkg/PciBusDxe: Enable CompletionTimeout feature Date: Sun, 10 May 2020 21:44:08 +0530 Message-Id: <20200510161412.13832-12-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200510161412.13832-1-ashraf.javeed@intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1954 https://bugzilla.tianocore.org/show_bug.cgi?id=2194 https://bugzilla.tianocore.org/show_bug.cgi?id=2313 https://bugzilla.tianocore.org/show_bug.cgi?id=2499 https://bugzilla.tianocore.org/show_bug.cgi?id=2500 Add the Program phase feature init routine for CompletionTimeout PCIe feature. Signed-off-by: Ashraf Javeed Signed-off-by: Ray Ni Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni Cc: Ashraf Javeed --- MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 15 +++++++++++++++ 3 files changed, 109 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c index 6bf06b0..e6d3363 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c @@ -60,6 +60,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = { TRUE, { TRUE, TRUE }, { NULL, RelaxedOrderingProgram } }, { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, NoSnoop), TRUE, { TRUE, TRUE }, { NULL, NoSnoopProgram } }, + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, CompletionTimeout), + TRUE, { TRUE, TRUE }, { NULL, CompletionTimeoutProgram}}, }; /** @@ -236,6 +238,7 @@ PcieNotifyDeviceState ( PcieDeviceState.MaxReadRequestSize = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize; PcieDeviceState.RelaxedOrdering = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering; PcieDeviceState.NoSnoop = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.NoSnoop; + PcieDeviceState.CompletionTimeout = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 & 0x1F; return mPciePlatformProtocol->NotifyDeviceState ( mPciePlatformProtocol, diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c index 6c22feb..ca4052f 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c @@ -267,3 +267,94 @@ NoSnoopProgram ( return EFI_SUCCESS; } +/** + Program PCIe feature Completion Timeout per the device-specific platform policy. + + @param PciIoDevice A pointer to the PCI_IO_DEVICE. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. + + @retval EFI_SUCCESS The feature is initialized successfully. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI configuration header of the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. +**/ +EFI_STATUS +CompletionTimeoutProgram ( + IN PCI_IO_DEVICE *PciIoDevice, + IN UINTN Level, + IN VOID **Context + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL2 DevicePolicy; + UINTN RangeIndex; + UINT8 SubRanges; + + if (PciIoDevice->DeviceState.CompletionTimeout == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE || + PciIoDevice->DeviceState.CompletionTimeout == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO) { + return EFI_SUCCESS; + } + + // + // Interpret the policy value as BIT[0:4] in Device Control 2 Register + // + DevicePolicy.Uint16 = (UINT16) PciIoDevice->DeviceState.CompletionTimeout; + + // + // Ignore when device doesn't support to disable Completion Timeout while the policy requests. + // + if (PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.CompletionTimeoutDisable == 0 && + DevicePolicy.Bits.CompletionTimeoutDisable == 1) { + return EFI_INVALID_PARAMETER; + } + + if (DevicePolicy.Bits.CompletionTimeoutValue != 0) { + // + // Ignore when the policy requests to use a range that's not supported by the device. + // RangeIndex is 0 ~ 3 for Range A ~ D. + // + RangeIndex = DevicePolicy.Bits.CompletionTimeoutValue >> 2; + if ((PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.CompletionTimeoutRanges & (1 < RangeIndex)) == 0) { + return EFI_INVALID_PARAMETER; + } + + // + // Ignore when the policy doesn't request one and only one sub-range for a certain range. + // + SubRanges = (UINT8) (DevicePolicy.Bits.CompletionTimeoutValue & (BIT0 | BIT1)); + if (SubRanges != BIT0 && SubRanges != BIT1) { + return EFI_INVALID_PARAMETER; + } + } + + if ((PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutDisable + != DevicePolicy.Bits.CompletionTimeoutDisable) || + (PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutValue + != DevicePolicy.Bits.CompletionTimeoutValue)) { + DEBUG (( + DEBUG_INFO, " %a [%02d|%02d|%02d]: Disable = %x -> %x, Timeout = %x -> %x.\n", + __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutDisable, + DevicePolicy.Bits.CompletionTimeoutDisable, + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutValue, + DevicePolicy.Bits.CompletionTimeoutValue + )); + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutDisable + = DevicePolicy.Bits.CompletionTimeoutDisable; + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTimeoutValue + = DevicePolicy.Bits.CompletionTimeoutValue; + + return PciIoDevice->PciIo.Pci.Write ( + &PciIoDevice->PciIo, + EfiPciIoWidthUint16, + PciIoDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2), + 1, + &PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 + ); + } + + return EFI_SUCCESS; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h index 60b8742..bdb7004 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h @@ -45,4 +45,19 @@ NoSnoopProgram ( IN VOID **Context ); +/** + Program PCIE feature Completion Timeout per the device-specific platform policy. + + @param PciIoDevice A pointer to the PCI_IO_DEVICE. + + @retval EFI_SUCCESS The feature is initialized successfully. + @retval EFI_INVALID_PARAMETER The policy is not supported by the device. +**/ +EFI_STATUS +CompletionTimeoutProgram ( + IN PCI_IO_DEVICE *PciIoDevice, + IN UINTN Level, + IN VOID **Context + ); + #endif -- 2.21.0.windows.1