From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.17390.1589127269924431738 for ; Sun, 10 May 2020 09:14:50 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ashraf.javeed@intel.com) IronPort-SDR: v2S5LEcGhvtJDqR1VLVBDpCC+n7mJQ4yKRDoMepEI296V9hC3lMRpeMWj1U5A+hAzPO4nrRe81 O6vFY+D/9sOw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2020 09:14:50 -0700 IronPort-SDR: tDs0RzbB9ueaLebvgfwmyOyvSMrbWbP9KfCrgB8ifKkG7nsyFlRIm8wHqB1GOGE+m26DafxznR 3XyrDXV9q83g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,376,1583222400"; d="scan'208";a="463129717" Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.37]) by fmsmga006.fm.intel.com with ESMTP; 10 May 2020 09:14:48 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Ray Ni , Jian J Wang , Hao A Wu Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 13/15] MdeModulePkg/PciBusDxe: Enable AtomicOp feature Date: Sun, 10 May 2020 21:44:10 +0530 Message-Id: <20200510161412.13832-14-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200510161412.13832-1-ashraf.javeed@intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1954 https://bugzilla.tianocore.org/show_bug.cgi?id=2194 https://bugzilla.tianocore.org/show_bug.cgi?id=2313 https://bugzilla.tianocore.org/show_bug.cgi?id=2499 https://bugzilla.tianocore.org/show_bug.cgi?id=2500 Add the Program phase feature init routine for AtomicOp PCIe feature. Signed-off-by: Ashraf Javeed Signed-off-by: Ray Ni Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni Cc: Ashraf Javeed --- MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 16 ++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c index 35aaffa..401521b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c @@ -64,6 +64,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = { TRUE, { TRUE, TRUE }, { NULL, CompletionTimeoutProgram}}, { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, Ltr), TRUE, { FALSE, TRUE }, { LtrScan, LtrProgram}}, + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, AtomicOp), + TRUE, { TRUE, TRUE }, { NULL, AtomicOpProgram}}, }; /** @@ -241,6 +243,7 @@ PcieNotifyDeviceState ( PcieDeviceState.RelaxedOrdering = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.RelaxedOrdering; PcieDeviceState.NoSnoop = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.NoSnoop; PcieDeviceState.CompletionTimeout = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 & 0x1F; + PcieDeviceState.AtomicOp = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Bits.AtomicOpRequester; PcieDeviceState.Ltr = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Bits.LtrMechanism; return mPciePlatformProtocol->NotifyDeviceState ( diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c index 8c7fae0..407c94a 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c @@ -552,3 +552,65 @@ LtrProgram ( return EFI_SUCCESS; } +/** + Program AtomicOp. + + @param PciIoDevice A pointer to the PCI_IO_DEVICE. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. + + @retval EFI_SUCCESS setup of PCI feature AtomicOp is successful. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI configuration header of the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. +**/ +EFI_STATUS +AtomicOpProgram ( + IN PCI_IO_DEVICE *PciIoDevice, + IN UINTN Level, + IN VOID **Context + ) +{ + if (PciIoDevice->DeviceState.AtomicOp == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO || + PciIoDevice->DeviceState.AtomicOp == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE) { + return EFI_SUCCESS; + } + + // + // BIT0 of the policy value is for AtomicOp Requester Enable (BIT6) + // BIT1 of the policy value is for AtomicOp Egress Blocking (BIT7) + // + if ((PciIoDevice->DeviceState.AtomicOp >> 2) != 0) { + return EFI_INVALID_PARAMETER; + } + + if (!PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.AtomicOpRouting) { + PciIoDevice->DeviceState.AtomicOp &= ~BIT1; + } + if (PciIoDevice->DeviceState.AtomicOp != + BitFieldRead16 (PciIoDevice->PciExpressCapability.DeviceControl2.Uint16, 6, 7)) { + + DEBUG (( + DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x.\n", + __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, + BitFieldRead16 (PciIoDevice->PciExpressCapability.DeviceControl2.Uint16, 6, 7), + PciIoDevice->DeviceState.AtomicOp + )); + BitFieldWrite16 ( + PciIoDevice->PciExpressCapability.DeviceControl2.Uint16, 6, 7, + PciIoDevice->DeviceState.AtomicOp + ); + return PciIoDevice->PciIo.Pci.Write ( + &PciIoDevice->PciIo, + EfiPciIoWidthUint16, + PciIoDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2), + 1, + &PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 + ); + } + + return EFI_SUCCESS; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h index a9dacf3..5c70e41 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h @@ -94,4 +94,20 @@ LtrProgram ( IN VOID **Context ); +/** + Program AtomicOp. + + @param PciIoDevice A pointer to the PCI_IO_DEVICE. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. + + @retval EFI_SUCCESS setup of PCI feature LTR is successful. +**/ +EFI_STATUS +AtomicOpProgram ( + IN PCI_IO_DEVICE *PciIoDevice, + IN UINTN Level, + IN VOID **Context + ); #endif -- 2.21.0.windows.1