From: "Javeed, Ashraf" <ashraf.javeed@intel.com>
To: devel@edk2.groups.io
Cc: Jian J Wang <jian.j.wang@intel.com>,
Hao A Wu <hao.a.wu@intel.com>, Ray Ni <ray.ni@intel.com>
Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 14/15] MdeModulePkg/PciBusDxe: Enable ExtendedTag feature
Date: Sun, 10 May 2020 21:44:11 +0530 [thread overview]
Message-ID: <20200510161412.13832-15-ashraf.javeed@intel.com> (raw)
In-Reply-To: <20200510161412.13832-1-ashraf.javeed@intel.com>
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase feature init routine for ExtendedTag
PCIe feature.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Ashraf Javeed <ashraf.javeed@intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 5 +++++
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 179 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 18 ++++++++++++++++++
3 files changed, 202 insertions(+)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
index 401521b..acd60d5 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
@@ -66,6 +66,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = {
TRUE, { FALSE, TRUE }, { LtrScan, LtrProgram}},
{ OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, AtomicOp),
TRUE, { TRUE, TRUE }, { NULL, AtomicOpProgram}},
+ { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, ExtendedTag),
+ TRUE, { TRUE, TRUE }, { NULL, ExtendedTagProgram } }
};
/**
@@ -245,6 +247,9 @@ PcieNotifyDeviceState (
PcieDeviceState.CompletionTimeout = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 & 0x1F;
PcieDeviceState.AtomicOp = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Bits.AtomicOpRequester;
PcieDeviceState.Ltr = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Bits.LtrMechanism;
+ PcieDeviceState.ExtendedTag =
+ (UINT8)((PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable << 1)
+ | PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField);
return mPciePlatformProtocol->NotifyDeviceState (
mPciePlatformProtocol,
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
index 407c94a..095f2ec 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
@@ -614,3 +614,182 @@ AtomicOpProgram (
return EFI_SUCCESS;
}
+/**
+ Record the parent Root Port 10b Extended Tag Completer capability.
+
+ @param PciDevice A pointer to the PCI_IO_DEVICE.
+ @param Level The level of the PCI device in the heirarchy.
+ Level of root ports is 0.
+ @param Context Pointer to feature specific context.
+**/
+STATIC
+VOID
+ExtendedTagCheck (
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ )
+{
+ BOOLEAN *TenBitCompleterCapable;
+
+ DEBUG ((
+ DEBUG_INFO, " %a [%02d|%02d|%02d]: Capability = %x",
+ __FUNCTION__, PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber,
+ PciDevice->PciExpressCapability.DeviceCapability.Bits.ExtendedTagField
+ ));
+ DEBUG ((
+ DEBUG_INFO, " Capability2 = [%x, %x]\n",
+ PciDevice->PciExpressCapability.DeviceCapability2.Bits.TenBitTagRequesterSupported,
+ PciDevice->PciExpressCapability.DeviceCapability2.Bits.TenBitTagCompleterSupported
+ ));
+
+ TenBitCompleterCapable = *Context;
+ if (TenBitCompleterCapable == NULL) {
+ TenBitCompleterCapable = AllocatePool (sizeof (*TenBitCompleterCapable));
+ *Context = TenBitCompleterCapable;
+ }
+ if (Level == 1) {
+ *TenBitCompleterCapable = (BOOLEAN)
+ (PciDevice->PciExpressCapability.DeviceCapability2.Bits.TenBitTagCompleterSupported);
+ }
+}
+
+/**
+ Program PCIe feature ExtendedTag.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+ @param Level The level of the PCI device in the heirarchy.
+ Level of root ports is 0.
+ @param Context Pointer to feature specific context.
+
+ @retval EFI_SUCCESS setup of PCI feature ExtendedTag is successful.
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
+ valid for the PCI configuration header of the PCI controller.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
+**/
+EFI_STATUS
+ExtendedTagProgram (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ )
+{
+ BOOLEAN *TenBitCompleterCapable;
+ PCI_REG_PCIE_DEVICE_CONTROL2 DeviceCtl2;
+ PCI_REG_PCIE_DEVICE_CONTROL DeviceCtl;
+ EFI_STATUS Status;
+
+ if (PciIoDevice->DeviceState.ExtendedTag == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO ||
+ PciIoDevice->DeviceState.ExtendedTag == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // BIT0 of the policy value is for 5b or 8b Extended Tag (DeviceControl BIT8)
+ // BIT1 of the policy value is for 10b Extended Tag (DeviceControl2 BIT12)
+ //
+ if ((PciIoDevice->DeviceState.ExtendedTag >> 2) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // check and prepare the context for the Extended Tag Completer capability
+ //
+ ExtendedTagCheck (PciIoDevice, Level, Context);
+
+ //
+ // start with no change to device 10b Requester Enable state
+ //
+ DeviceCtl2.Bits.TenBitTagRequesterEnable = 0;
+
+ //
+ // the device should be capable of 10b Extended Tag Requester
+ //
+ if ((PciIoDevice->DeviceState.ExtendedTag & BIT1) &&
+ (PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.TenBitTagRequesterSupported)) {
+ //
+ // for the Endpoint device 10b Extended Tag Requester Enable, the RC should be
+ // 10b Completer capable
+ //
+ if (PciIoDevice->PciExpressCapability.Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT ||
+ PciIoDevice->PciExpressCapability.Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT) {
+ //
+ // check the parent Root Port 10b Extended Tag Completer Capability
+ //
+ TenBitCompleterCapable = *Context;
+ if (*TenBitCompleterCapable == TRUE) {
+ //
+ // since the RC is 10b COmpleter capable, enable the EP as 10b Requester
+ //
+ DeviceCtl2.Bits.TenBitTagRequesterEnable = 1;
+ }
+ } else {
+ //
+ // enable the device as 10b Requester if it is capable and per platform ask
+ //
+ DeviceCtl2.Bits.TenBitTagRequesterEnable = 1;
+ }
+ //
+ // write DeviceControl2 register for 10b Extended Tag Requester state
+ //
+ if (DeviceCtl2.Bits.TenBitTagRequesterEnable !=
+ PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable) {
+
+ DEBUG ((
+ DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x.\n",
+ __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber,
+ PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable,
+ DeviceCtl2.Bits.TenBitTagRequesterEnable
+ ));
+ PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable =
+ DeviceCtl2.Bits.TenBitTagRequesterEnable;
+
+ Status = PciIoDevice->PciIo.Pci.Write (
+ &PciIoDevice->PciIo,
+ EfiPciIoWidthUint16,
+ PciIoDevice->PciExpressCapabilityOffset
+ + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2),
+ 1,
+ &PciIoDevice->PciExpressCapability.DeviceControl2.Uint16
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+ }
+
+ //
+ // if no 10b Extended Tag Requester for this device than consider 8b or 5b Extended Requester
+ //
+ if (!DeviceCtl2.Bits.TenBitTagRequesterEnable) {
+ //
+ // the device should be capable of 8b Extended Tag Requester
+ //
+ DeviceCtl.Bits.ExtendedTagField = (UINT16)
+ ((PciIoDevice->DeviceState.ExtendedTag & BIT0) &&
+ (PciIoDevice->PciExpressCapability.DeviceCapability.Bits.ExtendedTagField));
+
+ if (DeviceCtl.Bits.ExtendedTagField !=
+ PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField) {
+ DEBUG ((
+ DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x.\n",
+ __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber,
+ PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField,
+ DeviceCtl.Bits.ExtendedTagField
+ ));
+ PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField = DeviceCtl.Bits.ExtendedTagField;
+
+ return PciIoDevice->PciIo.Pci.Write (
+ &PciIoDevice->PciIo,
+ EfiPciIoWidthUint16,
+ PciIoDevice->PciExpressCapabilityOffset
+ + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl),
+ 1,
+ &PciIoDevice->PciExpressCapability.DeviceControl.Uint16
+ );
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
index 5c70e41..2699f70 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
@@ -110,4 +110,22 @@ AtomicOpProgram (
IN UINTN Level,
IN VOID **Context
);
+
+/**
+ Program ExtendedTag.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+ @param Level The level of the PCI device in the heirarchy.
+ Level of root ports is 0.
+ @param Context Pointer to feature specific context.
+
+ @retval EFI_SUCCESS setup of PCI feature ExtendedTag is successful.
+**/
+EFI_STATUS
+ExtendedTagProgram (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Level,
+ IN VOID **Context
+ );
+
#endif
--
2.21.0.windows.1
next prev parent reply other threads:[~2020-05-10 16:14 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200510161412.13832-1-ashraf.javeed@intel.com>
2020-05-10 16:13 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/15] MdePkg/Protocols: Deprecated the EFI encoded macros Javeed, Ashraf
2020-05-13 8:21 ` Ni, Ray
2020-05-10 16:13 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBusDxe: PciBusDxe Code refactor Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/15] MdeModulePkg/PciBus: Rename Cache PCIe Capability Structure Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/15] MdeModulePkg/PciBusDxe: Refactor the PCIe Bridge enable Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/15] MdeModulePkg/PciBusDxe: Locate PciePlatform/PcieOverride protocol Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/15] MdeModulePkg/PciBusDxe: Add the framework to init PCIe features Javeed, Ashraf
2020-05-13 6:39 ` Ni, Ray
2020-05-13 6:46 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/15] MdeModulePkg/PciBusDxe: Enable MaxPayloadSize feature Javeed, Ashraf
2020-05-13 6:45 ` Ni, Ray
2020-05-13 6:54 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/15] MdeModulePkg/PciBusDxe: Enable MaxReadRequestSize feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/15] MdeModulePkg/PciBusDxe: Enable RelaxedOrdering feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/15] MdeModulePkg/PciBusDxe: Enable NoSnoop feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/15] MdeModulePkg/PciBusDxe: Enable CompletionTimeout feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/15] MdeModulePkg/PciBusDxe: Enable LTR feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-13 7:10 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 13/15] MdeModulePkg/PciBusDxe: Enable AtomicOp feature Javeed, Ashraf
2020-05-13 6:51 ` [edk2-devel] " Ni, Ray
2020-05-10 16:14 ` Javeed, Ashraf [this message]
2020-05-13 8:09 ` [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 14/15] MdeModulePkg/PciBusDxe: Enable ExtendedTag feature Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 15/15] MdeModulePkg/PciBusDxe: Enable CommonClockConfiguration feature Javeed, Ashraf
2020-05-13 8:19 ` Ni, Ray
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