From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.17390.1589127269924431738 for ; Sun, 10 May 2020 09:14:52 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ashraf.javeed@intel.com) IronPort-SDR: tO/4wazpTZVnQnNNJYsBgR1uCrujGEIrzuEnN+QmVnF7Mmx2FxiFcLpcBw24qUF8Yvq3qOEXiv MyWLab57hoQw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2020 09:14:52 -0700 IronPort-SDR: ZmP4v0JrMtkaC+QGzV+xAMi42jB5PYJetx59XmRraBnsA6mW9k8K3xslYWGga8iCprRIlVKYF2 wySVuSasuVzA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,376,1583222400"; d="scan'208";a="463129726" Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.37]) by fmsmga006.fm.intel.com with ESMTP; 10 May 2020 09:14:50 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 14/15] MdeModulePkg/PciBusDxe: Enable ExtendedTag feature Date: Sun, 10 May 2020 21:44:11 +0530 Message-Id: <20200510161412.13832-15-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200510161412.13832-1-ashraf.javeed@intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1954 https://bugzilla.tianocore.org/show_bug.cgi?id=2194 https://bugzilla.tianocore.org/show_bug.cgi?id=2313 https://bugzilla.tianocore.org/show_bug.cgi?id=2499 https://bugzilla.tianocore.org/show_bug.cgi?id=2500 Add the Program phase feature init routine for ExtendedTag PCIe feature. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni Cc: Ashraf Javeed --- MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 5 +++++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 179 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 18 ++++++++++++++++++ 3 files changed, 202 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c index 401521b..acd60d5 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c @@ -66,6 +66,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] = { TRUE, { FALSE, TRUE }, { LtrScan, LtrProgram}}, { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, AtomicOp), TRUE, { TRUE, TRUE }, { NULL, AtomicOpProgram}}, + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, ExtendedTag), + TRUE, { TRUE, TRUE }, { NULL, ExtendedTagProgram } } }; /** @@ -245,6 +247,9 @@ PcieNotifyDeviceState ( PcieDeviceState.CompletionTimeout = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 & 0x1F; PcieDeviceState.AtomicOp = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Bits.AtomicOpRequester; PcieDeviceState.Ltr = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl2.Bits.LtrMechanism; + PcieDeviceState.ExtendedTag = + (UINT8)((PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable << 1) + | PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField); return mPciePlatformProtocol->NotifyDeviceState ( mPciePlatformProtocol, diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c index 407c94a..095f2ec 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c @@ -614,3 +614,182 @@ AtomicOpProgram ( return EFI_SUCCESS; } +/** + Record the parent Root Port 10b Extended Tag Completer capability. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. +**/ +STATIC +VOID +ExtendedTagCheck ( + IN PCI_IO_DEVICE *PciDevice, + IN UINTN Level, + IN VOID **Context + ) +{ + BOOLEAN *TenBitCompleterCapable; + + DEBUG (( + DEBUG_INFO, " %a [%02d|%02d|%02d]: Capability = %x", + __FUNCTION__, PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, + PciDevice->PciExpressCapability.DeviceCapability.Bits.ExtendedTagField + )); + DEBUG (( + DEBUG_INFO, " Capability2 = [%x, %x]\n", + PciDevice->PciExpressCapability.DeviceCapability2.Bits.TenBitTagRequesterSupported, + PciDevice->PciExpressCapability.DeviceCapability2.Bits.TenBitTagCompleterSupported + )); + + TenBitCompleterCapable = *Context; + if (TenBitCompleterCapable == NULL) { + TenBitCompleterCapable = AllocatePool (sizeof (*TenBitCompleterCapable)); + *Context = TenBitCompleterCapable; + } + if (Level == 1) { + *TenBitCompleterCapable = (BOOLEAN) + (PciDevice->PciExpressCapability.DeviceCapability2.Bits.TenBitTagCompleterSupported); + } +} + +/** + Program PCIe feature ExtendedTag. + + @param PciIoDevice A pointer to the PCI_IO_DEVICE. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. + + @retval EFI_SUCCESS setup of PCI feature ExtendedTag is successful. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI configuration header of the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. +**/ +EFI_STATUS +ExtendedTagProgram ( + IN PCI_IO_DEVICE *PciIoDevice, + IN UINTN Level, + IN VOID **Context + ) +{ + BOOLEAN *TenBitCompleterCapable; + PCI_REG_PCIE_DEVICE_CONTROL2 DeviceCtl2; + PCI_REG_PCIE_DEVICE_CONTROL DeviceCtl; + EFI_STATUS Status; + + if (PciIoDevice->DeviceState.ExtendedTag == EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO || + PciIoDevice->DeviceState.ExtendedTag == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE) { + return EFI_SUCCESS; + } + + // + // BIT0 of the policy value is for 5b or 8b Extended Tag (DeviceControl BIT8) + // BIT1 of the policy value is for 10b Extended Tag (DeviceControl2 BIT12) + // + if ((PciIoDevice->DeviceState.ExtendedTag >> 2) != 0) { + return EFI_INVALID_PARAMETER; + } + + // + // check and prepare the context for the Extended Tag Completer capability + // + ExtendedTagCheck (PciIoDevice, Level, Context); + + // + // start with no change to device 10b Requester Enable state + // + DeviceCtl2.Bits.TenBitTagRequesterEnable = 0; + + // + // the device should be capable of 10b Extended Tag Requester + // + if ((PciIoDevice->DeviceState.ExtendedTag & BIT1) && + (PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.TenBitTagRequesterSupported)) { + // + // for the Endpoint device 10b Extended Tag Requester Enable, the RC should be + // 10b Completer capable + // + if (PciIoDevice->PciExpressCapability.Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT || + PciIoDevice->PciExpressCapability.Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT) { + // + // check the parent Root Port 10b Extended Tag Completer Capability + // + TenBitCompleterCapable = *Context; + if (*TenBitCompleterCapable == TRUE) { + // + // since the RC is 10b COmpleter capable, enable the EP as 10b Requester + // + DeviceCtl2.Bits.TenBitTagRequesterEnable = 1; + } + } else { + // + // enable the device as 10b Requester if it is capable and per platform ask + // + DeviceCtl2.Bits.TenBitTagRequesterEnable = 1; + } + // + // write DeviceControl2 register for 10b Extended Tag Requester state + // + if (DeviceCtl2.Bits.TenBitTagRequesterEnable != + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable) { + + DEBUG (( + DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x.\n", + __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable, + DeviceCtl2.Bits.TenBitTagRequesterEnable + )); + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable = + DeviceCtl2.Bits.TenBitTagRequesterEnable; + + Status = PciIoDevice->PciIo.Pci.Write ( + &PciIoDevice->PciIo, + EfiPciIoWidthUint16, + PciIoDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2), + 1, + &PciIoDevice->PciExpressCapability.DeviceControl2.Uint16 + ); + if (EFI_ERROR(Status)) { + return Status; + } + } + } + + // + // if no 10b Extended Tag Requester for this device than consider 8b or 5b Extended Requester + // + if (!DeviceCtl2.Bits.TenBitTagRequesterEnable) { + // + // the device should be capable of 8b Extended Tag Requester + // + DeviceCtl.Bits.ExtendedTagField = (UINT16) + ((PciIoDevice->DeviceState.ExtendedTag & BIT0) && + (PciIoDevice->PciExpressCapability.DeviceCapability.Bits.ExtendedTagField)); + + if (DeviceCtl.Bits.ExtendedTagField != + PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField) { + DEBUG (( + DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x.\n", + __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, + PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField, + DeviceCtl.Bits.ExtendedTagField + )); + PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField = DeviceCtl.Bits.ExtendedTagField; + + return PciIoDevice->PciIo.Pci.Write ( + &PciIoDevice->PciIo, + EfiPciIoWidthUint16, + PciIoDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl), + 1, + &PciIoDevice->PciExpressCapability.DeviceControl.Uint16 + ); + } + } + + return EFI_SUCCESS; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h index 5c70e41..2699f70 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h @@ -110,4 +110,22 @@ AtomicOpProgram ( IN UINTN Level, IN VOID **Context ); + +/** + Program ExtendedTag. + + @param PciIoDevice A pointer to the PCI_IO_DEVICE. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. + + @retval EFI_SUCCESS setup of PCI feature ExtendedTag is successful. +**/ +EFI_STATUS +ExtendedTagProgram ( + IN PCI_IO_DEVICE *PciIoDevice, + IN UINTN Level, + IN VOID **Context + ); + #endif -- 2.21.0.windows.1