[edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 15/15] MdeModulePkg/PciBusDxe: Enable CommonClockConfiguration feature

["Javeed, Ashraf" <ashraf.javeed@intel.com>]

REF:
  https://bugzilla.tianocore.org/show_bug.cgi?id=1954
  https://bugzilla.tianocore.org/show_bug.cgi?id=2194
  https://bugzilla.tianocore.org/show_bug.cgi?id=2313
  https://bugzilla.tianocore.org/show_bug.cgi?id=2499
  https://bugzilla.tianocore.org/show_bug.cgi?id=2500

Add the Program phase feature init routine for CommonClockConfiguration
PCIe feature.

Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Ashraf Javeed <ashraf.javeed@intel.com>
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c |  4 ++++
 MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c       | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h       | 17 +++++++++++++++++
 3 files changed, 119 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
index acd60d5..c4bba0e 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c
@@ -52,6 +52,8 @@ PCIE_FEATURE_ENTRY  mPcieFeatures[] = {
   //
   // Individual PCIE features
   //
+  { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, CommonClockConfiguration),
+              TRUE, { TRUE,  FALSE },{ NULL,                    CommonClockConfigurationProgram } },
   { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxPayloadSize),
               TRUE, { TRUE,  TRUE }, { MaxPayloadSizeScan,      MaxPayloadSizeProgram } },
   { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxReadRequestSize),
@@ -250,6 +252,8 @@ PcieNotifyDeviceState (
   PcieDeviceState.ExtendedTag         =
                   (UINT8)((PciIoDevice->PciExpressCapability.DeviceControl2.Bits.TenBitTagRequesterEnable << 1)
                            | PciIoDevice->PciExpressCapability.DeviceControl.Bits.ExtendedTagField);
+  PcieDeviceState.CommonClockConfiguration = (UINT8)
+                                        PciIoDevice->PciExpressCapability.LinkControl.Bits.CommonClockConfiguration;
 
   return mPciePlatformProtocol->NotifyDeviceState (
                                   mPciePlatformProtocol,
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
index 095f2ec..063a6be 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c
@@ -793,3 +793,101 @@ ExtendedTagProgram (
   return EFI_SUCCESS;
 }
 
+/**
+  Program PCIe feature CommonClockConfiguration.
+
+  @param PciIoDevice            A pointer to the PCI_IO_DEVICE.
+  @param Level                  The level of the PCI device in the heirarchy.
+                                Level of root ports is 0.
+  @param Context                Pointer to feature specific context.
+
+  @retval EFI_SUCCESS           setup of PCI feature CommonClockConfiguration is successful.
+  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
+                                valid for the PCI configuration header of the PCI controller.
+  @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
+**/
+EFI_STATUS
+CommonClockConfigurationProgram (
+  IN  PCI_IO_DEVICE *PciIoDevice,
+  IN  UINTN         Level,
+  IN  VOID          **Context
+  )
+{
+  EFI_STATUS                    Status;
+
+  //
+  // no other options about the Common Clock Configuraton shall be accepted besides
+  // AUTO and NOT_APPLICABLE
+  //
+  if (PciIoDevice->DeviceState.CommonClockConfiguration != EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO &&
+      PciIoDevice->DeviceState.CommonClockConfiguration != EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE) {
+    return EFI_INVALID_PARAMETER;
+  }
+  //
+  // skip programming of the Common Clock COnfiguration in the Link Cnntrol register
+  //
+  if (PciIoDevice->DeviceState.CommonClockConfiguration == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE) {
+    return EFI_SUCCESS;
+  }
+
+  DEBUG ((
+    DEBUG_INFO, "  %a [%02d|%02d|%02d]: Status = %x\n",
+    __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber,
+    PciIoDevice->PciExpressCapability.LinkStatus.Bits.SlotClockConfiguration
+    ));
+
+  //
+  // the Common Clock Configuration of the device needs to be aligned with its
+  // Link Status register SlotClockConfiguration value
+  //
+  if (PciIoDevice->PciExpressCapability.LinkStatus.Bits.SlotClockConfiguration !=
+      PciIoDevice->PciExpressCapability.LinkControl.Bits.CommonClockConfiguration) {
+    DEBUG ((
+      DEBUG_INFO, "  %a [%02d|%02d|%02d]: %x -> %x.\n",
+      __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber,
+      PciIoDevice->PciExpressCapability.LinkControl.Bits.CommonClockConfiguration,
+      PciIoDevice->PciExpressCapability.LinkStatus.Bits.SlotClockConfiguration
+      ));
+    PciIoDevice->PciExpressCapability.LinkControl.Bits.CommonClockConfiguration =
+        PciIoDevice->PciExpressCapability.LinkStatus.Bits.SlotClockConfiguration;
+    //
+    // retrain the link at Root Port level, if its link is active
+    //
+    if (Level == 1 && PciIoDevice->PciExpressCapability.LinkStatus.Bits.DataLinkLayerLinkActive) {
+      PciIoDevice->PciExpressCapability.LinkControl.Bits.RetrainLink = 1;
+    }
+
+    Status = PciIoDevice->PciIo.Pci.Write (
+                                    &PciIoDevice->PciIo,
+                                    EfiPciIoWidthUint16,
+                                    PciIoDevice->PciExpressCapabilityOffset
+                                    + OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl),
+                                    1,
+                                    &PciIoDevice->PciExpressCapability.LinkControl.Uint16
+                                    );
+    if (EFI_ERROR(Status)) {
+      return Status;
+    }
+    //
+    // wait till link retrain is complete
+    //
+    if (Level == 1 && PciIoDevice->PciExpressCapability.LinkStatus.Bits.DataLinkLayerLinkActive) {
+      do {
+        Status = PciIoDevice->PciIo.Pci.Read (
+                                        &PciIoDevice->PciIo,
+                                        EfiPciIoWidthUint16,
+                                        PciIoDevice->PciExpressCapabilityOffset
+                                        + OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkStatus),
+                                        1,
+                                        &PciIoDevice->PciExpressCapability.LinkStatus.Uint16
+                                        );
+        if (EFI_ERROR(Status)) {
+          return Status;
+        }
+      } while (PciIoDevice->PciExpressCapability.LinkStatus.Bits.LinkTraining);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
index 2699f70..f1c4cb7 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h
@@ -128,4 +128,21 @@ ExtendedTagProgram (
   IN  VOID          **Context
   );
 
+/**
+  Program CommonClockConfiguration.
+
+  @param PciIoDevice  A pointer to the PCI_IO_DEVICE.
+  @param Level        The level of the PCI device in the heirarchy.
+                      Level of root ports is 0.
+  @param Context      Pointer to feature specific context.
+
+  @retval EFI_SUCCESS setup of PCI feature ExtendedTag is successful.
+**/
+EFI_STATUS
+CommonClockConfigurationProgram (
+  IN  PCI_IO_DEVICE *PciIoDevice,
+  IN  UINTN         Level,
+  IN  VOID          **Context
+  );
+
 #endif
-- 
2.21.0.windows.1