From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web12.17390.1589127269924431738 for ; Sun, 10 May 2020 09:14:30 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: ashraf.javeed@intel.com) IronPort-SDR: Ni/b/EAxrWeFP1/kKy6KCh6KOquU44VpASwMZGH5gkEst6lVF1tYssOa8lTyGCaHW+PLL6A6wo aCEzXoWgptvA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2020 09:14:29 -0700 IronPort-SDR: VM2oeSWV/Q1GHBqeLXWHmGcAq51KoZX2JLTb26S/HjtKwlvf2nzNAS4jyBR5VwEOj3EDb5xg/x aGYRk0rIN7Fw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,376,1583222400"; d="scan'208";a="463129613" Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.37]) by fmsmga006.fm.intel.com with ESMTP; 10 May 2020 09:14:24 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBusDxe: PciBusDxe Code refactor Date: Sun, 10 May 2020 21:43:59 +0530 Message-Id: <20200510161412.13832-3-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200510161412.13832-1-ashraf.javeed@intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable References:- https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 https://bugzilla.tianocore.org/show_bug.cgi?id=3D2499 https://bugzilla.tianocore.org/show_bug.cgi?id=3D2500 This code change represents the code refactoring by expelling the previous changes of the PCIe features. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 4 -- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 20 ++------- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 10 +---- MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 11 +---- MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 2178 ---------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------ MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 399 ---------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ------- MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 1019 ---------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------------------------- MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 304 ---------------= ---------------------------------------------------------------------------= ----------------------------------------- MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 902 ---------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= -------------------------------------------------------------------------- MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 119 ---------------= ------------------------------------- 10 files changed, 6 insertions(+), 4960 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.c index 714101c..53e6dfa 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c @@ -284,10 +284,6 @@ PciBusDriverBindingStart ( (VOID **) &gPciOverrideProtocol=0D );=0D }=0D - //=0D - // get the PCI Express Protocol or the PCI Express Override Protocol=0D - //=0D - GetPciExpressProtocol ();=0D =0D if (mIoMmuProtocol =3D=3D NULL) {=0D gBS->LocateProtocol (=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 34f482d..5a7c1c2 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -27,6 +27,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D +#include =0D =0D #include =0D #include =0D @@ -42,8 +44,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D -#include =0D -#include =0D +=0D =0D typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;=0D typedef struct _PCI_BAR PCI_BAR;=0D @@ -81,8 +82,6 @@ typedef enum { #include "PciPowerManagement.h"=0D #include "PciHotPlugSupport.h"=0D #include "PciLib.h"=0D -#include "PciPlatformSupport.h"=0D -#include "PciFeatureSupport.h"=0D =0D #define VGABASE1 0x3B0=0D #define VGALIMIT1 0x3BB=0D @@ -287,19 +286,6 @@ struct _PCI_IO_DEVICE { // This field is used to support this case.=0D //=0D UINT16 BridgeIoAlignment;=0D - //=0D - // PCI Express features setup flags=0D - //=0D - UINT8 SetupMPS;=0D - UINT8 SetupMRRS;=0D - PCI_FEATURE_POLICY SetupRO;=0D - PCI_FEATURE_POLICY SetupNS;=0D - PCI_FEATURE_POLICY SetupCTO;=0D - EFI_PCI_EXPRESS_ATOMIC_OP SetupAtomicOp;=0D - BOOLEAN SetupLtr;=0D - UINT8 SetupExtTag;=0D - UINT8 SetupAspm;=0D - EFI_PCI_EXPRESS_COMMON_CLOCK_CFG SetupCcc;=0D };=0D =0D #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index e3ad105..3b1559e 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -57,12 +57,6 @@ PciCommand.h=0D PciIo.h=0D PciBus.h=0D - PciFeatureSupport.c=0D - PciFeatureSupport.h=0D - PciPlatformSupport.c=0D - PciPlatformSupport.h=0D - PciExpressFeatures.c=0D - PciExpressFeatures.h=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D @@ -97,8 +91,8 @@ gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES=0D gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES=0D gEfiLoadedImageDevicePathProtocolGuid ## CONSUMES=0D - gEfiPciExpressPlatformProtocolGuid ## SOMETIMES_CONS= UMES=0D - gEfiPciExpressOverrideProtocolGuid ## SOMETIMES_CONS= UMES=0D + gEfiPciExpressPlatformProtocolGuid ## SOMETIMES_CONSUMES=0D + gEfiPciExpressOverrideProtocolGuid ## SOMETIMES_CONSUMES=0D =0D =0D [FeaturePcd]=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModuleP= kg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index 07ee9ba..5724fd6 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -859,16 +859,7 @@ StartPciDevicesOnBridge ( // the platform is required to indicate its requirement for the initia= lization=0D // of PCI Express features by publishing its protocol=0D //=0D - if (=0D - gFullEnumeration=0D - && IsPciExpressProtocolPresent ()=0D - ) {=0D -=0D - Status =3D EnumeratePciExpressFeatures (=0D - Controller,=0D - RootBridge=0D - );=0D - }=0D +=0D //=0D // finally start those PCI bridge port devices only=0D //=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c deleted file mode 100644 index 1e2f4a4..0000000 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c +++ /dev/null @@ -1,2178 +0,0 @@ -/** @file=0D - PCI standard feature support functions implementation for PCI Bus module= ..=0D -=0D -Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include "PciBus.h"=0D -#include "PciFeatureSupport.h"=0D -=0D -VOID=0D -ReportPciWriteError (=0D - IN UINT8 Bus,=0D - IN UINT8 Device,=0D - IN UINT8 Function,=0D - IN UINT32 Offset=0D - )=0D -{=0D - DEBUG ((=0D - DEBUG_ERROR,=0D - "Unexpected PCI register (%d,%d,%d,0x%x) write error!",=0D - Bus,=0D - Device,=0D - Function,=0D - Offset=0D - ));=0D -}=0D -=0D -/**=0D - Compare and Swap the payload value - between the global variable to maai= ntain=0D - common value among all the devices in the PCIe heirarchy from the root b= ridge=0D - device and all its child devices; with the device-sepcific setup value.= =0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS processing of PCI feature Max_Payl= oad_Size=0D - is successful.=0D -**/=0D -EFI_STATUS=0D -CasMaxPayloadSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table=0D - )=0D -{=0D - UINT8 MpsValue;=0D -=0D - //=0D - // align the MPS of the tree to the HCF with this device=0D - //=0D - if (PciExpressConfigurationTable) {=0D - MpsValue =3D PciExpressConfigurationTable->Max_Payload_Size;=0D -=0D - MpsValue =3D MIN (PciDevice->SetupMPS, MpsValue);=0D - PciDevice->SetupMPS =3D MIN (PciDevice->SetupMPS, MpsValue);=0D -=0D - if (MpsValue !=3D PciExpressConfigurationTable->Max_Payload_Size) {=0D - PciExpressConfigurationTable->Max_Payload_Size =3D MpsValue;=0D - }=0D - }=0D -=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "MPS: %d [DevCap:%d],",=0D - PciDevice->SetupMPS, PciDevice->PciExpressCapabilityStructure.DeviceCa= pability.Bits.MaxPayloadSize=0D - ));=0D -=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - The main routine which process the PCI feature Max_Payload_Size as per t= he=0D - device-specific platform policy, as well as in complaince with the PCI B= ase=0D - specification Revision 4, that aligns the value for the entire PCI heira= rchy=0D - starting from its physical PCI Root port / Bridge device.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS processing of PCI feature Max_Payl= oad_Size=0D - is successful.=0D -**/=0D -EFI_STATUS=0D -SetupMaxPayloadSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap;=0D - UINT8 MpsValue;=0D -=0D -=0D - PciDeviceCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceC= apability.Uint32;=0D -=0D - if (PciDevice->SetupMPS =3D=3D EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_AUTO) {= =0D - //=0D - // configure this feature as per its PCIe device capabilities=0D - //=0D - MpsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize;=0D - //=0D - // no change to PCI Root ports without any endpoint device=0D - //=0D - if (IS_PCI_BRIDGE (&PciDevice->Pci) && PciDeviceCap.Bits.MaxPayloadSiz= e) {=0D - if (IsListEmpty (&PciDevice->ChildList)) {=0D - //=0D - // No device on root bridge=0D - //=0D - MpsValue =3D PCIE_MAX_PAYLOAD_SIZE_128B;=0D - }=0D - }=0D - } else {=0D - MpsValue =3D SetDevicePolicyPciExpressMps (PciDevice->SetupMPS);=0D - }=0D - //=0D - // discard device policy override request if greater than PCI device cap= ability=0D - //=0D - PciDevice->SetupMPS =3D MIN ((UINT8)PciDeviceCap.Bits.MaxPayloadSize, Mp= sValue);=0D -=0D - return CasMaxPayloadSize (=0D - PciDevice,=0D - PciExpressConfigurationTable=0D - );=0D -}=0D -=0D -/**=0D - Overrides the PCI Device Control register MaxPayloadSize register field;= if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramMaxPayloadSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CONTROL PcieDev;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - PcieDev.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - if (PcieDev.Bits.MaxPayloadSize !=3D PciDevice->SetupMPS) {=0D - PcieDev.Bits.MaxPayloadSize =3D PciDevice->SetupMPS;=0D - DEBUG (( DEBUG_INFO, "MPS=3D%d,", PciDevice->SetupMPS));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D Pc= ieDev.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - }=0D - } else {=0D - DEBUG (( DEBUG_INFO, "No MPS=3D%d,", PciDevice->SetupMPS));=0D - }=0D -=0D - return Status;=0D -}=0D -=0D -EFI_STATUS=0D -ConditionalCasMaxReadReqSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - //=0D - // align the Max_Read_Request_Size of the PCI tree based on 3 conditions= :=0D - // first, if user defines MRRS for any one PCI device in the tree than a= lign=0D - // all the devices in the PCI tree.=0D - // second, if user override is not define for this PCI tree than setup t= he MRRS=0D - // based on MPS value of the tree to meet the criteria for the isochrono= us=0D - // traffic.=0D - // third, if no user override, or platform firmware policy has not selec= ted=0D - // this PCI bus driver to configure the MPS; than configure the MRRS to = a=0D - // highest common value of PCI device capability for the MPS found among= all=0D - // the PCI devices in this tree=0D - //=0D - if (PciExpressConfigurationTable) {=0D - if (PciExpressConfigurationTable->Lock_Max_Read_Request_Size) {=0D - PciDevice->SetupMRRS =3D PciExpressConfigurationTable->Max_Read_Requ= est_Size;=0D - } else {=0D - if (mPciExpressPlatformPolicy.Mps) {=0D - PciDevice->SetupMRRS =3D PciDevice->SetupMPS;=0D - } else {=0D - PciDevice->SetupMRRS =3D MIN (=0D - PciDevice->SetupMRRS,=0D - PciExpressConfigurationTable->Max_Read_Req= uest_Size=0D - );=0D - }=0D - PciExpressConfigurationTable->Max_Read_Request_Size =3D PciDevice->S= etupMRRS;=0D - }=0D - }=0D - DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS));=0D -=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - The main routine which process the PCI feature Max_Read_Req_Size as per = the=0D - device-specific platform policy, as well as in complaince with the PCI B= ase=0D - specification Revision 4, that aligns the value for the entire PCI heira= rchy=0D - starting from its physical PCI Root port / Bridge device.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS processing of PCI feature Max_Read= _Req_Size=0D - is successful.=0D -**/=0D -EFI_STATUS=0D -SetupMaxReadReqSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap;=0D - UINT8 MrrsValue;=0D -=0D - PciDeviceCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceC= apability.Uint32;=0D -=0D - if (PciDevice->SetupMRRS =3D=3D EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_AUTO) = {=0D - //=0D - // The maximum read request size is not the data packet size of the TL= P,=0D - // but the memory read request size, and set to the function as a requ= estor=0D - // to not exceed this limit.=0D - // However, for the PCI device capable of isochronous traffic; this me= mory read=0D - // request size should not extend beyond the Max_Payload_Size. Thus, i= n case if=0D - // device policy return by platform indicates to set as per device cap= ability=0D - // than set as per Max_Payload_Size configuration value=0D - //=0D - if (mPciExpressPlatformPolicy.Mps) {=0D - MrrsValue =3D PciDevice->SetupMPS;=0D - } else {=0D - //=0D - // in case this driver is not required to configure the Max_Payload_= Size=0D - // than consider programming HCF of the device capability's Max_Payl= oad_Size=0D - // in this PCI hierarchy; thus making this an implementation specifi= c feature=0D - // which the platform should avoid. For better results, the platform= should=0D - // make both the Max_Payload_Size & Max_Read_Request_Size to be conf= igured=0D - // by this driver=0D - //=0D - MrrsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize;=0D - }=0D - } else {=0D - //=0D - // override as per platform based device policy=0D - //=0D - MrrsValue =3D SetDevicePolicyPciExpressMrrs (PciDevice->SetupMRRS);=0D - //=0D - // align this device's Max_Read_Request_Size value to the entire PCI t= ree=0D - //=0D - if (PciExpressConfigurationTable) {=0D - if (!PciExpressConfigurationTable->Lock_Max_Read_Request_Size) {=0D - PciExpressConfigurationTable->Lock_Max_Read_Request_Size =3D TRUE;= =0D - PciExpressConfigurationTable->Max_Read_Request_Size =3D MrrsValue;= =0D - } else {=0D - //=0D - // in case of another user enforced value of MRRS within the same = tree,=0D - // pick the smallest between the locked value and this value; to s= et=0D - // across entire PCI tree nodes=0D - //=0D - MrrsValue =3D MIN (=0D - MrrsValue,=0D - PciExpressConfigurationTable->Max_Read_Request_Size= =0D - );=0D - PciExpressConfigurationTable->Max_Read_Request_Size =3D MrrsValue;= =0D - }=0D - }=0D - }=0D - //=0D - // align this device's Max_Read_Request_Size to derived configuration va= lue=0D - //=0D - PciDevice->SetupMRRS =3D MrrsValue;=0D -=0D - return ConditionalCasMaxReadReqSize (=0D - PciDevice,=0D - PciExpressConfigurationTable=0D - );=0D -}=0D -=0D -=0D -/**=0D - Overrides the PCI Device Control register Max_Read_Req_Size register fie= ld; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI controller.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramMaxReadReqSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CONTROL PcieDev;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - PcieDev.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - if (PcieDev.Bits.MaxReadRequestSize !=3D PciDevice->SetupMRRS) {=0D - PcieDev.Bits.MaxReadRequestSize =3D PciDevice->SetupMRRS;=0D - DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D Pc= ieDev.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - }=0D - } else {=0D - DEBUG (( DEBUG_INFO, "No MRRS=3D%d,", PciDevice->SetupMRRS));=0D - }=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - Overrides the PCI Device Control register Relax Order register field; if= =0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramRelaxOrder (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CONTROL PcieDev;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - PcieDev.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - if (PciDevice->SetupRO.Override=0D - && PcieDev.Bits.RelaxedOrdering !=3D PciDevice->SetupRO.Act=0D - ) {=0D - PcieDev.Bits.RelaxedOrdering =3D PciDevice->SetupRO.Act;=0D - DEBUG (( DEBUG_INFO, "RO=3D%d,", PciDevice->SetupRO.Act));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D Pc= ieDev.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - }=0D - } else {=0D - DEBUG (( DEBUG_INFO, "No RO,", PciDevice->SetupRO.Act));=0D - }=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - Overrides the PCI Device Control register No-Snoop register field; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramNoSnoop (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CONTROL PcieDev;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - PcieDev.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - if (PciDevice->SetupNS.Override=0D - && PcieDev.Bits.NoSnoop !=3D PciDevice->SetupNS.Act=0D - ) {=0D - PcieDev.Bits.NoSnoop =3D PciDevice->SetupNS.Act;=0D - DEBUG (( DEBUG_INFO, "NS=3D%d", PciDevice->SetupNS.Act));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D Pc= ieDev.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - }=0D - } else {=0D - DEBUG (( DEBUG_INFO, "No NS,", PciDevice->SetupRO.Act));=0D - }=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - To determine the CTO Range A values=0D -=0D - @param CtoValue input CTO range value from 0 to 14=0D - @retval TRUE the given CTO value belongs to Range A=0D - FALSE the given value does not belong to Range A=0D -**/=0D -BOOLEAN=0D -IsCtoRangeA (=0D - IN UINT8 CtoValue=0D - )=0D -{=0D - switch (CtoValue) {=0D - case PCIE_COMPLETION_TIMEOUT_50US_100US:=0D - case PCIE_COMPLETION_TIMEOUT_1MS_10MS:=0D - return TRUE;=0D - }=0D - return FALSE;=0D -}=0D -=0D -/**=0D - To determine the CTO Range B values=0D -=0D - @param CtoValue input CTO range value from 0 to 14=0D - @retval TRUE the given CTO value belongs to Range B=0D - FALSE the given value does not belong to Range B=0D -**/=0D -BOOLEAN=0D -IsCtoRangeB (=0D - IN UINT8 CtoValue=0D - )=0D -{=0D - switch (CtoValue) {=0D - case PCIE_COMPLETION_TIMEOUT_16MS_55MS:=0D - case PCIE_COMPLETION_TIMEOUT_65MS_210MS:=0D - return TRUE;=0D - }=0D - return FALSE;=0D -}=0D -=0D -/**=0D - To determine the CTO Range C values=0D -=0D - @param CtoValue input CTO range value from 0 to 14=0D - @retval TRUE the given CTO value belongs to Range C=0D - FALSE the given value does not belong to Range C=0D -**/=0D -BOOLEAN=0D -IsCtoRangeC (=0D - IN UINT8 CtoValue=0D - )=0D -{=0D - switch (CtoValue) {=0D - case PCIE_COMPLETION_TIMEOUT_260MS_900MS:=0D - case PCIE_COMPLETION_TIMEOUT_1S_3_5S:=0D - return TRUE;=0D - }=0D - return FALSE;=0D -}=0D -=0D -/**=0D - To determine the CTO Range D values=0D -=0D - @param CtoValue input CTO range value from 0 to 14=0D - @retval TRUE the given CTO value belongs to Range D=0D - FALSE the given value does not belong to Range D=0D -**/=0D -BOOLEAN=0D -IsCtoRangeD (=0D - IN UINT8 CtoValue=0D - )=0D -{=0D - switch (CtoValue) {=0D - case PCIE_COMPLETION_TIMEOUT_4S_13S:=0D - case PCIE_COMPLETION_TIMEOUT_17S_64S:=0D - return TRUE;=0D - }=0D - return FALSE;=0D -}=0D -=0D -/**=0D - The main routine which setup the PCI feature Completion Timeout as per t= he=0D - device-specific platform policy, as well as in complaince with the PCI B= ase=0D - specification Revision 4.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D -=0D - @retval EFI_SUCCESS processing of PCI feature CTO is s= uccessful.=0D -**/=0D -EFI_STATUS=0D -SetupCompletionTimeout (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2;=0D - UINT8 CtoRangeValue;=0D -=0D - if (!PciDevice->SetupCTO.Override) {=0D - //=0D - // No override of CTO is required for this device=0D - //=0D - return EFI_SUCCESS;=0D - }=0D -=0D - //=0D - // determine the CTO range values as per its device capability register= =0D - //=0D - DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceCap= ability2.Uint32;=0D - if (!DeviceCap2.Bits.CompletionTimeoutRanges=0D - && !DeviceCap2.Bits.CompletionTimeoutDisable=0D - ) {=0D - //=0D - // device does not support the CTO mechanism, hence no override is app= licable=0D - //=0D - return EFI_SUCCESS;=0D - }=0D -=0D - //=0D - // override the device CTO values if applicable=0D - //=0D - if (PciDevice->SetupCTO.Act) {=0D - //=0D - // program the CTO range values=0D - //=0D - if (DeviceCap2.Bits.CompletionTimeoutRanges) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS;=0D - //=0D - // in case if the supported CTO range and the requirement from platf= orm=0D - // policy does not match, than the CTO range setting would be based = on=0D - // this driver's implementation specific, and its rules are as follo= ws:-=0D - //=0D - // if device is capable of Range A only and if platform ask for any = of=0D - // ranges B, C, D; than this implementation will only program the de= fault=0D - // range value for the duration of 50us to 50ms.=0D - //=0D - // if device is capable of Range B, or range B & C, or Ranges B, C &= D only=0D - // and if the platform ask for the Range A; than this implementation= will=0D - // only program the default range value for the duration of 50us to = 50ms.=0D - //=0D - // if the device is capable of Range B only, or the ranges A & B; an= d the=0D - // platform ask for Range C, or Range D values, than this implementa= tion=0D - // will only program the Range B value for the duration of 65ms to 2= 10ms.=0D - //=0D - // if the device is capable of Ranges B & C, or Ranges A, B, and C; = and=0D - // if the platform ask for Range D values; than this implementation = will=0D - // only program the Range C for the duration of 1s to 3.5s.=0D - //=0D -=0D - switch (DeviceCap2.Bits.CompletionTimeoutRanges) {=0D - case PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED:=0D - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) {=0D - CtoRangeValue =3D PciDevice->SetupCTO.Support;=0D - }=0D - //=0D - // if device is capable of Range A only and if platform ask for = any of=0D - // ranges B, C, D; than this implementation will only program th= e default=0D - // range value for the duration of 50us to 50ms.=0D - //=0D - if (IsCtoRangeB (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeC (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeD (PciDevice->SetupCTO.Support)=0D - ) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS;=0D - }=0D - break;=0D -=0D - case PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED:=0D - //=0D - // if device is capable of Range B, or range B & C, or Ranges B,= C & D only=0D - // and if the platform ask for the Range A; than this implementa= tion will=0D - // only program the default range value for the duration of 50us= to 50ms.=0D - //=0D - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS;=0D - }=0D -=0D - if (IsCtoRangeB (PciDevice->SetupCTO.Support)) {=0D - CtoRangeValue =3D PciDevice->SetupCTO.Support;=0D - }=0D - //=0D - // if the device is capable of Range B only, or the ranges A & B= ; and the=0D - // platform ask for Range C, or Range D values, than this implem= entation=0D - // will only program the Range B value for the duration of 65ms = to 210ms.=0D - //=0D - if (IsCtoRangeC (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeD (PciDevice->SetupCTO.Support)=0D - ) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS;=0D - }=0D - break;=0D -=0D - case PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED:=0D - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS;=0D - }=0D -=0D - if (IsCtoRangeB (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeC (PciDevice->SetupCTO.Support)=0D - ) {=0D - CtoRangeValue =3D PciDevice->SetupCTO.Support;=0D - }=0D - //=0D - // if the device is capable of Ranges B & C, or Ranges A, B, and= C; and=0D - // if the platform ask for Range D values; than this implementat= ion will=0D - // only program the Range C for the duration of 1s to 3.5s.=0D - //=0D - if (IsCtoRangeD (PciDevice->SetupCTO.Support)) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S;=0D - }=0D - break;=0D -=0D - case PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED:=0D - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS;=0D - }=0D - if (IsCtoRangeB (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeC (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeD (PciDevice->SetupCTO.Support)=0D - ) {=0D - CtoRangeValue =3D PciDevice->SetupCTO.Support;=0D - }=0D - break;=0D -=0D - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED:=0D - if (IsCtoRangeA (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeB (PciDevice->SetupCTO.Support)=0D - ) {=0D - CtoRangeValue =3D PciDevice->SetupCTO.Support;=0D - }=0D - if (IsCtoRangeC (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeD (PciDevice->SetupCTO.Support)=0D - ) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS;=0D - }=0D - break;=0D -=0D - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED:=0D - if (IsCtoRangeA (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeB (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeC (PciDevice->SetupCTO.Support)=0D - ) {=0D - CtoRangeValue =3D PciDevice->SetupCTO.Support;=0D - }=0D - if (IsCtoRangeD (PciDevice->SetupCTO.Support)) {=0D - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S;=0D - }=0D - break;=0D -=0D - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED:=0D - if (IsCtoRangeA (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeB (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeC (PciDevice->SetupCTO.Support)=0D - || IsCtoRangeD (PciDevice->SetupCTO.Support)=0D - ) {=0D - CtoRangeValue =3D PciDevice->SetupCTO.Support;=0D - }=0D - break;=0D -=0D - default:=0D - DEBUG ((=0D - DEBUG_ERROR,=0D - "Invalid CTO range: %d\n",=0D - DeviceCap2.Bits.CompletionTimeoutRanges=0D - ));=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - if (PciDevice->SetupCTO.Support !=3D CtoRangeValue) {=0D - PciDevice->SetupCTO.Support =3D CtoRangeValue;=0D - }=0D - }=0D - DEBUG (( DEBUG_INFO, "CTO enable: %d, CTO range: 0x%x,",=0D - PciDevice->SetupCTO.Act,=0D - PciDevice->SetupCTO.Support=0D - ));=0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Overrides the PCI Device Control2 register Completion Timeout range; if= =0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramCompletionTimeout (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CONTROL2 DeviceCtl2;=0D - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - if (!PciDevice->SetupCTO.Override) {=0D - //=0D - // No override of CTO is required for this device=0D - //=0D - DEBUG (( DEBUG_INFO, "CTO skipped,"));=0D - return EFI_SUCCESS;=0D - }=0D -=0D - //=0D - // to program the CTO range values, determine in its device capability r= egister=0D - //=0D - DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceCap= ability2.Uint32;=0D - if (DeviceCap2.Bits.CompletionTimeoutRanges=0D - || DeviceCap2.Bits.CompletionTimeoutDisable) {=0D - //=0D - // device supports the CTO mechanism=0D - //=0D - DeviceCtl2.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &DeviceCtl2.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D - } else {=0D - //=0D - // device does not support the CTO mechanism, hence no override perfor= med=0D - //=0D - DEBUG (( DEBUG_INFO, "CTO n/a,"));=0D - return EFI_SUCCESS;=0D - }=0D -=0D - //=0D - // override the device CTO values if applicable=0D - //=0D - if (PciDevice->SetupCTO.Act) {=0D - //=0D - // program the CTO range values=0D - //=0D - if (PciDevice->SetupCTO.Support !=3D DeviceCtl2.Bits.CompletionTimeout= Value) {=0D - DeviceCtl2.Bits.CompletionTimeoutValue =3D PciDevice->SetupCTO.Suppo= rt;=0D - }=0D - } else {=0D - //=0D - // disable the CTO mechanism in device=0D - //=0D - DeviceCtl2.Bits.CompletionTimeoutValue =3D 0;=0D - DeviceCtl2.Bits.CompletionTimeoutDisable =3D 1;=0D - }=0D - DEBUG (( DEBUG_INFO, "CTO disable: %d, CTO range: 0x%x,",=0D - DeviceCtl2.Bits.CompletionTimeoutDisable,=0D - DeviceCtl2.Bits.CompletionTimeoutValue=0D - ));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write op= eration completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &DeviceCtl2.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D Dev= iceCtl2.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, Pc= iDevice->FunctionNumber, Offset);=0D - }=0D - return Status;=0D -}=0D -=0D -/**=0D - Routine to setup the AtomicOp Requester in the PCI device, verifies the = routing=0D - support in the bridge devices, to be complaint as per the PCI Base speci= fication.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExFeatureConfiguration pointer to common configuration ta= ble to=0D - initialize the PCI Express feature= =0D -=0D - @retval EFI_SUCCESS bridge device routing capability i= s successful.=0D - EFI_INVALID_PARAMETER input parameter is NULL=0D -**/=0D -EFI_STATUS=0D -SetupAtomicOpRoutingSupport (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration= =0D - )=0D -{=0D - //=0D - // to enable the AtomicOp Requester in the PCI EP device; its Root Port = (bridge),=0D - // and its PCIe switch upstream & downstream ports (if present) needs to= support=0D - // the AtomicOp Routing capability.=0D - //=0D - if (IS_PCI_BRIDGE (&PciDevice->Pci)) {=0D - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.A= tomicOpRouting) {=0D - //=0D - // since the AtomicOp Routing support flag is initialized as TRUE, n= egate=0D - // in case if any of the PCI Bridge device in the PCI tree does not = support=0D - // the AtomicOp Routing capability=0D - //=0D - if (PciExFeatureConfiguration =3D=3D NULL) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D - PciExFeatureConfiguration->AtomicOpRoutingSupported =3D FALSE;=0D - }=0D - }=0D -=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Overrides the PCI Device Control 2 register AtomicOp Requester enable fi= eld; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramAtomicOp (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CONTROL2 PcieDev;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - PcieDev.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - if (PciDevice->SetupAtomicOp.Override) {=0D - //=0D - // override AtomicOp requester device control bit of the device based = on the=0D - // platform request=0D - //=0D - if (IS_PCI_BRIDGE (&PciDevice->Pci)) {=0D - //=0D - // for a bridge device as AtomicOp Requester function; only platform= override=0D - // request is used to set the device control register=0D - //=0D - if (PcieDev.Bits.AtomicOpRequester !=3D PciDevice->SetupAtomicOp.Ena= ble_AtomicOpRequester) {=0D - PcieDev.Bits.AtomicOpRequester =3D PciDevice->SetupAtomicOp.Enable= _AtomicOpRequester;=0D - }=0D - //=0D - // if platform also request its AtomicOp Egress blocking to be enabl= ed; set=0D - // only if its device capability's AtomicOpRouting bit is 1.=0D - // applicable to only the bridge devices=0D - //=0D - if (PciDevice->SetupAtomicOp.Enable_AtomicOpEgressBlocking) {=0D - if (PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bit= s.AtomicOpRouting) {=0D - PcieDev.Bits.AtomicOpEgressBlocking =3D 1;=0D - }=0D - }=0D - } else {=0D - //=0D - // in the case of non-bridge device=0D - //=0D - if (PciExFeatureConfiguration) {=0D - //=0D - // for a device as AtomicOp Requester function; its bridge devices= should=0D - // support the AtomicOp Routing capability to enable the device's = as a=0D - // requester function=0D - //=0D - if (PciExFeatureConfiguration->AtomicOpRoutingSupported) {=0D - if (PcieDev.Bits.AtomicOpRequester !=3D PciDevice->SetupAtomicOp= .Enable_AtomicOpRequester) {=0D - PcieDev.Bits.AtomicOpRequester =3D PciDevice->SetupAtomicOp.En= able_AtomicOpRequester;=0D - }=0D - }=0D - } else {=0D - //=0D - // for the RCiEP device or the bridge device without any child, se= tup AtomicOp=0D - // Requester as per platform's device policy=0D - //=0D - if (PcieDev.Bits.AtomicOpRequester !=3D PciDevice->SetupAtomicOp.E= nable_AtomicOpRequester) {=0D - PcieDev.Bits.AtomicOpRequester =3D PciDevice->SetupAtomicOp.Enab= le_AtomicOpRequester;=0D - }=0D - }=0D - //=0D - // the enabling of AtomicOp Egress Blocking is not applicable to a n= on-bridge=0D - // device=0D - //=0D - }=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "AtomicOp=3D%d,",=0D - PcieDev.Bits.AtomicOpRequester=0D - ));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D P= cieDev.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - }=0D - } else {=0D - DEBUG (( DEBUG_INFO, "No AtomicOp,"));=0D - }=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - The main routine which process the PCI feature LTR enable/disable as per= the=0D - device-specific platform policy, as well as in complaince with the PCI E= xpress=0D - Base specification Revision 5.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -SetupLtr (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2;=0D - //=0D - // as per the PCI-Express Base Specification, in order to enable LTR mec= hanism=0D - // in the upstream ports, all the upstream ports and its downstream port= s has=0D - // to support the LTR mechanism reported in its Device Capability 2 regi= ster=0D - //=0D - DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceCap= ability2.Uint32;=0D -=0D - if (PciExpressConfigurationTable) {=0D - //=0D - // in this phase establish 2 requirements:=0D - // (1) all the PCI devices in the hierarchy supports the LTR mechanism= =0D - // (2) check and record any device-specific platform policy that wants= to=0D - // enable the LTR mechanism=0D - //=0D - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.L= trMechanism) {=0D -=0D - //=0D - // it starts with the assumption that all the PCI devices support LT= R mechanism=0D - // and negates the flag if any PCI device Device Capability 2 regist= er advertizes=0D - // as not supported=0D - //=0D - PciExpressConfigurationTable->LtrSupported =3D FALSE;=0D - }=0D -=0D - if (PciDevice->SetupLtr =3D=3D TRUE) {=0D - //=0D - // it starts with the assumption that device-specific platform polic= y would=0D - // be set to LTR disable, and negates the flag if any PCI device pla= tform=0D - // policy wants to override to enable the LTR mechanism=0D - //=0D - PciExpressConfigurationTable->LtrEnable =3D TRUE;=0D - }=0D - } else {=0D - //=0D - // in case of RCiEP device or the bridge device with out any child dev= ice,=0D - // overrule the device policy if the device in not capable=0D - //=0D - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.L= trMechanism=0D - && PciDevice->SetupLtr =3D=3D TRUE) {=0D - PciDevice->SetupLtr =3D FALSE;=0D - }=0D - //=0D - // for any bridge device which is Hot-Plug capable, it is expected tha= t platform=0D - // will not enforce the enabling of LTR mechanism only for the bridge = device=0D - //=0D - }=0D -=0D - DEBUG (( DEBUG_INFO, "LTR En: %d (LTR Cap: %d),",=0D - PciDevice->SetupLtr ? 1 : 0,=0D - PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.LtrMec= hanism=0D - ));=0D - return EFI_SUCCESS;=0D -}=0D -=0D -EFI_STATUS=0D -ReSetupLtr (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - //=0D - // not applicable to RCiEP device...=0D - // for the bridge device without any child device, the policy is already= overruled=0D - // based on capability in the above routine=0D - //=0D - if (PciExpressConfigurationTable) {=0D - //=0D - // in this phase align the device policy to enable LTR policy of any P= CI device=0D - // in the tree if all the devices are capable to support the LTR mecha= nism=0D - //=0D - if (PciExpressConfigurationTable->LtrSupported =3D=3D TRUE=0D - && PciExpressConfigurationTable->LtrEnable =3D=3D TRUE=0D - ) {=0D - PciDevice->SetupLtr =3D TRUE;=0D - } else {=0D - PciDevice->SetupLtr =3D FALSE;=0D - }=0D - }=0D -=0D - DEBUG (( DEBUG_INFO, "LTR En: %d (LTR Cap: %d),",=0D - PciDevice->SetupLtr ? 1 : 0,=0D - PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.LtrMec= hanism=0D - ));=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Program the PCI Device Control 2 register LTR mechanism field; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramLtr (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CONTROL2 PcieDev;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - PcieDev.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - if (PciDevice->SetupLtr !=3D (BOOLEAN) PcieDev.Bits.LtrMechanism) {=0D - PcieDev.Bits.LtrMechanism =3D PciDevice->SetupLtr ? 1 : 0;=0D - DEBUG (( DEBUG_INFO, "LTR=3D%d,", PcieDev.Bits.LtrMechanism));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &PcieDev.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D P= cieDev.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - }=0D - } else {=0D - DEBUG (( DEBUG_INFO, "no LTR,"));=0D - }=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - The main routine to setup the PCI Express feature Extended Tag as per th= e=0D - device-specific platform policy, as well as in complaince with the PCI E= xpress=0D - Base specification Revision 5.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -SetupExtTag (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2;=0D - PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCap;=0D - EFI_PCI_EXPRESS_EXTENDED_TAG PciExpressExtendedTag;=0D -=0D - DeviceCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceCapa= bility.Uint32;=0D - DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceCap= ability2.Uint32;=0D - //=0D - // The PCI Express feature Extended Tag has to be maintained common from= a=0D - // root bridge device to all its child devices.=0D - // The Device Capability 2 register is used to determine the 10b Extende= d Tag=0D - // capability of a device. The device capability register is used to det= ermine=0D - // 5b/8b Extended Tag capability of a device=0D - //=0D - if (DeviceCap2.Bits.TenBitTagCompleterSupported & DeviceCap2.Bits.TenBit= TagRequesterSupported) {=0D - //=0D - // device supports the 10b Extended Tag capability=0D - //=0D - PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT;=0D - } else {=0D - if (DeviceCap.Bits.ExtendedTagField) {=0D - PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT;=0D - } else {=0D - PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT;=0D - }=0D - }=0D - if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_AUTO) {=0D - PciDevice->SetupExtTag =3D PciExpressExtendedTag;=0D - }=0D - //=0D - // in case of PCI Bridge and its child devices=0D - //=0D - if (PciExpressConfigurationTable) {=0D - //=0D - // align the Extended Tag value as per the device supported value=0D - //=0D - PciExpressConfigurationTable->ExtendedTag =3D MIN (=0D - PciExpressExtendedTag,=0D - PciExpressConfigurationT= able->ExtendedTag=0D - );=0D - //=0D - // check for any invalid platform policy request for the device; if tr= ue than=0D - // align with the device capability value. Else align as per platform = request=0D - //=0D - if (PciDevice->SetupExtTag > PciExpressConfigurationTable->ExtendedTag= ) {=0D - //=0D - // setup the device Extended Tag to common value supported by all th= e devices=0D - //=0D - PciDevice->SetupExtTag =3D PciExpressConfigurationTable->ExtendedTag= ;=0D - }=0D - //=0D - // if the platform policy is to downgrade the device's Extended Tag va= lue than=0D - // all the other devices in the PCI tree including the root bridge wil= l be align=0D - // with this device override value=0D - //=0D - if (PciDevice->SetupExtTag < PciExpressConfigurationTable->ExtendedTag= ) {=0D - PciExpressConfigurationTable->ExtendedTag =3D PciDevice->SetupExtTag= ;=0D - }=0D - } else {=0D - //=0D - // in case of RCiEP devices or the bridge device without any child, ov= errule=0D - // the Extended Tag device policy if it does not match with its capabi= lity=0D - //=0D - PciDevice->SetupExtTag =3D MIN (=0D - PciDevice->SetupExtTag,=0D - PciExpressExtendedTag=0D - );=0D - }=0D -=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "ExtTag: %d [cap:%d],",=0D - PciDevice->SetupExtTag,=0D - PciExpressExtendedTag=0D - ));=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Additional routine to setup the PCI Express feature Extended Tag in comp= laince=0D - with the PCI Express Base specification Revision, a common value for all= the=0D - devices in the PCI hierarchy.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -AlignExtTag (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - if (PciExpressConfigurationTable) {=0D - //=0D - // align the Extended Tag value to a common value among all the device= s=0D - //=0D - PciDevice->SetupExtTag =3D MIN (=0D - PciDevice->SetupExtTag,=0D - PciExpressConfigurationTable->ExtendedTag=0D - );=0D - }=0D -=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "ExtTag: %d,",=0D - PciDevice->SetupExtTag=0D - ));=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Program the PCI Device Control 2 register for 10b Extended Tag value, or= the=0D - Device Control register for 5b/8b Extended Tag value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramExtTag (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_DEVICE_CONTROL DevCtl;=0D - PCI_REG_PCIE_DEVICE_CONTROL2 DevCtl2;=0D - UINT32 Offset;=0D - UINT32 Offset2;=0D - BOOLEAN OverrideDevCtl;=0D - BOOLEAN OverrideDevCtl2;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - //=0D - // read the Device Control register for the Extended Tag Field Enable=0D - //=0D - DevCtl.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &DevCtl.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - OverrideDevCtl =3D FALSE;=0D - //=0D - // read the Device COntrol 2 register for the 10-Bit Tag Requester Enabl= e=0D - //=0D - DevCtl2.Uint16 =3D 0;=0D - Offset2 =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset2,=0D - 1,=0D - &DevCtl2.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - OverrideDevCtl2 =3D FALSE;=0D -=0D - if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT) {=0D - if (DevCtl.Bits.ExtendedTagField) {=0D - DevCtl.Bits.ExtendedTagField =3D 0;=0D - OverrideDevCtl =3D TRUE;=0D - }=0D -=0D - if (DevCtl2.Bits.TenBitTagRequesterEnable) {=0D - DevCtl2.Bits.TenBitTagRequesterEnable =3D 0;=0D - OverrideDevCtl2 =3D TRUE;=0D - }=0D - }=0D - if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT) {=0D - if (!DevCtl.Bits.ExtendedTagField) {=0D - DevCtl.Bits.ExtendedTagField =3D 1;=0D - OverrideDevCtl =3D TRUE;=0D - }=0D - if (DevCtl2.Bits.TenBitTagRequesterEnable) {=0D - DevCtl2.Bits.TenBitTagRequesterEnable =3D 0;=0D - OverrideDevCtl2 =3D TRUE;=0D - }=0D - }=0D - if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT) {= =0D - if (!DevCtl2.Bits.TenBitTagRequesterEnable) {=0D - DevCtl2.Bits.TenBitTagRequesterEnable =3D 1;=0D - OverrideDevCtl2 =3D TRUE;=0D - }=0D - }=0D -=0D - if (OverrideDevCtl) {=0D -=0D - DEBUG (( DEBUG_INFO, "ExtTag=3D%d,", DevCtl.Bits.ExtendedTagField));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &DevCtl.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D De= vCtl.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - }=0D - } else {=0D - DEBUG (( DEBUG_INFO, "no ExtTag (%d),", DevCtl.Bits.ExtendedTagField))= ;=0D - }=0D -=0D - if (OverrideDevCtl2) {=0D -=0D - DEBUG (( DEBUG_INFO, "10bExtTag=3D%d,", DevCtl2.Bits.TenBitTagRequeste= rEnable));=0D -=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset2,=0D - 1,=0D - &DevCtl2.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR(Status)) {=0D - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D D= evCtl2.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset2);=0D - }=0D - } else {=0D - DEBUG (( DEBUG_INFO, "no 10bExtTag (%d),", DevCtl2.Bits.TenBitTagReque= sterEnable));=0D - }=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - Set the ASPM device policy as per the device's link capability.=0D -**/=0D -UINT8=0D -SetAspmPolicy (=0D - IN UINT8 PciExpressLinkCapAspm=0D - )=0D -{=0D - switch (PciExpressLinkCapAspm) {=0D - case 0:=0D - //=0D - // cannot support ASPM state, disable=0D - //=0D - return EFI_PCI_EXPRESS_ASPM_DISABLE;=0D - case 1:=0D - //=0D - // supports only ASPM L0s state=0D - //=0D - return EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT;=0D - case 2:=0D - //=0D - // supports only ASPM L1 state=0D - //=0D - return EFI_PCI_EXPRESS_ASPM_L1_SUPPORT;=0D - case 3:=0D - //=0D - // supports both L0s and L1 ASPM states=0D - //=0D - return EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT;=0D - }=0D - return EFI_PCI_EXPRESS_ASPM_DISABLE;=0D -}=0D -=0D -/**=0D - The main routine to setup the PCI Express feature ASPM as per the=0D - device-specific platform policy, as well as in complaince with the PCI E= xpress=0D - Base specification Revision 5.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -SetupAspm (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - PCI_REG_PCIE_LINK_CAPABILITY PciExLinkCap;=0D - PCI_REG_PCIE_DEVICE_CAPABILITY PciExpressDeviceCapability;=0D - BOOLEAN AlignAspmPolicy;=0D -=0D - PciExLinkCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.LinkCap= ability.Uint32;=0D - PciExpressDeviceCapability.Uint32 =3D PciDevice->PciExpressCapabilityStr= ucture.DeviceCapability.Uint32;=0D - //=0D - // ASPM support is only applicable to root bridge and its child devices.= Not=0D - // applicable to empty bridge devices or RCiEP devices=0D - //=0D - if (PciExpressConfigurationTable) {=0D - PciExpressConfigurationTable->L0sExitLatency =3D MAX (=0D - PciExpressConfigurationTable->L0sExitLatency,=0D - (UINT8)PciExLinkCap.Bits.L0sExitLatency=0D - );=0D - PciExpressConfigurationTable->L1ExitLatency =3D MAX (=0D - PciExpressConfigurationTable->L1ExitLatency,=0D - (UINT8)PciExLinkCap.Bits.L1ExitLatency=0D - );=0D - if (PciDevice->SetupAspm =3D=3D EFI_PCI_EXPRESS_ASPM_AUTO) {=0D - //=0D - // set the ASPM support as per device's link capability=0D - //=0D - PciDevice->SetupAspm =3D SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Asp= m);=0D - } else {=0D - //=0D - // Check the ASPM device policy is applicable to the link capability= .=0D - // In case of invalid device policy, there are 2 options:=0D - // (1) ASPM disable -> platform request rightly denied, and no ASPM= =0D - // (2) set as per the device capability -> platform request rightly = denied,=0D - // but still set applicable power management=0D - // this implementation shall take option 2 to overule invalid platfo= rm request=0D - // and go with applicable policy as per device capability=0D - //=0D - switch (SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm)) {=0D - case EFI_PCI_EXPRESS_ASPM_DISABLE:=0D - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_ASPM_DISABLE;=0D - break;=0D - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT:=0D - if (PciDevice->SetupAspm =3D=3D EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT= ) {=0D - //=0D - // not applicable, set as per device's link capability=0D - //=0D - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_ASPM_L1_SUPPORT;=0D - }=0D - break;=0D - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT:=0D - if (PciDevice->SetupAspm =3D=3D EFI_PCI_EXPRESS_ASPM_L1_SUPPORT)= {=0D - //=0D - // not applicable, set as per device's link capability=0D - //=0D - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT;=0D - }=0D - break;=0D - }=0D - }=0D - //=0D - // set the ASPM policy to minimum state among all the devices links=0D - //=0D - PciExpressConfigurationTable->AspmSupport =3D MIN (=0D - PciExpressConfigurationT= able->AspmSupport,=0D - PciDevice->SetupAspm=0D - );=0D - //=0D - // check the common ASPM value applicable as per this device capabilit= y, if=0D - // not applicable disable the ASPM for all the devices=0D - //=0D - if (=0D - (PciExpressConfigurationTable->AspmSupport =3D=3D EFI_PCI_EXPRESS_AS= PM_L0s_SUPPORT=0D - && SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm) =3D=3D EFI_PCI_EX= PRESS_ASPM_L1_SUPPORT)=0D - ||=0D - (PciExpressConfigurationTable->AspmSupport =3D=3D EFI_PCI_EXPRESS_AS= PM_L1_SUPPORT=0D - && SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm) =3D=3D EFI_PCI_EX= PRESS_ASPM_L0s_SUPPORT)=0D - ) {=0D - //=0D - // disable the ASPM=0D - //=0D - PciExpressConfigurationTable->AspmSupport =3D EFI_PCI_EXPRESS_ASPM_D= ISABLE;=0D - PciDevice->SetupAspm =3D PciExpressConfigurationTable->AspmSupport;= =0D - }=0D -=0D - if (PciExpressConfigurationTable->AspmSupport !=3D EFI_PCI_EXPRESS_ASP= M_DISABLE) {=0D - //=0D - // in case of ASPM policy is not to disable the ASPM support, check = other=0D - // condition of EP device L0s/L1 acceptance latency with the L0s/L1 = exit=0D - // latencies comprising from this endpoint all the way up to root co= mplex=0D - // root port, to determine whether the ASPM L0s/L1 entry can be used= with=0D - // no loss of performance=0D - //=0D - if (!IS_PCI_BRIDGE (&PciDevice->Pci)) {=0D -=0D - switch (PciExpressConfigurationTable->AspmSupport) {=0D - case EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT:=0D - if (=0D - PciExpressDeviceCapability.Bits.EndpointL0sAcceptableLaten= cy >=3D PciExpressConfigurationTable->L0sExitLatency=0D - && PciExpressDeviceCapability.Bits.EndpointL1AcceptableLat= ency >=3D PciExpressConfigurationTable->L1ExitLatency=0D - ) {=0D - //=0D - // both the L0s & L1 acceptance of this endpoint device is g= reater=0D - // than or equal to all of the comprised L0s & L1 exit laten= cies=0D - // thus good to set the ASPM to L0s & L1 state=0D - //=0D - AlignAspmPolicy =3D TRUE;=0D - } else {=0D - //=0D - // in case the EP device L0s and L1 Acceptance latency does = not match=0D - // with the comprised L0s & L1 exit latencies than disable t= he ASPM=0D - // state=0D - //=0D - AlignAspmPolicy =3D FALSE;=0D - }=0D - break;=0D -=0D - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT:=0D - if (=0D - PciExpressDeviceCapability.Bits.EndpointL1AcceptableLatenc= y >=3D PciExpressConfigurationTable->L1ExitLatency=0D - ) {=0D - //=0D - // the endpoint device L1 acceptance latency meets the all t= he=0D - // comprised L1 exit latencies of all the devices from the b= ridge=0D - // hence ASPM L1 is applicable state for the PCI tree=0D - //=0D - AlignAspmPolicy =3D TRUE;=0D - } else {=0D - //=0D - // in case the EP device L1 Acceptance latency does not matc= h=0D - // with the comprised L1 exit latencies than disable the ASP= M=0D - // state=0D - //=0D - AlignAspmPolicy =3D FALSE;=0D - }=0D - break;=0D -=0D - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT:=0D - if (=0D - PciExpressDeviceCapability.Bits.EndpointL0sAcceptableLaten= cy >=3D PciExpressConfigurationTable->L0sExitLatency=0D - ) {=0D - //=0D - // the endpoint device L0s acceptance latency meets the all = the=0D - // comprised L0s exit latencies of all the devices from the = bridge=0D - // hence ASPM L0s is applicable state for the PCI tree=0D - //=0D - AlignAspmPolicy =3D TRUE;=0D - } else {=0D - //=0D - // in case the EP device L0s Acceptance latency does not mat= ch=0D - // with the comprised L0s exit latencies than disable the AS= PM=0D - // state=0D - //=0D - AlignAspmPolicy =3D FALSE;=0D - }=0D - break;=0D - }=0D - } else {=0D - //=0D - // align the bridge with the global common ASPM value=0D - //=0D - AlignAspmPolicy =3D TRUE;=0D - }=0D - } else {=0D - //=0D - // ASPM is disabled for all the devices=0D - //=0D - AlignAspmPolicy =3D FALSE;=0D - }=0D -=0D - if (AlignAspmPolicy) {=0D - //=0D - // reset the device's ASPM policy to common minimum value=0D - //=0D - if (PciDevice->SetupAspm !=3D PciExpressConfigurationTable->AspmSupp= ort) {=0D - PciDevice->SetupAspm =3D PciExpressConfigurationTable->AspmSupport= ;=0D - }=0D - } else {=0D - //=0D - // disable the ASPM=0D - //=0D - PciExpressConfigurationTable->AspmSupport =3D EFI_PCI_EXPRESS_ASPM_D= ISABLE;=0D - PciDevice->SetupAspm =3D PciExpressConfigurationTable->AspmSupport;= =0D - }=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "Aspm: %d [cap:%d],",=0D - PciDevice->SetupAspm,=0D - (PciExLinkCap.Bits.Aspm + 1)=0D - ));=0D - }=0D -=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Setup of PCI Express feature ASPM in the PciExpressFeatureEntendedSetupP= hase=0D -**/=0D -EFI_STATUS=0D -AlignAspm (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - //=0D - // ASPM support is only applicable to root bridge and its child devices.= Not=0D - // applicable to empty bridge devices or RCiEP devices=0D - //=0D - if (PciExpressConfigurationTable) {=0D - //=0D - // reset the device's ASPM policy to common minimum ASPM value=0D - //=0D - if (PciDevice->SetupAspm !=3D PciExpressConfigurationTable->AspmSuppor= t) {=0D - PciDevice->SetupAspm =3D PciExpressConfigurationTable->AspmSupport;= =0D - }=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "Aspm: %d,",=0D - PciDevice->SetupAspm=0D - ));=0D - }=0D -=0D - return EFI_SUCCESS;=0D -}=0D -=0D -=0D -/**=0D - Get the ASPM value from the ASPM device policy.=0D -**/=0D -UINT8=0D -GetAspmValue (=0D - IN UINT8 AspmPolicy=0D - )=0D -{=0D - switch (AspmPolicy) {=0D - case EFI_PCI_EXPRESS_ASPM_DISABLE:=0D - //=0D - // ASPM disable=0D - //=0D - return 0;=0D - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT:=0D - //=0D - // ASPM L0s state=0D - //=0D - return 1;=0D - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT:=0D - //=0D - // ASPM L1 state=0D - //=0D - return 2;=0D - case EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT:=0D - //=0D - // L0s and L1 ASPM states=0D - //=0D - return 3;=0D - }=0D - return 0;=0D -}=0D -=0D -/**=0D - Program the PCIe Link Control register ASPM Control field; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramAspm (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_LINK_CONTROL LinkCtl;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D - UINT8 AspmValue;=0D -=0D - //=0D - // ASPM support is only applicable to root bridge and its child devices.= Not=0D - // applicable to empty bridge devices or RCiEP devices=0D - //=0D - if (!PciExFeatureConfiguration) {=0D - return EFI_SUCCESS;=0D - }=0D -=0D - //=0D - // read the link Control register for the ASPM Control=0D - //=0D - LinkCtl.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &LinkCtl.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - AspmValue =3D GetAspmValue (PciDevice->SetupAspm);=0D - if (AspmValue !=3D LinkCtl.Bits.AspmControl) {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "Aspm: %d,",=0D - AspmValue=0D - ));=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &LinkCtl.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR (Status)) {=0D - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 =3D Link= Ctl.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - return Status;=0D - }=0D - } else {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "No Aspm (%d),",=0D - AspmValue=0D - ));=0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - The main routine to setup the PCI Express feature Common Clock configura= tion=0D - as per the device-specific platform policy, as well as in complaince wit= h the=0D - PCI Express Base specification Revision 5.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -SetupCommonClkCfg (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - )=0D -{=0D - PCI_REG_PCIE_LINK_STATUS LinkSts;=0D -=0D - LinkSts.Uint16 =3D PciDevice->PciExpressCapabilityStructure.LinkStatus.U= int16;=0D -=0D - //=0D - // Common Clock Configuration is only applicable to root bridge and its = child=0D - // devices. Not applicable to empty bridge devices or RCiEP devices=0D - //=0D - if (PciExpressConfigurationTable) {=0D - if (PciDevice->SetupCcc =3D=3D EFI_PCI_EXPRESS_CLK_CFG_AUTO) {=0D - //=0D - // as per the PCI Express Base Specification, the link status regist= er=0D - // slot clock configuration of the opposing side of link devices ind= icate=0D - // the clock configuration properly; hence rely on this data to conf= igure=0D - // the link's clock configuration=0D - //=0D - if (LinkSts.Bits.SlotClockConfiguration) {=0D - PciExpressConfigurationTable->CommonClockConfiguration =3D TRUE;=0D - } else {=0D - PciExpressConfigurationTable->CommonClockConfiguration =3D FALSE;= =0D - }=0D - } else if (PciDevice->SetupCcc =3D=3D EFI_PCI_EXPRESS_CLK_CFG_ASYNCH) = {=0D - //=0D - // platform override to any device shall change for other device on = the=0D - // link, the clock configuration has to be maintained common across = all=0D - // the devices=0D - //=0D - PciExpressConfigurationTable->CommonClockConfiguration =3D FALSE;=0D - } else {=0D - PciExpressConfigurationTable->CommonClockConfiguration =3D TRUE;=0D - }=0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Program the PCIe Link Control register Coomon Clock Configuration field;= if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramCcc (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_LINK_CONTROL LinkCtl;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - //=0D - // Common Clock Configuration is only applicable to root bridge and its = child=0D - // devices. Not applicable to empty bridge devices or RCiEP devices=0D - //=0D - if (!PciExFeatureConfiguration) {=0D - return EFI_SUCCESS;=0D - }=0D -=0D - //=0D - // read the link Control register for the ASPM Control=0D - //=0D - LinkCtl.Uint16 =3D 0;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl);=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &LinkCtl.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D -=0D - //=0D - // in case Common Clock Configuration is required to be programmed in th= e=0D - // downstream ports from the root bridge devices in the heirarchy=0D - //=0D - if (PciExFeatureConfiguration->CommonClockConfiguration =3D=3D TRUE) {=0D - if (LinkCtl.Bits.CommonClockConfiguration =3D=3D 0) {=0D - LinkCtl.Bits.CommonClockConfiguration =3D 1;=0D - //=0D - // current clock mode does not match hence retrain of the link at br= idge device=0D - // is required=0D - //=0D - PciExFeatureConfiguration->LinkReTrain =3D TRUE;=0D - }=0D - } else {=0D - //=0D - // in case the opposing devices of the PCI link have different referen= ce clock=0D - // set the link control register CCC field accordingly=0D - //=0D - if (LinkCtl.Bits.CommonClockConfiguration) {=0D - LinkCtl.Bits.CommonClockConfiguration =3D 0;=0D - //=0D - // current clock mode does not match hence retrain of the link at br= idge device=0D - // is required=0D - //=0D - PciExFeatureConfiguration->LinkReTrain =3D TRUE;=0D - }=0D - }=0D - //=0D - // use the retrain flag as a sigm to also update the CCC of the link reg= ister=0D - //=0D - if (PciExFeatureConfiguration->LinkReTrain =3D=3D TRUE) {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "CCC: %d,",=0D - LinkCtl.Bits.CommonClockConfiguration=0D - ));=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the write = operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &LinkCtl.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR (Status)) {=0D - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 =3D Link= Ctl.Uint16;=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset);=0D - return Status;=0D - }=0D - } else {=0D - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 =3D LinkCt= l.Uint16;=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "No CCC (%d),",=0D - LinkCtl.Bits.CommonClockConfiguration=0D - ));=0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Second phase of programming for Common Clock COnfiguration, conditoonall= y done=0D - only on the downstream ports (bridge devices only).=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -EnforceCcc (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration=0D - )=0D -{=0D - PCI_REG_PCIE_LINK_CONTROL LinkCtl;=0D - PCI_REG_PCIE_LINK_STATUS LinkSts;=0D - PCI_REG_PCIE_CAPABILITY PciExCap;=0D - UINT32 Offset;=0D - EFI_STATUS Status;=0D - EFI_TPL OldTpl;=0D -=0D - //=0D - // Common Clock Configuration is only applicable to root bridge and its = child=0D - // devices. Not applicable to empty bridge devices or RCiEP devices=0D - //=0D - if (!PciExFeatureConfiguration) {=0D - return EFI_SUCCESS;=0D - }=0D - PciExCap.Uint16 =3D PciDevice->PciExpressCapabilityStructure.Capability.= Uint16;=0D - LinkCtl.Uint16 =3D PciDevice->PciExpressCapabilityStructure.LinkControl.= Uint16;=0D -=0D - //=0D - // retrain the bridge device (downstream ports including the root port)= =0D - //=0D - if (PciExFeatureConfiguration->LinkReTrain =3D=3D TRUE) {=0D - if (IS_PCI_BRIDGE (&PciDevice->Pci)) {=0D - //=0D - // retrain of the PCI link happens for CCC change only on the downst= ream=0D - // ports=0D - //=0D - if (=0D - PciExCap.Bits.DevicePortType =3D=3D PCIE_DEVICE_PORT_TYPE_ROOT_POR= T=0D - || PciExCap.Bits.DevicePortType =3D=3D PCIE_DEVICE_PORT_TYPE_DOWNS= TREAM_PORT=0D - ) {=0D - LinkCtl.Bits.RetrainLink =3D 1;=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl);=0D - //=0D - // Raise TPL to high level to disable timer interrupt while the wr= ite operation completes=0D - //=0D - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D -=0D - Status =3D PciDevice->PciIo.Pci.Write (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &LinkCtl.Uint16=0D - );=0D - //=0D - // Restore TPL to its original level=0D - //=0D - gBS->RestoreTPL (OldTpl);=0D -=0D - if (!EFI_ERROR (Status)) {=0D - //=0D - // poll the link status register for the link retrain to be comp= lete=0D - //=0D - Offset =3D PciDevice->PciExpressCapabilityOffset +=0D - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkStatu= s);=0D - do {=0D - Status =3D PciDevice->PciIo.Pci.Read (=0D - &PciDevice->PciIo,=0D - EfiPciIoWidthUint16,=0D - Offset,=0D - 1,=0D - &LinkSts.Uint16=0D - );=0D - ASSERT (Status =3D=3D EFI_SUCCESS);=0D - } while (LinkSts.Bits.LinkTraining);=0D - } else {=0D - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumb= er, PciDevice->FunctionNumber, Offset);=0D - return Status;=0D - }=0D - }=0D - //=0D - // ignore the upstream bridge devices=0D - //=0D - }=0D - //=0D - // not applicable to endpoint devices=0D - //=0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h deleted file mode 100644 index 33df337..0000000 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h +++ /dev/null @@ -1,399 +0,0 @@ -/** @file=0D - PCI standard feature support functions implementation for PCI Bus module= ..=0D -=0D -Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#ifndef _EFI_PCI_EXPRESS_FEATURES_H_=0D -#define _EFI_PCI_EXPRESS_FEATURES_H_=0D -=0D -//=0D -// PCIe L0s Exit Latencies declarations=0D -//=0D -#define PCIE_LINK_CAPABILITY_L0S_EXIT_LATENCY_64NS 0 // less than 64ns= =0D -=0D -//=0D -// PCIe L1 Exit latencies declarations=0D -//=0D -#define PCIE_LINK_CAPABILITY_L1_EXIT_LATENCY_1US 0 // less than 1us=0D -=0D -/**=0D - The main routine which process the PCI feature Max_Payload_Size as per t= he=0D - device-specific platform policy, as well as in complaince with the PCI B= ase=0D - specification Revision 4, that aligns the value for the entire PCI heira= rchy=0D - starting from its physical PCI Root port / Bridge device.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS processing of PCI feature Max_Payl= oad_Size=0D - is successful.=0D -**/=0D -EFI_STATUS=0D -SetupMaxPayloadSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -EFI_STATUS=0D -CasMaxPayloadSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -/**=0D - Overrides the PCI Device Control register Max_Read_Req_Size register fie= ld; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI controller.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramMaxPayloadSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -=0D -EFI_STATUS=0D -ConditionalCasMaxReadReqSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -/**=0D - The main routine which process the PCI feature Max_Read_Req_Size as per = the=0D - device-specific platform policy, as well as in complaince with the PCI B= ase=0D - specification Revision 4, that aligns the value for the entire PCI heira= rchy=0D - starting from its physical PCI Root port / Bridge device.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciConfigPhase for the PCI feature configuration = phases:=0D - PciExpressFeatureSetupPhase & PciE= xpressFeatureEntendedSetupPhase=0D - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS processing of PCI feature Max_Read= _Req_Size=0D - is successful.=0D -**/=0D -EFI_STATUS=0D -SetupMaxReadReqSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -/**=0D - Overrides the PCI Device Control register Max_Read_Req_Size register fie= ld; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI controller.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramMaxReadReqSize (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - Overrides the PCI Device Control register Relax Order register field; if= =0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramRelaxOrder (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - Overrides the PCI Device Control register No-Snoop register field; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramNoSnoop (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - The main routine which process the PCI feature Completion Timeout as per= the=0D - device-specific platform policy, as well as in complaince with the PCI B= ase=0D - specification Revision 4.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciConfigPhase for the PCI feature configuration = phases:=0D - PciExpressFeatureSetupPhase & PciE= xpressFeatureEntendedSetupPhase=0D -=0D - @retval EFI_SUCCESS processing of PCI feature CTO is s= uccessful.=0D -**/=0D -EFI_STATUS=0D -SetupCompletionTimeout (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - Overrides the PCI Device Control2 register Completion Timeout range; if= =0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramCompletionTimeout (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - Routine to setup the AtomicOp Requester in the PCI device, verifies the = routing=0D - support in the bridge devices, to be complaint as per the PCI Base speci= fication.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExFeatureConfiguration pointer to common configuration ta= ble to=0D - initialize the PCI Express feature= =0D -=0D - @retval EFI_SUCCESS bridge device routing capability i= s successful.=0D - EFI_INVALID_PARAMETER input parameter is NULL=0D -**/=0D -EFI_STATUS=0D -SetupAtomicOpRoutingSupport (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration= =0D - );=0D -=0D -/**=0D - Overrides the PCI Device Control 2 register AtomicOp Requester enable fi= eld; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramAtomicOp (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - The main routine which process the PCI feature LTR enable/disable as per= the=0D - device-specific platform policy, as well as in complaince with the PCI E= xpress=0D - Base specification Revision 5.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -SetupLtr (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -EFI_STATUS=0D -ReSetupLtr (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -/**=0D - Program the PCI Device Control 2 register LTR mechanism field; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramLtr (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - The main routine to setup the PCI Express feature Extended Tag as per th= e=0D - device-specific platform policy, as well as in complaince with the PCI E= xpress=0D - Base specification Revision 5.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -SetupExtTag (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -/**=0D - Additional routine to setup the PCI Express feature Extended Tag in comp= laince=0D - with the PCI Express Base specification Revision, a common value for all= the=0D - devices in the PCI hierarchy.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -AlignExtTag (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -/**=0D - Program the PCI Device Control 2 register for 10b Extended Tag value, or= the=0D - Device Control register for 5b/8b Extended Tag value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramExtTag (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - The main routine to setup the PCI Express feature ASPM as per the=0D - device-specific platform policy, as well as in complaince with the PCI E= xpress=0D - Base specification Revision 5.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -SetupAspm (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -/**=0D - Setup of PCI Express feature ASPM in the PciExpressFeatureEntendedSetupP= hase=0D -**/=0D -EFI_STATUS=0D -AlignAspm (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationT= able=0D - );=0D -=0D -/**=0D - Program the PCIe Link Control register ASPM Control field; if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramAspm (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - The main routine to setup the PCI Express feature Common Clock configura= tion=0D - as per the device-specific platform policy, as well as in complaince wit= h the=0D - PCI Express Base specification Revision 5.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_CON= FIGURATION_TABLE=0D -=0D - @retval EFI_SUCCESS setup of PCI feature LTR is succes= sful.=0D -**/=0D -EFI_STATUS=0D -SetupCommonClkCfg (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurationTa= ble=0D - );=0D -=0D -/**=0D - Program the PCIe Link Control register Coomon Clock Configuration field;= if=0D - the hardware value is different than the intended value.=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -ProgramCcc (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration=0D - );=0D -=0D -/**=0D - Second phase of programming for Common Clock COnfiguration, conditoonall= y done=0D - only on the downstream ports (bridge devices only).=0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE instance.=0D -=0D - @retval EFI_SUCCESS The data was read from or written to the P= CI device.=0D - @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not=0D - valid for the PCI configuration header of = the PCI controller.=0D - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.=0D -=0D -**/=0D -EFI_STATUS=0D -EnforceCcc (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration=0D - );=0D -#endif=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c deleted file mode 100644 index 4d3641c..0000000 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ /dev/null @@ -1,1019 +0,0 @@ -/** @file=0D - PCI standard feature support functions implementation for PCI Bus module= ..=0D -=0D -Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include "PciBus.h"=0D -#include "PciFeatureSupport.h"=0D -#include "PciExpressFeatures.h"=0D -=0D -/**=0D - Hold the current instance of Root Bridge IO protocol Handle=0D -**/=0D -EFI_HANDLE mRootBridgeHandle;=0D -=0D -/**=0D - A gobal pointer to BRIDGE_DEVICE_NODE buffer to track all the primary ph= ysical=0D - PCI Root Ports (PCI Controllers) for a given PCI Root Bridge instance wh= ile=0D - enumerating to configure the PCI features=0D -**/=0D -LIST_ENTRY mRootBridgeDeviceList;=0D -=0D -/**=0D - global list to indicate the supported PCI Express features of this driver= , it=0D - is expected to be overridden based on the platform request=0D -**/=0D -EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPlatformPolicy =3D = {=0D - //=0D - // support for PCI Express feature - Max. Payload Size=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - Max. Read Request Size=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - Extended Tag=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - Relax Order=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - No-Snoop=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - ASPM state=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - Common Clock Configuration=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - Extended Sync=0D - //=0D - FALSE,=0D - //=0D - // support for PCI Express feature - Atomic Op=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - LTR=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - PTM=0D - //=0D - FALSE,=0D - //=0D - // support for PCI Express feature - Completion Timeout=0D - //=0D - TRUE,=0D - //=0D - // support for PCI Express feature - Clock Power Management=0D - //=0D - FALSE,=0D - //=0D - // support for PCI Express feature - L1 PM Substates=0D - //=0D - FALSE=0D -};=0D -=0D -//=0D -// indicates the driver has completed query to platform on the list of sup= ported=0D -// PCI features to be configured=0D -//=0D -BOOLEAN mPciExpressGetPlatformPolicyComplete =3D FALSE;=0D -=0D -//=0D -// PCI Express feature initialization phase handle routines=0D -//=0D -PCI_EXPRESS_FEATURE_INITIALIZATION_POINT mPciExpressFeatureInitialization= List[] =3D {=0D - {=0D - PciExpressFeatureSetupPhase, PciExpressCcc, SetupCommo= nClkCfg=0D - },=0D - {=0D - PciExpressFeatureEntendedSetupPhase, PciExpressCcc, ProgramCcc= =0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressCcc, EnforceCcc= =0D - },=0D - {=0D - PciExpressFeatureSetupPhase, PciExpressAspm, SetupAspm= =0D - },=0D - {=0D - PciExpressFeatureEntendedSetupPhase, PciExpressAspm, AlignAspm= =0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressAspm, ProgramAsp= m=0D - },=0D - {=0D - PciExpressFeatureSetupPhase, PciExpressMps, SetupMaxPa= yloadSize=0D - },=0D - {=0D - PciExpressFeatureEntendedSetupPhase, PciExpressMps, CasMaxPayl= oadSize=0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressMps, ProgramMax= PayloadSize=0D - },=0D - {=0D - PciExpressFeatureSetupPhase, PciExpressMrrs, SetupMaxRe= adReqSize=0D - },=0D - {=0D - PciExpressFeatureEntendedSetupPhase, PciExpressMrrs, Conditiona= lCasMaxReadReqSize=0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressMrrs, ProgramMax= ReadReqSize=0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressRelaxOrder, ProgramRel= axOrder=0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressNoSnoop, ProgramNoS= noop=0D - },=0D - {=0D - PciExpressFeatureSetupPhase, PciExpressCto, SetupCompl= etionTimeout=0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressCto, ProgramCom= pletionTimeout=0D - },=0D - {=0D - PciExpressFeatureSetupPhase, PciExpressAtomicOp, SetupAtomi= cOpRoutingSupport=0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressAtomicOp, ProgramAto= micOp=0D - },=0D - {=0D - PciExpressFeatureSetupPhase, PciExpressLtr, SetupLtr=0D - },=0D - {=0D - PciExpressFeatureEntendedSetupPhase, PciExpressLtr, ReSetupLtr= =0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressLtr, ProgramLtr= =0D - },=0D - {=0D - PciExpressFeatureSetupPhase, PciExpressExtTag, SetupExtTa= g=0D - },=0D - {=0D - PciExpressFeatureEntendedSetupPhase, PciExpressExtTag, AlignExtTa= g=0D - },=0D - {=0D - PciExpressFeatureProgramPhase, PciExpressExtTag, ProgramExt= Tag=0D - }=0D -};=0D -=0D -/**=0D - Routine to serially dispatch the designated the PCI Express feature spec= ific=0D - functions defined for each of the configuration phase. The order for eac= h phase=0D - would be based entirely on the table mPciExpressFeatureInitializationLis= t.=0D -=0D - @param PciDevice pointer to PCI_IO_DEVICE to iden= tify device=0D - @param PciExFeatureConfigPhase input configuration phase=0D - @param PciExpressFeatureConfiguration used pointer to void to accomoda= te any PCI=0D - Express feature specific data ty= pe=0D - @retval EFI_STATUS output only from feature specifi= c function=0D - defined in the table mPciExpress= FeatureInitializationList=0D -**/=0D -EFI_STATUS=0D -DispatchPciExpressInitializationFunctions (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciExFeatureConfigPhase,=0D - IN VOID *PciExpressFeatureConfigurat= ion=0D - )=0D -{=0D - UINTN idx;=0D - EFI_STATUS Status;=0D - UINT8 *PciExpressPolicy;=0D -=0D - for (=0D - idx =3D 0, PciExpressPolicy =3D (UINT8*)&mPciExpressPlatformPolicy=0D - ; idx < sizeof (mPciExpressFeatureInitializationList) / sizeof (PCI_= EXPRESS_FEATURE_INITIALIZATION_POINT)=0D - ; idx++=0D - ){=0D - if (=0D - //=0D - // match the configuration phase=0D - //=0D - mPciExpressFeatureInitializationList[idx].PciExpressFeatureConfigu= rationPhase =3D=3D PciExFeatureConfigPhase=0D - //=0D - // check whether the PCI Express features is enabled=0D - //=0D - && PciExpressPolicy[mPciExpressFeatureInitializationList[idx].PciE= xpressFeatureId] =3D=3D TRUE=0D - ) {=0D - Status =3D mPciExpressFeatureInitializationList[idx].PciExpressFeat= ureConfigurationRoutine (=0D - PciDevice,=0D - PciExpressFeat= ureConfiguration=0D - );=0D - }=0D - }=0D - return Status;=0D -}=0D -=0D -/**=0D - Main routine to indicate platform selection of any of the other PCI feat= ures=0D - to be configured by this driver=0D -=0D - @retval TRUE platform has selected the other PCI features to be confi= gured=0D - FALSE platform has not selected any of the other PCI features= =0D -**/=0D -BOOLEAN=0D -CheckPciExpressFeatureList (=0D - )=0D -{=0D - UINTN length;=0D - UINT8 *list;=0D -=0D - for (=0D - length =3D 0, list =3D (UINT8*)&mPciExpressPlatformPolicy=0D - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY)=0D - ; length++=0D - ) {=0D - if (list[length]) {=0D - return TRUE;=0D - }=0D - }=0D - return FALSE;=0D -}=0D -=0D -/**=0D - helper routine to wipe out the global PCI Express feature list=0D -**/=0D -VOID=0D -NegatePciExpressFeatureList (=0D - )=0D -{=0D - UINTN length;=0D - UINT8 *list;=0D -=0D - for (=0D - length =3D 0, list =3D (UINT8*)&mPciExpressPlatformPolicy=0D - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY)=0D - ; length++=0D - ) {=0D - if (list[length]) {=0D - list[length] =3D FALSE;=0D - }=0D - }=0D -}=0D -=0D -/**=0D - Main routine to indicate whether the PCI Express feature initialization = is=0D - required or not=0D -=0D - @retval TRUE PCI Express feature initialization required=0D - FALSE PCI Express feature not required=0D -**/=0D -BOOLEAN=0D -IsPciExpressFeatureConfigurationRequired (=0D - )=0D -{=0D - EFI_STATUS Status;=0D -=0D - if (mPciExpressGetPlatformPolicyComplete) {=0D - return CheckPciExpressFeatureList ();=0D - }=0D - //=0D - // initialize the PCI Express feature data members=0D - //=0D - InitializeListHead (&mRootBridgeDeviceList);=0D - //=0D - // check the platform to configure the PCI Express features=0D - //=0D - mPciExpressGetPlatformPolicyComplete =3D TRUE;=0D -=0D - Status =3D PciExpressPlatformGetPolicy ();=0D - if (EFI_ERROR (Status)) {=0D - //=0D - // fail to obtain the PCI Express feature configuration from platform,= =0D - // negate the list to avoid any unwanted configuration=0D - //=0D - NegatePciExpressFeatureList ();=0D - return FALSE;=0D - }=0D - //=0D - // PCI Express feature configuration list is ready from platform=0D - //=0D - return TRUE;=0D -}=0D -=0D -=0D -/**=0D - Indicates whether the set of PCI Express features selected by platform r= equires=0D - extended setup, that has additional resources that would be allocated to= align=0D - all the devices in the PCI tree, and free the resources later.=0D -=0D - @retval TRUE PCI Express feature requires extended setup=0D - FALSE PCI Express feature does not require extended setup=0D -**/=0D -BOOLEAN=0D -IsPciExpressFeatureExtendedSetupRequired (=0D - )=0D -{=0D - UINTN idx;=0D - UINT8 *PciExpressPolicy;=0D - //=0D - // return TRUE only for those features which are required to be aligned = with=0D - // common values among all the devices in the PCI tree=0D - //=0D - for (=0D - idx =3D 0, PciExpressPolicy =3D (UINT8*)&mPciExpressPlatformPolicy=0D - ; idx < sizeof (mPciExpressFeatureInitializationList) / sizeof (PCI_= EXPRESS_FEATURE_INITIALIZATION_POINT)=0D - ; idx++=0D - ){=0D - if (=0D - //=0D - // match the configuration phase to extended setup phase=0D - //=0D - mPciExpressFeatureInitializationList[idx].PciExpressFeatureConfigu= rationPhase =3D=3D PciExpressFeatureEntendedSetupPhase=0D - //=0D - // check whether the PCI Express features is enabled=0D - //=0D - && PciExpressPolicy[mPciExpressFeatureInitializationList[idx].PciE= xpressFeatureId] =3D=3D TRUE=0D - ) {=0D - return TRUE;=0D - } else if (=0D - //=0D - // the PCI Express feature does not require extended setup phase b= ut it=0D - // does require global flag to track the AtomicOpRouting caoabilit= y to=0D - // be tracked for all its bridge devices=0D - //=0D - idx =3D=3D PciExpressAtomicOp=0D - && PciExpressPolicy[idx] =3D=3D TRUE=0D - ) {=0D - return TRUE;=0D - }=0D - }=0D -=0D - return FALSE;=0D -}=0D -=0D -/**=0D - Helper routine to determine the existence of previously enumerated PCI de= vice=0D -=0D - @retval TRUE PCI device exist=0D - FALSE does not exist=0D -**/=0D -BOOLEAN=0D -DeviceExist (=0D - PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D - EFI_PCI_IO_PROTOCOL *PciIoProtocol =3D &PciDevice->PciIo;=0D - UINT16 VendorId =3D 0xFFFF;=0D -=0D - PciIoProtocol->Pci.Read (=0D - PciIoProtocol,=0D - EfiPciIoWidthUint16,=0D - PCI_VENDOR_ID_OFFSET,=0D - 1,=0D - &VendorId=0D - );=0D - if (VendorId =3D=3D 0 || VendorId =3D=3D 0xFFFF) {=0D - return FALSE;=0D - } else {=0D - return TRUE;=0D - }=0D -}=0D -=0D -/**=0D - Free up memory alloted for the primary physical PCI Root ports of the PC= I Root=0D - Bridge instance. Free up all the nodes of type BRIDGE_DEVICE_NODE.=0D -**/=0D -VOID=0D -DestroyRootBridgeDeviceNodes ()=0D -{=0D - LIST_ENTRY *Link;=0D - BRIDGE_DEVICE_NODE *Temp;=0D -=0D - Link =3D mRootBridgeDeviceList.ForwardLink;=0D - while (Link !=3D NULL && Link !=3D &mRootBridgeDeviceList) {=0D - Temp =3D ROOT_BRIDGE_DEVICE_NODE_FROM_LINK (Link);=0D - Link =3D RemoveEntryList (Link);=0D - FreePool (Temp->PciExFeaturesConfigurationTable);=0D - FreePool (Temp);=0D - }=0D -}=0D -=0D -/**=0D - Main routine to determine the child PCI devices of a PCI bridge device=0D - and group them under a common internal PCI features Configuration table.= =0D -=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.= =0D - @param PciFeaturesConfigTable A pointer to a pointer to the=0D - PCI_EXPRESS_FEATURES_CONFIGURATI= ON_TABLE.=0D - Returns NULL in case of RCiEP or= the PCI=0D - device does match with any of th= e physical=0D - Root ports, or it does not belon= g to any=0D - Root port's PCI bus range (not a= child)=0D -=0D - @retval EFI_SUCCESS able to determine the PCI featur= e=0D - configuration table. For RCiEP s= ince=0D - since it is not prepared.=0D - EFI_DEVICE_ERROR the PCI device has invalid EFI d= evice=0D - path=0D -**/=0D -EFI_STATUS=0D -GetPciExpressFeaturesConfigurationTable (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - OUT PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE **PciFeaturesConfigTable=0D - )=0D -{=0D - LIST_ENTRY *Link;=0D - BRIDGE_DEVICE_NODE *Temp;=0D - BOOLEAN NodeMatch;=0D - EFI_DEVICE_PATH_PROTOCOL *RootPortPath;=0D - EFI_DEVICE_PATH_PROTOCOL *PciDevicePath;=0D -=0D - if (IsListEmpty (&mRootBridgeDeviceList)) {=0D - //=0D - // no populated PCI primary root ports to parse and match the PCI feat= ures=0D - // configuration table=0D - //=0D - *PciFeaturesConfigTable =3D NULL;=0D - return EFI_SUCCESS;=0D - }=0D -=0D - //=0D - // The PCI features configuration table is not built for RCiEP, return N= ULL=0D - //=0D - if (PciDevice->PciExpressCapabilityStructure.Capability.Bits.DevicePortT= ype =3D=3D \=0D - PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) {=0D - *PciFeaturesConfigTable =3D NULL;=0D - return EFI_SUCCESS;=0D - }=0D -=0D - if (IsDevicePathEnd (PciDevice->DevicePath)){=0D - //=0D - // the given PCI device does not have a valid device path=0D - //=0D - *PciFeaturesConfigTable =3D NULL;=0D - return EFI_DEVICE_ERROR;=0D - }=0D -=0D -=0D - Link =3D mRootBridgeDeviceList.ForwardLink;=0D - do {=0D - Temp =3D ROOT_BRIDGE_DEVICE_NODE_FROM_LINK (Link);=0D - RootPortPath =3D Temp->RootBridgeDevicePath;=0D - PciDevicePath =3D PciDevice->DevicePath;=0D - NodeMatch =3D FALSE;=0D - //=0D - // match the device path from the list of primary Root Ports with the = given=0D - // device; the initial nodes matching in sequence indicate that the gi= ven PCI=0D - // device belongs to that PCI tree from the root port=0D - //=0D - if (IsDevicePathEnd (RootPortPath)) {=0D - //=0D - // critical error as no device path available in root=0D - //=0D - *PciFeaturesConfigTable =3D NULL;=0D - return EFI_DEVICE_ERROR;=0D - }=0D -=0D - if (EfiCompareDevicePath (RootPortPath, PciDevicePath)) {=0D - //=0D - // the given PCI device is the primary root port itself=0D - //=0D - *PciFeaturesConfigTable =3D Temp->PciExFeaturesConfigurationTable;=0D - return EFI_SUCCESS;=0D - }=0D - //=0D - // check this PCI device belongs to the primary root port of the root = bridge=0D - // any child PCI device will have the same initial device path nodes = as=0D - // its parent root port=0D - //=0D - while (!IsDevicePathEnd (RootPortPath)){=0D -=0D - if (DevicePathNodeLength (RootPortPath) !=3D DevicePathNodeLength (P= ciDevicePath)) {=0D - //=0D - // break to check the next primary root port nodes as does not mat= ch=0D - //=0D - NodeMatch =3D FALSE;=0D - break;=0D - }=0D - if (CompareMem (RootPortPath, PciDevicePath, DevicePathNodeLength (R= ootPortPath)) !=3D 0) {=0D - //=0D - // node does not match, break to check next node=0D - //=0D - NodeMatch =3D FALSE;=0D - break;=0D - }=0D - NodeMatch =3D TRUE;=0D - //=0D - // advance to next node=0D - //=0D - RootPortPath =3D NextDevicePathNode (RootPortPath);=0D - PciDevicePath =3D NextDevicePathNode (PciDevicePath);=0D - }=0D -=0D - if (NodeMatch =3D=3D TRUE) {=0D - //=0D - // device belongs to primary root port, return its PCI feature confi= guration=0D - // table=0D - //=0D - *PciFeaturesConfigTable =3D Temp->PciExFeaturesConfigurationTable;=0D - return EFI_SUCCESS;=0D - }=0D -=0D - //=0D - // advance to next Root port node=0D - //=0D - Link =3D Link->ForwardLink;=0D - } while (Link !=3D &mRootBridgeDeviceList && Link !=3D NULL);=0D - //=0D - // the PCI device must be RCiEP, does not belong to any primary root por= t=0D - //=0D - *PciFeaturesConfigTable =3D NULL;=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - helper routine to dump the PCIe Device Port Type=0D -**/=0D -VOID=0D -DumpDevicePortType (=0D - IN UINT8 DevicePortType=0D - )=0D -{=0D - switch (DevicePortType){=0D - case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT:=0D - DEBUG (( DEBUG_INFO, "PCIe endpoint found\n"));=0D - break;=0D - case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT:=0D - DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n"));=0D - break;=0D - case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:=0D - DEBUG (( DEBUG_INFO, "PCIe Root Port found\n"));=0D - break;=0D - case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT:=0D - DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n"));=0D - break;=0D - case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:=0D - DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n"));=0D - break;=0D - case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE:=0D - DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n"));=0D - break;=0D - case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE:=0D - DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n"));=0D - break;=0D - case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT:=0D - DEBUG (( DEBUG_INFO, "RCiEP found\n"));=0D - break;=0D - case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR:=0D - DEBUG (( DEBUG_INFO, "RC Event Collector found\n"));=0D - break;=0D - }=0D -}=0D -=0D -/**=0D - Setup each PCI device as per the pltaform's device-specific policy, in = accordance=0D - with PCI Express Base specification.=0D -=0D - @param RootBridge A pointer to the PCI_IO_DEVICE.=0D -=0D - @retval EFI_SUCCESS processing each PCI feature as per policy = defined=0D - was successful.=0D - **/=0D -EFI_STATUS=0D -SetupDevicePciExpressFeatures (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase=0D - )=0D -{=0D - EFI_STATUS Status;=0D - PCI_REG_PCIE_CAPABILITY PcieCap;=0D - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressFeaturesConfigTable= ;=0D -=0D - PciExpressFeaturesConfigTable =3D NULL;=0D - Status =3D GetPciExpressFeaturesConfigurationTable (PciDevice, &PciExpre= ssFeaturesConfigTable);=0D -=0D - if (PciConfigPhase =3D=3D PciExpressFeatureSetupPhase) {=0D - DEBUG_CODE (=0D - if (EFI_ERROR( Status)) {=0D - DEBUG ((=0D - DEBUG_WARN,=0D - "[Cfg group: 0 {error in dev path}]"=0D - ));=0D - } else if (PciExpressFeaturesConfigTable =3D=3D NULL) {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "[Cfg group: 0]"=0D - ));=0D - } else {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "[Cfg group: %d]",=0D - PciExpressFeaturesConfigTable->ID=0D - ));=0D - }=0D - PcieCap.Uint16 =3D PciDevice->PciExpressCapabilityStructure.Capabili= ty.Uint16;=0D - DumpDevicePortType ((UINT8)PcieCap.Bits.DevicePortType);=0D - );=0D -=0D - //=0D - // get the device-specific platform policy for the PCI Express feature= s=0D - //=0D - Status =3D PciExpressPlatformGetDevicePolicy (PciDevice);=0D - if (EFI_ERROR(Status)) {=0D - DEBUG ((=0D - DEBUG_ERROR,=0D - "Error in obtaining PCI device policy!!!\n"=0D - ));=0D - }=0D - }=0D -=0D - DEBUG ((DEBUG_INFO, "["));=0D -=0D - Status =3D DispatchPciExpressInitializationFunctions (=0D - PciDevice,=0D - PciConfigPhase,=0D - PciExpressFeaturesConfigTable=0D - );=0D -=0D - DEBUG ((DEBUG_INFO, "]\n"));=0D - return Status;=0D -}=0D -=0D -/**=0D - Create and append a node of type BRIDGE_DEVICE_NODE in the list for the = primary=0D - Root Port so that all its child PCI devices can be identified against th= e PCI=0D - features configuration table group ID, of type PCI_EXPRESS_FEATURES_CONF= IGURATION_TABLE.=0D -=0D - @param BridgePort A pointer to the PCI_IO_DEVICE=0D - @param PortNumber A UINTN value to identify the PCI feature configura= tion=0D - table group=0D -=0D - @retval EFI_SUCCESS success in adding a node of BRIDGE_DEVICE_= NODE=0D - to the list=0D - EFI_OUT_OF_RESOURCES unable to get memory for creating the node= =0D -**/=0D -EFI_STATUS=0D -CreatePciRootBridgeDeviceNode (=0D - IN PCI_IO_DEVICE *BridgePort,=0D - IN UINTN PortNumber=0D - )=0D -{=0D - BRIDGE_DEVICE_NODE *RootBridgeNode =3D NULL;=0D - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciConfigTable =3D NULL;=0D -=0D - RootBridgeNode =3D AllocateZeroPool (sizeof (BRIDGE_DEVICE_NODE));=0D - if (RootBridgeNode =3D=3D NULL) {=0D - return EFI_OUT_OF_RESOURCES;=0D - }=0D - RootBridgeNode->Signature =3D PCI_ROOT_BRIDGE_DEVICE= _SIGNATURE;=0D - RootBridgeNode->RootBridgeDevicePath =3D BridgePort->DevicePath= ;=0D - PciConfigTable =3D AllocateZeroPool (=0D - sizeof (PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE)=0D - );=0D - if (PciConfigTable) {=0D - PciConfigTable->ID =3D PortNumber;=0D - //=0D - // start by assuming 4096B as the default value for the Max. Payload S= ize=0D - //=0D - PciConfigTable->Max_Payload_Size =3D PCIE_MAX_PAYLOAD_SIZE_= 4096B;=0D - //=0D - // start by assuming 4096B as the default value for the Max. Read Requ= est Size=0D - //=0D - PciConfigTable->Max_Read_Request_Size =3D PCIE_MAX_READ_REQ_SIZE= _4096B;=0D - //=0D - // start by assuming the Max. Read Request Size need not be common for= all=0D - // the devices in the PCI tree=0D - //=0D - PciConfigTable->Lock_Max_Read_Request_Size =3D FALSE;=0D - //=0D - // start by assuming the LTR mechanism is supported in a PCI tree=0D - //=0D - PciConfigTable->LtrSupported =3D TRUE;=0D - //=0D - // the default LTR mechanism is disabled as per the PCI Base specifica= tion=0D - //=0D - PciConfigTable->LtrEnable =3D FALSE;=0D - //=0D - // start by assuming the AtomicOp Routing capability is supported in t= he PCI=0D - // tree=0D - //=0D - PciConfigTable->AtomicOpRoutingSupported =3D TRUE;=0D - //=0D - // start by assuming the Extended Tag is 10b Requester capable=0D - //=0D - PciConfigTable->ExtendedTag =3D EFI_PCI_EXPRESS_EXTEND= ED_TAG_10BIT;=0D - //=0D - // initial state set to ASPM L0s and L1 both=0D - //=0D - PciConfigTable->AspmSupport =3D EFI_PCI_EXPRESS_ASPM_L= 0S_L1_SUPPORT;=0D - //=0D - // start by assuming less than 64ns of L0s Exit Latency=0D - //=0D - PciConfigTable->L0sExitLatency =3D PCIE_LINK_CAPABILITY_L= 0S_EXIT_LATENCY_64NS;=0D - //=0D - // start by assuming less than 1us of L1 Exit Latency=0D - //=0D - PciConfigTable->L1ExitLatency =3D PCIE_LINK_CAPABILITY_L= 1_EXIT_LATENCY_1US;=0D - //=0D - // default link retrain is not required=0D - //=0D - PciConfigTable->LinkReTrain =3D FALSE;=0D - //=0D - // start by assuming no common clock configuration mode for the device= 's link=0D - //=0D - PciConfigTable->CommonClockConfiguration =3D FALSE;=0D - }=0D -=0D - RootBridgeNode->PciExFeaturesConfigurationTable =3D PciConfigTable;=0D -=0D - InsertTailList (&mRootBridgeDeviceList, &RootBridgeNode->NextRootBridgeD= evice);=0D -=0D - if (PciConfigTable =3D=3D NULL) {=0D - return EFI_OUT_OF_RESOURCES;=0D - }=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Scan all the nodes of the RootBridge to identify and create a separate l= ist=0D - of all primary physical PCI root ports and link each with its own instan= ce of=0D - the PCI Feature Configuration Table.=0D -=0D - @param RootBridge A pointer to the PCI_IO_DEVICE of the PCI Root Bri= dge=0D -=0D - @retval EFI_OUT_OF_RESOURCES unable to allocate buffer to store PCI fea= ture=0D - configuration table for all the physical P= CI root=0D - ports given=0D - EFI_NOT_FOUND No PCI Bridge device found=0D - EFI_SUCCESS PCI Feature COnfiguration table created fo= r all=0D - the PCI Rooot ports found=0D - EFI_INVALID_PARAMETER invalid parameter passed to the routine wh= ich=0D - creates the PCI controller node for the pr= imary=0D - Root post list=0D -**/=0D -EFI_STATUS=0D -CreatePciRootBridgeDeviceList (=0D - IN PCI_IO_DEVICE *RootBridge=0D - )=0D -{=0D - EFI_STATUS Status =3D EFI_NOT_FOUND;=0D - LIST_ENTRY *Link;=0D - PCI_IO_DEVICE *Device;=0D - UINTN BridgeDeviceCount;=0D -=0D - BridgeDeviceCount =3D 0;=0D - for ( Link =3D RootBridge->ChildList.ForwardLink=0D - ; Link !=3D &RootBridge->ChildList=0D - ; Link =3D Link->ForwardLink=0D - ) {=0D - Device =3D PCI_IO_DEVICE_FROM_LINK (Link);=0D - if (!DeviceExist (Device)) {=0D - continue;=0D - }=0D - if (IS_PCI_BRIDGE (&Device->Pci)) {=0D - BridgeDeviceCount++;=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "#%d ::Bridge [%02x|%02x|%02x]",=0D - BridgeDeviceCount, Device->BusNumber, Device->DeviceNumber, Device= ->FunctionNumber=0D - ));=0D - //=0D - // create a list of bridge devices if that is connected to any other= device=0D - //=0D - if (!IsListEmpty (&Device->ChildList)) {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "- has downstream device!\n"=0D - ));=0D - Status =3D CreatePciRootBridgeDeviceNode (Device, BridgeDeviceCoun= t);=0D - if (EFI_ERROR (Status)) {=0D - DEBUG ((=0D - DEBUG_ERROR,=0D - "PCI configuration table allocation failure for #%d ::Bridge [= %02x|%02x|%02x]\n",=0D - BridgeDeviceCount, Device->BusNumber, Device->DeviceNumber, De= vice->FunctionNumber=0D - ));=0D - }=0D - } else {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "- no downstream device!\n"=0D - ));=0D - }=0D - }=0D - }=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - Initialize the device's PCI Express features, in a staged manner=0D - @param PciDevice A pointer to the PCI_IO_DEVICE.=0D -=0D - @retval EFI_SUCCESS initializing all the nodes of the root bri= dge=0D - instances were successfull.=0D -**/=0D -EFI_STATUS=0D -InitializeDevicePciExpressFeatures (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase=0D - )=0D -{=0D - EFI_STATUS Status;=0D -=0D - switch (PciConfigPhase) {=0D - case PciExpressFeatureSetupPhase:=0D - case PciExpressFeatureEntendedSetupPhase:=0D - case PciExpressFeatureProgramPhase:=0D - Status =3D SetupDevicePciExpressFeatures (PciDevice, PciConfigPhase)= ;=0D - break;=0D - case PciExpressFeatureEndPhase:=0D - Status =3D PciExpressPlatformNotifyDeviceState (PciDevice);=0D - break;=0D - }=0D - return Status;=0D -}=0D -=0D -/**=0D - Traverse all the nodes from the root bridge or PCI-PCI bridge instance, = to=0D - configure the PCI Express features as per the PCI Express Base Secificat= ion=0D - by considering its device-specific platform policy, and its device capab= ility,=0D - as applicable.=0D -=0D - @param RootBridge A pointer to the PCI_IO_DEVICE.=0D -=0D - @retval EFI_SUCCESS Traversing all the nodes of the root bridg= e=0D - instances were successfull.=0D -**/=0D -EFI_STATUS=0D -InitializePciExpressFeatures (=0D - IN PCI_IO_DEVICE *RootBridge,=0D - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase=0D - )=0D -{=0D - EFI_STATUS Status;=0D - LIST_ENTRY *Link;=0D - PCI_IO_DEVICE *Device;=0D -=0D - for ( Link =3D RootBridge->ChildList.ForwardLink=0D - ; Link !=3D &RootBridge->ChildList=0D - ; Link =3D Link->ForwardLink=0D - ) {=0D - Device =3D PCI_IO_DEVICE_FROM_LINK (Link);=0D - if (!DeviceExist (Device)) {=0D - DEBUG ((=0D - DEBUG_ERROR,=0D - "::Device [%02x|%02x|%02x] - does not exist!!!\n",=0D - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber=0D - ));=0D - continue;=0D - }=0D - if (IS_PCI_BRIDGE (&Device->Pci)) {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "::Bridge [%02x|%02x|%02x] -",=0D - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber=0D - ));=0D - if (Device->IsPciExp) {=0D - Status =3D InitializeDevicePciExpressFeatures (=0D - Device,=0D - PciConfigPhase=0D - );=0D - } else {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "Not a PCIe capable device!\n"=0D - ));=0D - //=0D - // PCI Bridge which does not have PCI Express Capability structure= =0D - // cannot process this kind of PCI Bridge device=0D - //=0D - }=0D -=0D - InitializePciExpressFeatures (Device, PciConfigPhase);=0D - } else {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "::Device [%02x|%02x|%02x] -",=0D - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber=0D - ));=0D - if (Device->IsPciExp) {=0D - Status =3D InitializeDevicePciExpressFeatures (=0D - Device,=0D - PciConfigPhase=0D - );=0D - } else {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "Not a PCIe capable device!\n"=0D - ));=0D - //=0D - // PCI Device which does not have PCI Express Capability structure= =0D - // cannot process this kind of PCI device=0D - //=0D - }=0D - }=0D - }=0D -=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge, = to=0D - configure the other PCI features.=0D -=0D - @param RootBridge A pointer to the PCI_IO_DEVICE.=0D -=0D - @retval EFI_SUCCESS The other PCI features configuration durin= g enumeration=0D - of all the nodes of the PCI root bridge in= stance were=0D - programmed in PCI-compliance pattern along= with the=0D - device-specific policy, as applicable.=0D - @retval EFI_UNSUPPORTED One of the override operation maong the no= des of=0D - the PCI hierarchy resulted in a incompatib= le address=0D - range.=0D - @retval EFI_INVALID_PARAMETER The override operation is performed with i= nvalid input=0D - parameters.=0D -**/=0D -EFI_STATUS=0D -EnumeratePciExpressFeatures (=0D - IN EFI_HANDLE Controller,=0D - IN PCI_IO_DEVICE *RootBridge=0D - )=0D -{=0D - EFI_STATUS Status;=0D - UINTN PciExpressFeatureConfigPhase;=0D -=0D - if (!IsPciExpressFeatureConfigurationRequired ()) {=0D - //=0D - // exit as agreement is not reached with platform to configure the PCI= =0D - // Express features=0D - //=0D - return EFI_SUCCESS;=0D - }=0D - mRootBridgeHandle =3D Controller;=0D -=0D - DEBUG_CODE (=0D - CHAR16 *Str;=0D - Str =3D ConvertDevicePathToText (=0D - DevicePathFromHandle (RootBridge->Handle),=0D - FALSE,=0D - FALSE=0D - );=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "Enumerating PCI features for Root Bridge %s\n",=0D - Str !=3D NULL ? Str : L""=0D - ));=0D -=0D - if (Str !=3D NULL) {=0D - FreePool (Str);=0D - }=0D - );=0D -=0D - for ( PciExpressFeatureConfigPhase =3D PciExpressFeaturePreProcessPhase= =0D - ; PciExpressFeatureConfigPhase <=3D PciExpressFeatureEndPhase=0D - ; PciExpressFeatureConfigPhase++=0D - ) {=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "<<********** Phase [%d]**********>>\n",=0D - PciExpressFeatureConfigPhase=0D - ));=0D - if (PciExpressFeatureConfigPhase =3D=3D PciExpressFeaturePreProcessPha= se) {=0D - //=0D - // create a list of root bridge devices (root ports) of the root com= plex=0D - // if extra setup phase required=0D - //=0D - if (IsPciExpressFeatureExtendedSetupRequired ()) {=0D - CreatePciRootBridgeDeviceList (RootBridge);=0D - }=0D - continue;=0D - }=0D - if (PciExpressFeatureConfigPhase =3D=3D PciExpressFeatureEntendedSetup= Phase) {=0D - if (!IsPciExpressFeatureExtendedSetupRequired ()) {=0D - //=0D - // since the PCI Express features require no extra initialization = steps=0D - // skip this phase=0D - //=0D - continue;=0D - }=0D - }=0D - //=0D - // setup the PCI Express features=0D - //=0D - Status =3D InitializePciExpressFeatures (RootBridge, PciExpressFeature= ConfigPhase);=0D -=0D - if (PciExpressFeatureConfigPhase =3D=3D PciExpressFeatureEndPhase) {=0D - //=0D - // clean up the temporary resource nodes created for this root bridg= e=0D - //=0D - if (IsPciExpressFeatureExtendedSetupRequired ()) {=0D - DestroyRootBridgeDeviceNodes ();=0D - }=0D - }=0D - }=0D -=0D - return Status;=0D -}=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h deleted file mode 100644 index 481bd90..0000000 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ /dev/null @@ -1,304 +0,0 @@ -/** @file=0D - PCI standard feature support functions implementation for PCI Bus module= ..=0D -=0D -Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#ifndef _EFI_PCI_FEATURES_SUPPORT_H_=0D -#define _EFI_PCI_FEATURES_SUPPORT_H_=0D -=0D -extern EFI_HANDLE mRootBridgeHandle;=0D -extern EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPlatformPol= icy;=0D -//=0D -// defines the data structure to hold the details of the PCI Root port dev= ices=0D -//=0D -typedef struct _BRIDGE_DEVICE_NODE BRIDGE_DEVICE_NODE;=0D -=0D -//=0D -// defines the data structure to hold the configuration data for the other= PCI=0D -// features=0D -//=0D -typedef struct _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE PCI_EXPRESS_FEAT= URES_CONFIGURATION_TABLE;=0D -=0D -//=0D -// define the data type for the PCI feature policy support=0D -//=0D -typedef struct _PCI_FEATURE_POLICY PCI_FEATURE_POLICY;=0D -=0D -//=0D -// Signature value for the PCI Root Port node=0D -//=0D -#define PCI_ROOT_BRIDGE_DEVICE_SIGNATURE SIGNATURE_32 ('p', = 'c', 'i', 'p')=0D -=0D -//=0D -// Definitions of the PCI Root Port data structure members=0D -//=0D -struct _BRIDGE_DEVICE_NODE {=0D - //=0D - // Signature header=0D - //=0D - UINT32 Signature;=0D - //=0D - // linked list pointers to next node=0D - //=0D - LIST_ENTRY NextRootBridgeDevice;=0D - //=0D - // pointer to PCI_IO_DEVICE of the primary PCI Controller device=0D - //=0D - EFI_DEVICE_PATH_PROTOCOL *RootBridgeDevicePath;=0D - //=0D - // pointer to the corresponding PCI Express feature configuration Table = node=0D - // all the child PCI devices of the controller are aligned based on this= table=0D - //=0D - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeaturesConfigurationTab= le;=0D -};=0D -=0D -#define ROOT_BRIDGE_DEVICE_NODE_FROM_LINK(a) \=0D - CR (a, BRIDGE_DEVICE_NODE, NextRootBridgeDevice, PCI_ROOT_BRIDGE_DEVICE_= SIGNATURE)=0D -=0D -//=0D -// Definition of the PCI Feature configuration Table members=0D -//=0D -struct _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE {=0D - //=0D - // Configuration Table ID=0D - //=0D - UINTN ID;=0D - //=0D - // to configure the PCI feature Maximum payload size to maintain the dat= a packet=0D - // size among all the PCI devices in the PCI hierarchy=0D - //=0D - UINT8 Max_Payload_Size;=0D - //=0D - // to configure the PCI feature maximum read request size to maintain th= e memory=0D - // requester size among all the PCI devices in the PCI hierarchy=0D - //=0D - UINT8 Max_Read_Request_Size;=0D - //=0D - // lock the Max_Read_Request_Size for the entire PCI tree of a root port= =0D - //=0D - BOOLEAN Lock_Max_Read_Request_Size;=0D - //=0D - // to record the adversity in LTR mechanism support capability among the= PCI=0D - // device of an heirarchy=0D - //=0D - BOOLEAN LtrSupported;=0D - //=0D - // to enable the LTR mechansim for the entire PCI tree from a root port= =0D - //=0D - BOOLEAN LtrEnable;=0D - //=0D - // to record the AtomicOp Routing capability of the PCI Heirarchy to ena= ble=0D - // the AtomicOp of the EP device=0D - //=0D - BOOLEAN AtomicOpRoutingSupported;=0D - //=0D - // to configure a common extended tag size for all the childs of a root = port=0D - //=0D - UINT8 ExtendedTag;=0D - //=0D - // to configure common ASPM state for all the devices link=0D - //=0D - UINT8 AspmSupport;=0D - //=0D - // to record maximum L0s Exit Latency among all the devices starting fro= m root=0D - // bridge device to its downstream bridge and its endpoint device=0D - //=0D - UINT8 L0sExitLatency;=0D - //=0D - // to record maximum L1 Exit Latency among all the devices starting from= root=0D - // bridge device to its downstream bridge and its endpoint device=0D - //=0D - UINT8 L1ExitLatency;=0D - //=0D - // flag to indicate the link training is required in the devices of down= stream=0D - // ports=0D - //=0D - BOOLEAN LinkReTrain;=0D - //=0D - // link status slot clock configuration=0D - //=0D - BOOLEAN CommonClockConfiguration;=0D -};=0D -=0D -//=0D -// Declaration of the internal sub-phases during enumeration to configure = the PCI=0D -// Express features=0D -//=0D -typedef enum {=0D - //=0D - // preprocessing applicable only to few PCI Express features to bind all= devices=0D - // under the common root bridge device (root port), that would be useful= to align=0D - // all devices with a common value. This would be optional phase based o= n the=0D - // type of the PCI Express feature to be programmed based on platform po= licy=0D - //=0D - PciExpressFeaturePreProcessPhase,=0D -=0D - //=0D - // mandatory phase to setup the PCI Express feature to its applicable at= tribute,=0D - // based on its device-specific platform policies, matching with its dev= ice capabilities=0D - //=0D - PciExpressFeatureSetupPhase,=0D -=0D - //=0D - // optional phase primarily to align all devices, specially required whe= n PCI=0D - // switch is present in the hierarchy, applicable to certain few PCI Exp= ress=0D - // features only=0D - //=0D - PciExpressFeatureEntendedSetupPhase,=0D -=0D - //=0D - // mandatory programming phase to complete the configuration of the PCI = Express=0D - // features=0D - //=0D - PciExpressFeatureProgramPhase,=0D -=0D - //=0D - // optional phase to clean up temporary buffers, like those that were pr= epared=0D - // during the preprocessing phase above=0D - //=0D - PciExpressFeatureEndPhase=0D -=0D -}PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE;=0D -=0D -//=0D -// declaration for the data type to harbor the PCI feature policies=0D -//=0D -struct _PCI_FEATURE_POLICY {=0D - //=0D - // if set, it indicates the feature should be enabled=0D - // if clear, it indicates the feature should be disabled=0D - //=0D - UINT8 Act : 1;=0D - //=0D - // this field will be specific to feature, it can be implementation spec= ific=0D - // or it can be reserved and remain unused=0D - //=0D - UINT8 Support : 6;=0D - //=0D - // if set indicates override the feature policy defined by the members a= bove=0D - // if clear it indicates that this feature policy should be ignored comp= letely=0D - // this means the above two members should not be used=0D - //=0D - UINT8 Override : 1;=0D -};=0D -=0D -//=0D -// Declaration of the PCI Express features unique Id=0D -//=0D -typedef enum {=0D - //=0D - // support for PCI Express feature - Max. Payload Size=0D - //=0D - PciExpressMps,=0D - //=0D - // support for PCI Express feature - Max. Read Request Size=0D - //=0D - PciExpressMrrs,=0D - //=0D - // support for PCI Express feature - Extended Tag=0D - //=0D - PciExpressExtTag,=0D - //=0D - // support for PCI Express feature - Relax Order=0D - //=0D - PciExpressRelaxOrder,=0D - //=0D - // support for PCI Express feature - No-Snoop=0D - //=0D - PciExpressNoSnoop,=0D - //=0D - // support for PCI Express feature - ASPM state=0D - //=0D - PciExpressAspm,=0D - //=0D - // support for PCI Express feature - Common Clock Configuration=0D - //=0D - PciExpressCcc,=0D - //=0D - // support for PCI Express feature - Extended Sync=0D - //=0D - PciExpressExtSync,=0D - //=0D - // support for PCI Express feature - Atomic Op=0D - //=0D - PciExpressAtomicOp,=0D - //=0D - // support for PCI Express feature - LTR=0D - //=0D - PciExpressLtr,=0D - //=0D - // support for PCI Express feature - PTM=0D - //=0D - PciExpressPtm,=0D - //=0D - // support for PCI Express feature - Completion Timeout=0D - //=0D - PciExpressCto,=0D - //=0D - // support for PCI Express feature - Clock Power Management=0D - //=0D - PciExpressCpm,=0D - //=0D - // support for PCI Express feature - L1 PM Substates=0D - //=0D - PciExpressL1PmSubstates=0D -=0D -} PCI_EXPRESS_FEATURE_ID;=0D -=0D -//=0D -// PCI Express feature configuration routine during initialization phases= =0D -//=0D -typedef=0D -EFI_STATUS=0D -(*PCI_EXPRESS_FEATURE_CONFIGURATION_ROUTINE) (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN VOID *PciExpressFeatureConfigurat= ion=0D - );=0D -=0D -//=0D -// data type for the PCI Express feature initialization phases=0D -//=0D -typedef struct {=0D - //=0D - // Pci Express feature configuration phase=0D - //=0D - PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciExpressFeatureConfiguration= Phase;=0D - //=0D - // PCI Express feature Id=0D - //=0D - PCI_EXPRESS_FEATURE_ID PciExpressFeatureId;=0D - //=0D - // PCI Express feature configuration routine=0D - //=0D - PCI_EXPRESS_FEATURE_CONFIGURATION_ROUTINE PciExpressFeatureConfiguration= Routine;=0D -=0D -}PCI_EXPRESS_FEATURE_INITIALIZATION_POINT;=0D -=0D -=0D -=0D -/**=0D - Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge, = to=0D - configure the other PCI features.=0D -=0D - @param RootBridge A pointer to the PCI_IO_DEVICE.=0D -=0D - @retval EFI_SUCCESS The other PCI features configuration durin= g enumeration=0D - of all the nodes of the PCI root bridge in= stance were=0D - programmed in PCI-compliance pattern along= with the=0D - device-specific policy, as applicable.=0D - @retval EFI_UNSUPPORTED One of the override operation maong the no= des of=0D - the PCI hierarchy resulted in a incompatib= le address=0D - range.=0D - @retval EFI_INVALID_PARAMETER The override operation is performed with i= nvalid input=0D - parameters.=0D -**/=0D -EFI_STATUS=0D -EnumeratePciExpressFeatures (=0D - IN EFI_HANDLE Controller,=0D - IN PCI_IO_DEVICE *RootBridge=0D - );=0D -=0D -#endif=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c deleted file mode 100644 index bf380ab..0000000 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ /dev/null @@ -1,902 +0,0 @@ -/** @file=0D - This file encapsulate the usage of PCI Platform Protocol=0D -=0D - This file define the necessary hooks used to obtain the platform=0D - level data and policies which could be used in the PCI Enumeration phase= s=0D -=0D -Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include "PciBus.h"=0D -=0D -=0D -EFI_PCI_EXPRESS_PLATFORM_PROTOCOL *mPciExPlatformProtocol;=0D -EFI_PCI_EXPRESS_OVERRIDE_PROTOCOL *mPciExOverrideProtocol;=0D -=0D -=0D -/**=0D - This function retrieves the PCI Express Platform Protocols published by = platform=0D - @retval EFI_STATUS direct return status from the LocateProtocol= ()=0D - boot service for the PCI Express Override Pr= otocol=0D - EFI_SUCCESS The PCI Express Platform Protocol is found=0D -**/=0D -EFI_STATUS=0D -GetPciExpressProtocol (=0D - )=0D -{=0D - EFI_STATUS Status;=0D -=0D - if (mPciExPlatformProtocol) {=0D - //=0D - // the PCI Express Platform Protocol is already initialized=0D - //=0D - return EFI_SUCCESS;=0D - }=0D - if (mPciExOverrideProtocol) {=0D - //=0D - // the PCI Express Override Protocol is already initialized=0D - //=0D - return EFI_SUCCESS;=0D - }=0D - //=0D - // locate the PCI Express Platform Protocol=0D - //=0D - Status =3D gBS->LocateProtocol (=0D - &gEfiPciExpressPlatformProtocolGuid,=0D - NULL,=0D - (VOID **) &mPciExPlatformProtocol=0D - );=0D - if (!EFI_ERROR (Status)) {=0D - return Status;=0D - }=0D - //=0D - // If PCI Express Platform protocol doesn't exist, try to get the Pci Ex= press=0D - // Override Protocol.=0D - //=0D - return gBS->LocateProtocol (=0D - &gEfiPciExpressOverrideProtocolGuid,=0D - NULL,=0D - (VOID **) &mPciExOverrideProtocol=0D - );=0D -}=0D -=0D -/**=0D - This function indicates that the platform has published the PCI Express = Platform=0D - Protocol (or PCI Express Override Protocol) to indicate that this driver= can=0D - initialize the PCI Express features.=0D - @retval TRUE or FALSE=0D -**/=0D -BOOLEAN=0D -IsPciExpressProtocolPresent (=0D - )=0D -{=0D - if (=0D - mPciExPlatformProtocol =3D=3D NULL=0D - && mPciExOverrideProtocol =3D=3D NULL=0D - ) {=0D - return FALSE;=0D - }=0D - return TRUE;=0D -}=0D -=0D -/**=0D - Routine to translate the given device-specific platform policy from type= =0D - EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base S= pecification=0D - Revision 4.0; for the PCI feature Max_Payload_Size.=0D -=0D - @param MPS Input device-specific policy should be in terms of type= =0D - EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE=0D -=0D - @retval Range values for the Max_Payload_Size as defined in the = PCI=0D - Base Specification 4.0=0D -**/=0D -UINT8=0D -SetDevicePolicyPciExpressMps (=0D - IN UINT8 MPS=0D -)=0D -{=0D - switch (MPS) {=0D - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_128B:=0D - return PCIE_MAX_PAYLOAD_SIZE_128B;=0D - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_256B:=0D - return PCIE_MAX_PAYLOAD_SIZE_256B;=0D - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_512B:=0D - return PCIE_MAX_PAYLOAD_SIZE_512B;=0D - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_1024B:=0D - return PCIE_MAX_PAYLOAD_SIZE_1024B;=0D - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_2048B:=0D - return PCIE_MAX_PAYLOAD_SIZE_2048B;=0D - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_4096B:=0D - return PCIE_MAX_PAYLOAD_SIZE_4096B;=0D - default:=0D - return PCIE_MAX_PAYLOAD_SIZE_128B;=0D - }=0D -}=0D -=0D -/**=0D - Routine to translate the given device-specific platform policy from type= =0D - EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Base = Specification=0D - Revision 4.0; for the PCI feature Max_Read_Req_Size.=0D -=0D - @param MRRS Input device-specific policy should be in terms of type= =0D - EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE=0D -=0D - @retval Range values for the Max_Read_Req_Size as defined in the= PCI=0D - Base Specification 4.0=0D -**/=0D -UINT8=0D -SetDevicePolicyPciExpressMrrs (=0D - IN UINT8 MRRS=0D -)=0D -{=0D - switch (MRRS) {=0D - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_128B:=0D - return PCIE_MAX_READ_REQ_SIZE_128B;=0D - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_256B:=0D - return PCIE_MAX_READ_REQ_SIZE_256B;=0D - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_512B:=0D - return PCIE_MAX_READ_REQ_SIZE_512B;=0D - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_1024B:=0D - return PCIE_MAX_READ_REQ_SIZE_1024B;=0D - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_2048B:=0D - return PCIE_MAX_READ_REQ_SIZE_2048B;=0D - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_4096B:=0D - return PCIE_MAX_READ_REQ_SIZE_4096B;=0D - default:=0D - return PCIE_MAX_READ_REQ_SIZE_128B;=0D - }=0D -}=0D -=0D -/**=0D - Routine to set the device-specific policy for the PCI feature Relax Orde= ring=0D -=0D - @param RelaxOrder value corresponding to data type EFI_PCI_EXPRESS_R= ELAX_ORDER=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D -**/=0D -VOID=0D -SetDevicePolicyPciExpressRo (=0D - IN EFI_PCI_EXPRESS_RELAX_ORDER RelaxOrder,=0D - OUT PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D - //=0D - // implementation specific rules for the usage of PCI_FEATURE_POLICY mem= bers=0D - // exclusively for the PCI Feature Relax Ordering (RO)=0D - //=0D - // .Override =3D 0 to skip this PCI feature RO for the PCI device=0D - // .Override =3D 1 to program this RO PCI feature=0D - // .Act =3D 1 to enable the RO in the PCI device=0D - // .Act =3D 0 to disable the RO in the PCI device=0D - //=0D - switch (RelaxOrder) {=0D - case EFI_PCI_EXPRESS_RO_AUTO:=0D - PciDevice->SetupRO.Override =3D 0;=0D - break;=0D - case EFI_PCI_EXPRESS_RO_DISABLE:=0D - PciDevice->SetupRO.Override =3D 1;=0D - PciDevice->SetupRO.Act =3D 0;=0D - break;=0D - case EFI_PCI_EXPRESS_RO_ENABLE:=0D - PciDevice->SetupRO.Override =3D 1;=0D - PciDevice->SetupRO.Act =3D 1;=0D - break;=0D - default:=0D - PciDevice->SetupRO.Override =3D 0;=0D - break;=0D - }=0D -}=0D -=0D -/**=0D - Routine to set the device-specific policy for the PCI feature No-Snoop e= nable=0D - or disable=0D -=0D - @param NoSnoop value corresponding to data type EFI_PCI_EXPRESS_N= O_SNOOP=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D -**/=0D -VOID=0D -SetDevicePolicyPciExpressNs (=0D - IN EFI_PCI_EXPRESS_NO_SNOOP NoSnoop,=0D - OUT PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D - //=0D - // implementation specific rules for the usage of PCI_FEATURE_POLICY mem= bers=0D - // exclusively for the PCI Feature No-Snoop=0D - //=0D - // .Override =3D 0 to skip this PCI feature No-Snoop for the PCI device= =0D - // .Override =3D 1 to program this No-Snoop PCI feature=0D - // .Act =3D 1 to enable the No-Snoop in the PCI device=0D - // .Act =3D 0 to disable the No-Snoop in the PCI device=0D - //=0D - switch (NoSnoop) {=0D - case EFI_PCI_EXPRESS_NS_AUTO:=0D - PciDevice->SetupNS.Override =3D 0;=0D - break;=0D - case EFI_PCI_EXPRESS_NS_DISABLE:=0D - PciDevice->SetupNS.Override =3D 1;=0D - PciDevice->SetupNS.Act =3D 0;=0D - break;=0D - case EFI_PCI_EXPRESS_NS_ENABLE:=0D - PciDevice->SetupNS.Override =3D 1;=0D - PciDevice->SetupNS.Act =3D 1;=0D - break;=0D - default:=0D - PciDevice->SetupNS.Override =3D 0;=0D - break;=0D - }=0D -}=0D -=0D -/**=0D - Routine to set the device-specific policy for the PCI feature CTO value = range=0D - or disable=0D -=0D - @param CtoSupport value corresponding to data type EFI_PCI_EXPRESS_C= TO_SUPPORT=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D -**/=0D -VOID=0D -SetDevicePolicyPciExpressCto (=0D - IN EFI_PCI_EXPRESS_CTO_SUPPORT CtoSupport,=0D - OUT PCI_IO_DEVICE *PciDevice=0D -)=0D -{=0D - //=0D - // implementation specific rules for the usage of PCI_FEATURE_POLICY mem= bers=0D - // exclusively for the PCI Feature CTO=0D - //=0D - // .Override =3D 0 to skip this PCI feature CTO for the PCI device=0D - // .Override =3D 1 to program this CTO PCI feature=0D - // .Act =3D 1 to program the CTO range as per given device policy i= n .Support=0D - // .Act =3D 0 to disable the CTO mechanism in the PCI device, CTO s= et to default range=0D - //=0D - switch (CtoSupport) {=0D - case EFI_PCI_EXPRESS_CTO_AUTO:=0D - PciDevice->SetupCTO.Override =3D 0;=0D - break;=0D - case EFI_PCI_EXPRESS_CTO_DEFAULT:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_50MS;=0D - break;=0D - case EFI_PCI_EXPRESS_CTO_RANGE_A1:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_100US;= =0D - break;=0D - case EFI_PCI_EXPRESS_CTO_RANGE_A2:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_1MS_10MS;=0D - break;=0D - case EFI_PCI_EXPRESS_CTO_RANGE_B1:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_16MS_55MS;=0D - break;=0D - case EFI_PCI_EXPRESS_CTO_RANGE_B2:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS;= =0D - break;=0D - case EFI_PCI_EXPRESS_CTO_RANGE_C1:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_260MS_900MS;= =0D - break;=0D - case EFI_PCI_EXPRESS_CTO_RANGE_C2:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S;=0D - break;=0D - case EFI_PCI_EXPRESS_CTO_RANGE_D1:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_4S_13S;=0D - break;=0D - case EFI_PCI_EXPRESS_CTO_RANGE_D2:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 1;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_17S_64S;=0D - break;=0D - case EFI_PCI_EXPRESS_CTO_DET_DISABLE:=0D - PciDevice->SetupCTO.Override =3D 1;=0D - PciDevice->SetupCTO.Act =3D 0;=0D - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_50MS;=0D - break;=0D - }=0D -}=0D -=0D -/**=0D - Routine to set the device-specific policy for the PCI feature LTR enable= /disable=0D -=0D - @param AtomicOp value corresponding to data type EFI_PCI_EXPRESS_A= TOMIC_OP=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D -=0D -**/=0D -VOID=0D -SetDevicePolicyPciExpressLtr (=0D - IN EFI_PCI_EXPRESS_LTR Ltr,=0D - OUT PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D - switch (Ltr){=0D - case EFI_PCI_EXPRESS_LTR_AUTO:=0D - case EFI_PCI_EXPRESS_LTR_DISABLE:=0D - //=0D - // leave the LTR mechanism disable or restore to its default state=0D - //=0D - PciDevice->SetupLtr =3D FALSE;=0D - break;=0D - case EFI_PCI_EXPRESS_LTR_ENABLE:=0D - //=0D - // LTR mechanism enable=0D - //=0D - PciDevice->SetupLtr =3D TRUE;=0D - break;=0D - }=0D -}=0D -=0D -/**=0D - Generic routine to setup the PCI features as per its predetermined defau= lts.=0D -**/=0D -VOID=0D -SetupDefaultPciExpressDevicePolicy (=0D - IN PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D -=0D - if (mPciExpressPlatformPolicy.Mps) {=0D - PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_AUTO;=0D - } else {=0D - PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D - if (mPciExpressPlatformPolicy.Mrrs) {=0D - PciDevice->SetupMRRS =3D EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_AUTO;=0D - } else {=0D - PciDevice->SetupMRRS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D - PciDevice->SetupRO.Override =3D 0;=0D -=0D - PciDevice->SetupNS.Override =3D 0;=0D -=0D - PciDevice->SetupCTO.Override =3D 0;=0D -=0D - PciDevice->SetupAtomicOp.Override =3D 0;=0D -=0D - PciDevice->SetupLtr =3D FALSE;=0D -=0D - if (mPciExpressPlatformPolicy.ExtTag) {=0D - PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_AUTO;=0D - } else {=0D - PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D - //=0D - // default device policy for device's link ASPM=0D - //=0D - if (mPciExpressPlatformPolicy.Aspm) {=0D - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_ASPM_AUTO;=0D - } else {=0D - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D - //=0D - // default device policy for the device's link clock configuration=0D - //=0D - if (mPciExpressPlatformPolicy.Ccc) {=0D - PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_CLK_CFG_AUTO;=0D - } else {=0D - PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D -}=0D -=0D -/**=0D - initialize the device policy data members=0D -**/=0D -VOID=0D -InitializeDevicePolicyData (=0D - IN EFI_PCI_EXPRESS_DEVICE_POLICY *PciExpressDevicePolicy=0D - )=0D -{=0D - UINTN length;=0D - UINT8 *PciExpressPolicy;=0D - UINT8 *PciExDevicePolicy;=0D -=0D -=0D - ZeroMem (PciExpressDevicePolicy, sizeof (EFI_PCI_EXPRESS_DEVICE_POLICY))= ;=0D -=0D - for (=0D - length =3D 0=0D - , PciExpressPolicy =3D (UINT8*)&mPciExpressPlatformPolicy=0D - , PciExDevicePolicy =3D (UINT8*)PciExpressDevicePolicy=0D - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY)=0D - ; length++=0D - ) {=0D - if (!PciExpressPolicy[length]) {=0D - PciExDevicePolicy[length] =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D - }=0D -}=0D -=0D -/**=0D - Intermediate routine to either get the PCI device specific platform poli= cies=0D - through the PCI Platform Protocol, or its alias the PCI Override Protoco= l.=0D -=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D - @param PciPlatformProtocol A pointer to EFI_PCI_EXPRESS_PLATFORM_PROTOC= OL=0D -=0D - @retval EFI_STATUS The direct status from the PCI Platform Prot= ocol=0D - @retval EFI_SUCCESS if on returning predetermined PCI features d= efaults,=0D - for the case when protocol returns as EFI_UN= SUPPORTED=0D - to indicate PCI device exist and it has no p= latform=0D - policy defined.=0D -**/=0D -EFI_STATUS=0D -GetPciExpressDevicePolicy (=0D - IN PCI_IO_DEVICE *PciDevice,=0D - IN EFI_PCI_EXPRESS_PLATFORM_PROTOCOL *PciPlatformProtocol=0D - )=0D -{=0D - EFI_PCI_EXPRESS_DEVICE_POLICY PciExpressDevicePolicy;=0D - EFI_STATUS Status;=0D - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;=0D -=0D - PciAddress.Bus =3D PciDevice->BusNumber;=0D - PciAddress.Device =3D PciDevice->DeviceNumber;=0D - PciAddress.Function =3D PciDevice->FunctionNumber;=0D - PciAddress.Register =3D 0;=0D - PciAddress.ExtendedRegister =3D 0;=0D -=0D - InitializeDevicePolicyData (&PciExpressDevicePolicy);=0D - Status =3D PciPlatformProtocol->GetDevicePolicy (=0D - PciPlatformProtocol,=0D - mRootBridgeHandle,=0D - PciAddress,=0D - sizeof (EFI_PCI_EXPRESS_DEVICE_POLICY),= =0D - &PciExpressDevicePolicy=0D - );=0D - if (!EFI_ERROR(Status)) {=0D - //=0D - // platform chipset policies are returned for this PCI device=0D - //=0D -=0D - //=0D - // set device specific policy for the Max_Payload_Size=0D - //=0D - if (mPciExpressPlatformPolicy.Mps) {=0D - PciDevice->SetupMPS =3D PciExpressDevicePolicy.DeviceCtlMPS;=0D - } else {=0D - PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D - //=0D - // set device specific policy for Max_Read_Req_Size=0D - //=0D - if (mPciExpressPlatformPolicy.Mrrs) {=0D - PciDevice->SetupMRRS =3D PciExpressDevicePolicy.DeviceCtlMRRS;=0D - } else {=0D - PciDevice->SetupMRRS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D - //=0D - // set device specific policy for Relax Ordering=0D - //=0D - if (mPciExpressPlatformPolicy.RelaxOrder) {=0D - SetDevicePolicyPciExpressRo (PciExpressDevicePolicy.DeviceCtlRelaxOr= der, PciDevice);=0D - } else {=0D - PciDevice->SetupRO.Override =3D 0;=0D - }=0D -=0D - //=0D - // set the device specific policy for No-Snoop=0D - //=0D - if (mPciExpressPlatformPolicy.NoSnoop) {=0D - SetDevicePolicyPciExpressNs (PciExpressDevicePolicy.DeviceCtlNoSnoop= , PciDevice);=0D - } else {=0D - PciDevice->SetupNS.Override =3D 0;=0D - }=0D -=0D - //=0D - // set the device specific policy for Completion Timeout (CTO)=0D - //=0D - if (mPciExpressPlatformPolicy.Cto) {=0D - SetDevicePolicyPciExpressCto (PciExpressDevicePolicy.CTOsupport, Pci= Device);=0D - } else {=0D - PciDevice->SetupCTO.Override =3D 0;=0D - }=0D -=0D - //=0D - // set the device-specific policy for AtomicOp=0D - //=0D - if (mPciExpressPlatformPolicy.AtomicOp) {=0D - PciDevice->SetupAtomicOp =3D PciExpressDevicePolicy.DeviceCtl2Atomic= Op;=0D - } else {=0D - PciDevice->SetupAtomicOp.Override =3D 0;=0D - }=0D -=0D - //=0D - // set the device-specific policy for LTR mechanism in the function=0D - //=0D - if (mPciExpressPlatformPolicy.Ltr) {=0D - SetDevicePolicyPciExpressLtr (PciExpressDevicePolicy.DeviceCtl2LTR, = PciDevice);=0D - } else {=0D - PciDevice->SetupLtr =3D FALSE;=0D - }=0D -=0D - //=0D - // set the device-specifci policy for the PCI Express feature Extended= Tag=0D - //=0D - if (mPciExpressPlatformPolicy.ExtTag) {=0D - PciDevice->SetupExtTag =3D PciExpressDevicePolicy.DeviceCtlExtTag;=0D - } else {=0D - PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D - //=0D - // set the device-specific policy for the PCI Express feature ASPM=0D - //=0D - if (mPciExpressPlatformPolicy.Aspm) {=0D - PciDevice->SetupAspm =3D PciExpressDevicePolicy.LinkCtlASPMState;=0D - } else {=0D - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D - //=0D - // set the device policy for the PCI Express feature Common Clock Conf= iguration=0D - //=0D - if (mPciExpressPlatformPolicy.Ccc) {=0D - PciDevice->SetupCcc =3D PciExpressDevicePolicy.LinkCtlCommonClkCfg;= =0D - } else {=0D - PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D - }=0D -=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "[device policy: platform]"=0D - ));=0D - return Status;=0D - } else if (Status =3D=3D EFI_UNSUPPORTED) {=0D - //=0D - // platform chipset policies are not provided for this PCI device=0D - // let the enumeration happen as per the PCI standard way=0D - //=0D - SetupDefaultPciExpressDevicePolicy (PciDevice);=0D - DEBUG ((=0D - DEBUG_INFO,=0D - "[device policy: default]"=0D - ));=0D - return EFI_SUCCESS;=0D - }=0D - DEBUG ((=0D - DEBUG_ERROR,=0D - "[device policy: none (error)]"=0D - ));=0D - return Status;=0D -}=0D -=0D -/**=0D - Gets the PCI device-specific platform policy from the PCI Express Platfo= rm Protocol.=0D - If no PCI Platform protocol is published than setup the PCI feature to p= redetermined=0D - defaults, in order to align all the PCI devices in the PCI hierarchy, as= applicable.=0D -=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D -=0D - @retval EFI_STATUS The direct status from the PCI Platform Protocol=0D - @retval EFI_SUCCESS On return of predetermined PCI features defaults, = for=0D - the case when protocol returns as EFI_UNSUPPORTED = to=0D - indicate PCI device exist and it has no platform p= olicy=0D - defined. Also, on returns when no PCI Platform Pro= tocol=0D - exist.=0D -**/=0D -EFI_STATUS=0D -PciExpressPlatformGetDevicePolicy (=0D - IN PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D - if (mPciExPlatformProtocol !=3D NULL) {=0D - return GetPciExpressDevicePolicy (PciDevice, mPciExPlatformProtocol);= =0D - } else if (mPciExOverrideProtocol !=3D NULL) {=0D - return GetPciExpressDevicePolicy (PciDevice, mPciExOverrideProtocol);= =0D - } else {=0D - //=0D - // no protocol found, platform does not require the PCI Express initia= lization=0D - //=0D - return EFI_UNSUPPORTED;=0D - }=0D -}=0D -=0D -/**=0D - This function gets the platform requirement to initialize the list of PC= I Express=0D - features from the protocol definition supported.=0D - This function should be called after the LocatePciPlatformProtocol.=0D - @retval EFI_SUCCESS return by platform to acknowledge the list= of=0D - PCI Express feature to be configured=0D - (in mPciExpressPlatformPolicy)=0D - EFI_INVALID_PARAMETER platform does not support the protocol arg= uements=0D - passed=0D - EFI_UNSUPPORTED platform did not published the protocol=0D -**/=0D -EFI_STATUS=0D -PciExpressPlatformGetPolicy (=0D - )=0D -{=0D - EFI_STATUS Status;=0D -=0D - if (mPciExPlatformProtocol) {=0D - Status =3D mPciExPlatformProtocol->GetPolicy (=0D - mPciExPlatformProtocol,=0D - sizeof (EFI_PCI_EXPRESS_PLATFORM_POL= ICY),=0D - &mPciExpressPlatformPolicy=0D - );=0D - } else if (mPciExOverrideProtocol) {=0D - Status =3D mPciExOverrideProtocol->GetPolicy (=0D - mPciExOverrideProtocol,=0D - sizeof (EFI_PCI_EXPRESS_PLATFORM_POL= ICY),=0D - &mPciExpressPlatformPolicy=0D - );=0D - } else {=0D - //=0D - // no protocol found, platform does not require the PCI Express initia= lization=0D - //=0D - return EFI_UNSUPPORTED;=0D - }=0D - return Status;=0D -}=0D -=0D -EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE=0D -GetPciExpressMps (=0D - IN UINT8 Mps=0D - )=0D -{=0D - switch (Mps) {=0D - case PCIE_MAX_PAYLOAD_SIZE_128B:=0D - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_128B;=0D - case PCIE_MAX_PAYLOAD_SIZE_256B:=0D - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_256B;=0D - case PCIE_MAX_PAYLOAD_SIZE_512B:=0D - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_512B;=0D - case PCIE_MAX_PAYLOAD_SIZE_1024B:=0D - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_1024B;=0D - case PCIE_MAX_PAYLOAD_SIZE_2048B:=0D - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_2048B;=0D - case PCIE_MAX_PAYLOAD_SIZE_4096B:=0D - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_4096B;=0D - }=0D - return EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D -}=0D -=0D -EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE=0D -GetPciExpressMrrs (=0D - IN UINT8 Mrrs=0D - )=0D -{=0D - switch (Mrrs) {=0D - case PCIE_MAX_READ_REQ_SIZE_128B:=0D - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_128B;=0D - case PCIE_MAX_READ_REQ_SIZE_256B:=0D - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_256B;=0D - case PCIE_MAX_READ_REQ_SIZE_512B:=0D - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_512B;=0D - case PCIE_MAX_READ_REQ_SIZE_1024B:=0D - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_1024B;=0D - case PCIE_MAX_READ_REQ_SIZE_2048B:=0D - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_2048B;=0D - case PCIE_MAX_READ_REQ_SIZE_4096B:=0D - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_4096B;=0D - }=0D - return EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D -}=0D -=0D -EFI_PCI_EXPRESS_CTO_SUPPORT=0D -GetPciExpressCto (=0D - IN UINT8 Cto=0D - )=0D -{=0D - switch (Cto) {=0D - case PCIE_COMPLETION_TIMEOUT_50US_50MS:=0D - return EFI_PCI_EXPRESS_CTO_DEFAULT;=0D - case PCIE_COMPLETION_TIMEOUT_50US_100US:=0D - return EFI_PCI_EXPRESS_CTO_RANGE_A1;=0D - case PCIE_COMPLETION_TIMEOUT_1MS_10MS:=0D - return EFI_PCI_EXPRESS_CTO_RANGE_A2;=0D - case PCIE_COMPLETION_TIMEOUT_16MS_55MS:=0D - return EFI_PCI_EXPRESS_CTO_RANGE_B1;=0D - case PCIE_COMPLETION_TIMEOUT_65MS_210MS:=0D - return EFI_PCI_EXPRESS_CTO_RANGE_B2;=0D - case PCIE_COMPLETION_TIMEOUT_260MS_900MS:=0D - return EFI_PCI_EXPRESS_CTO_RANGE_C1;=0D - case PCIE_COMPLETION_TIMEOUT_1S_3_5S:=0D - return EFI_PCI_EXPRESS_CTO_RANGE_C2;=0D - case PCIE_COMPLETION_TIMEOUT_4S_13S:=0D - return EFI_PCI_EXPRESS_CTO_RANGE_D1;=0D - case PCIE_COMPLETION_TIMEOUT_17S_64S:=0D - return EFI_PCI_EXPRESS_CTO_RANGE_D2;=0D - }=0D - return EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D -}=0D -=0D -EFI_PCI_EXPRESS_EXTENDED_TAG=0D -GetPciExpressExtTag (=0D - IN PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D - if (PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bits.TenBitT= agRequesterEnable) {=0D - return EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT;=0D - } else if (PciDevice->PciExpressCapabilityStructure.DeviceControl.Bits.E= xtendedTagField) {=0D - return EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT;=0D - } else {=0D - return EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT;=0D - }=0D -}=0D -=0D -EFI_PCI_EXPRESS_ASPM_SUPPORT=0D -GetPciExpressAspmState (=0D - IN PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D - switch (PciDevice->PciExpressCapabilityStructure.LinkControl.Bits.AspmCo= ntrol) {=0D - case 0:=0D - return EFI_PCI_EXPRESS_ASPM_DISABLE;=0D - case 1:=0D - return EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT;=0D - case 2:=0D - return EFI_PCI_EXPRESS_ASPM_L1_SUPPORT;=0D - case 3:=0D - return EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT;=0D - }=0D - return EFI_PCI_EXPRESS_NOT_APPLICABLE;=0D -}=0D -=0D -/**=0D - Notifies the platform about the current PCI Express state of the device.= =0D -=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D - @param PciExDeviceConfiguration Pointer to EFI_PCI_EXPRESS_DEVICE_CONF= IGURATION.=0D - Used to pass the current state of devi= ce to=0D - platform.=0D -=0D - @retval EFI_STATUS The direct status from the PCI Express Platfor= m Protocol=0D - @retval EFI_UNSUPPORTED returns when the PCI Express Platform Protocol= or its=0D - alias PCI Express OVerride Protocol is not pre= sent.=0D -**/=0D -EFI_STATUS=0D -PciExpressPlatformNotifyDeviceState (=0D - IN PCI_IO_DEVICE *PciDevice=0D - )=0D -{=0D - EFI_PCI_EXPRESS_DEVICE_CONFIGURATION PciExDeviceConfiguration;=0D -=0D - //=0D - // get the device-specific state for the PCIe Max_Payload_Size feature=0D - //=0D - if (mPciExpressPlatformPolicy.Mps) {=0D - PciExDeviceConfiguration.DeviceCtlMPS =3D GetPciExpressMps (=0D - (UINT8)PciDevice->PciExpress= CapabilityStructure.DeviceControl.Bits.MaxPayloadSize=0D - );=0D - } else {=0D - PciExDeviceConfiguration.DeviceCtlMPS =3D EFI_PCI_EXPRESS_NOT_APPLICAB= LE;=0D - }=0D -=0D - //=0D - // get the device-specific state for the PCIe Max_Read_Req_Size feature= =0D - //=0D - if (mPciExpressPlatformPolicy.Mrrs) {=0D - PciExDeviceConfiguration.DeviceCtlMRRS =3D GetPciExpressMrrs (=0D - (UINT8)PciDevice->PciExpress= CapabilityStructure.DeviceControl.Bits.MaxReadRequestSize=0D - );=0D - } else {=0D - PciExDeviceConfiguration.DeviceCtlMRRS =3D EFI_PCI_EXPRESS_NOT_APPLICA= BLE;=0D - }=0D - //=0D - // get the device-specific state for the PCIe Relax Order feature=0D - //=0D - if (mPciExpressPlatformPolicy.RelaxOrder) {=0D - PciExDeviceConfiguration.DeviceCtlRelaxOrder =3D PciDevice->PciExpress= CapabilityStructure.DeviceControl.Bits.RelaxedOrdering=0D - ? EFI_PCI_EXPRESS_RO= _ENABLE=0D - : EFI_PCI_EXPRESS_RO= _DISABLE;=0D - } else {=0D - PciExDeviceConfiguration.DeviceCtlRelaxOrder =3D EFI_PCI_EXPRESS_NOT_A= PPLICABLE;=0D - }=0D -=0D - //=0D - // get the device-specific state for the PCIe NoSnoop feature=0D - //=0D - if (mPciExpressPlatformPolicy.NoSnoop) {=0D - PciExDeviceConfiguration.DeviceCtlNoSnoop =3D PciDevice->PciExpressCap= abilityStructure.DeviceControl.Bits.NoSnoop=0D - ? EFI_PCI_EXPRESS_NS_E= NABLE=0D - : EFI_PCI_EXPRESS_NS_D= ISABLE;=0D - } else {=0D - PciExDeviceConfiguration.DeviceCtlNoSnoop =3D EFI_PCI_EXPRESS_NOT_APPL= ICABLE;=0D - }=0D -=0D - //=0D - // get the device-specific state for the PCIe CTO feature=0D - //=0D - if (mPciExpressPlatformPolicy.Cto) {=0D - PciExDeviceConfiguration.CTOsupport =3D PciDevice->PciExpressCapabilit= yStructure.DeviceControl2.Bits.CompletionTimeoutDisable=0D - ? EFI_PCI_EXPRESS_CTO_DET_DISABL= E=0D - : GetPciExpressCto (=0D - (UINT8)PciDevice->PciExpress= CapabilityStructure.DeviceControl2.Bits.CompletionTimeoutValue=0D - );=0D - } else {=0D - PciExDeviceConfiguration.CTOsupport =3D EFI_PCI_EXPRESS_NOT_APPLICABLE= ;=0D - }=0D -=0D - //=0D - // get the device-specific state for the PCIe AtomicOp feature=0D - //=0D - if (mPciExpressPlatformPolicy.AtomicOp) {=0D - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpRequester=0D - =3D (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bit= s.AtomicOpRequester;=0D - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpEgressBlock= ing=0D - =3D (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bit= s.AtomicOpEgressBlocking;=0D - } else {=0D - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Override =3D 0;=0D - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpRequester = =3D 0;=0D - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpEgressBlock= ing =3D 0;=0D - }=0D - //=0D - // get the device-specific state for LTR mechanism in the function=0D - //=0D - if (mPciExpressPlatformPolicy.Ltr) {=0D - PciExDeviceConfiguration.DeviceCtl2LTR =3D PciDevice->PciExpressCapabi= lityStructure.DeviceControl2.Bits.LtrMechanism=0D - ? EFI_PCI_EXPRESS_LTR_ENAB= LE=0D - : EFI_PCI_EXPRESS_LTR_DISA= BLE;=0D - } else {=0D - PciExDeviceConfiguration.DeviceCtl2LTR =3D EFI_PCI_EXPRESS_NOT_APPLICA= BLE;=0D - }=0D -=0D - //=0D - // get the device-specific state for the PCie Extended Tag in the functi= on=0D - //=0D - if (mPciExpressPlatformPolicy.ExtTag) {=0D - PciExDeviceConfiguration.DeviceCtlExtTag =3D GetPciExpressExtTag (PciD= evice);=0D - } else {=0D - PciExDeviceConfiguration.DeviceCtlExtTag =3D EFI_PCI_EXPRESS_NOT_APPLI= CABLE;=0D - }=0D -=0D - //=0D - // get the device-specific state for PCIe ASPM state=0D - //=0D - if (mPciExpressPlatformPolicy.Aspm) {=0D - PciExDeviceConfiguration.LinkCtlASPMState =3D GetPciExpressAspmState (= PciDevice);=0D - } else {=0D - PciExDeviceConfiguration.LinkCtlASPMState =3D EFI_PCI_EXPRESS_NOT_APPL= ICABLE;=0D - }=0D -=0D - //=0D - // get the device-specific Common CLock Configuration value=0D - //=0D - if (mPciExpressPlatformPolicy.Ccc) {=0D - PciExDeviceConfiguration.LinkCtlCommonClkCfg =3D=0D - PciDevice->PciExpressCapabilityStructure.LinkControl.Bits.CommonCl= ockConfiguration ?=0D - EFI_PCI_EXPRESS_CLK_CFG_COMMON : EFI_PCI_EXPRESS_CLK_CFG_ASYNC= H;=0D - } else {=0D - PciExDeviceConfiguration.LinkCtlCommonClkCfg =3D EFI_PCI_EXPRESS_NOT_A= PPLICABLE;=0D - }=0D -=0D - if (mPciExPlatformProtocol !=3D NULL) {=0D - return mPciExPlatformProtocol->NotifyDeviceState (=0D - mPciExPlatformProtocol,=0D - PciDevice->Handle,=0D - sizeof (EFI_PCI_EXPRESS_DEVICE_CONFIGU= RATION),=0D - &PciExDeviceConfiguration=0D - );=0D - } else if (mPciExOverrideProtocol !=3D NULL) {=0D - return mPciExOverrideProtocol->NotifyDeviceState (=0D - mPciExOverrideProtocol,=0D - PciDevice->Handle,=0D - sizeof (EFI_PCI_EXPRESS_DEVICE_CONFIGU= RATION),=0D - &PciExDeviceConfiguration=0D - );=0D - } else {=0D - //=0D - // unexpected error=0D - //=0D - return EFI_UNSUPPORTED;=0D - }=0D -}=0D -=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h deleted file mode 100644 index 4653c79..0000000 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h +++ /dev/null @@ -1,119 +0,0 @@ -/** @file=0D - This file encapsulate the usage of PCI Platform Protocol=0D -=0D - This file define the necessary hooks used to obtain the platform=0D - level data and policies which could be used in the PCI Enumeration phase= s=0D -=0D -Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -=0D -#ifndef _EFI_PCI_PLATFORM_SUPPORT_H_=0D -#define _EFI_PCI_PLATFORM_SUPPORT_H_=0D -=0D -=0D -/**=0D - This function retrieves the PCI Express Platform Protocols published by = platform=0D - @retval EFI_STATUS direct return status from the LocateProtocol= ()=0D - boot service for the PCI Express Override Pr= otocol=0D - EFI_SUCCESS The PCI Express Platform Protocol is found=0D -**/=0D -EFI_STATUS=0D -GetPciExpressProtocol (=0D - );=0D -=0D -/**=0D - This function indicates that the platform has published the PCI Express = Platform=0D - Protocol (or PCI Express Override Protocol) to indicate that this driver= can=0D - initialize the PCI Express features.=0D - @retval TRUE or FALSE=0D -**/=0D -BOOLEAN=0D -IsPciExpressProtocolPresent (=0D - );=0D -=0D -/**=0D - This function gets the platform requirement to initialize the list of PC= I Express=0D - features from the protocol definition supported.=0D - This function should be called after the LocatePciPlatformProtocol.=0D - @retval EFI_SUCCESS return by platform to acknowledge the list= of=0D - PCI Express feature to be configured=0D - (in mPciExpressPlatformPolicy)=0D - EFI_INVALID_PARAMETER platform does not support the protocol arg= uements=0D - passed=0D - EFI_UNSUPPORTED platform did not published the protocol=0D -**/=0D -EFI_STATUS=0D -PciExpressPlatformGetPolicy (=0D - );=0D -=0D -/**=0D - Gets the PCI device-specific platform policy from the PCI Platform Proto= col.=0D - If no PCI Platform protocol is published than setup the PCI feature to p= redetermined=0D - defaults, in order to align all the PCI devices in the PCI hierarchy, as= applicable.=0D -=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D -=0D - @retval EFI_STATUS The direct status from the PCI Platform Protocol=0D - @retval EFI_SUCCESS On return of predetermined PCI features defaults, = for=0D - the case when protocol returns as EFI_UNSUPPORTED = to=0D - indicate PCI device exist and it has no platform p= olicy=0D - defined. Also, on returns when no PCI Platform Pro= tocol=0D - exist.=0D -**/=0D -EFI_STATUS=0D -PciExpressPlatformGetDevicePolicy (=0D - IN PCI_IO_DEVICE *PciDevice=0D - );=0D -=0D -/**=0D - Notifies the platform about the current PCI Express state of the device.= =0D -=0D - @param PciDevice A pointer to PCI_IO_DEVICE=0D - @param PciExDeviceConfiguration Pointer to EFI_PCI_EXPRESS_DEVICE_CONF= IGURATION.=0D - Used to pass the current state of devi= ce to=0D - platform.=0D -=0D - @retval EFI_STATUS The direct status from the PCI Express Platfor= m Protocol=0D - @retval EFI_UNSUPPORTED returns when the PCI Express Platform Protocol= or its=0D - alias PCI Express OVerride Protocol is not pre= sent.=0D -**/=0D -EFI_STATUS=0D -PciExpressPlatformNotifyDeviceState (=0D - IN PCI_IO_DEVICE *PciDevice=0D - );=0D -=0D -/**=0D - Routine to translate the given device-specific platform policy from type= =0D - EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base Spec= ification=0D - Revision 4.0; for the PCI feature Max_Payload_Size.=0D -=0D - @param MPS Input device-specific policy should be in terms of type= =0D - EFI_PCI_CONF_MAX_PAYLOAD_SIZE=0D -=0D - @retval Range values for the Max_Payload_Size as defined in the = PCI=0D - Base Specification 4.0=0D -**/=0D -UINT8=0D -SetDevicePolicyPciExpressMps (=0D - IN UINT8 MPS=0D -);=0D -=0D -/**=0D - Routine to translate the given device-specific platform policy from type= =0D - EFI_PCI_CONF_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Base Spe= cification=0D - Revision 4.0; for the PCI feature Max_Read_Req_Size.=0D -=0D - @param MRRS Input device-specific policy should be in terms of type= =0D - EFI_PCI_CONF_MAX_READ_REQ_SIZE=0D -=0D - @retval Range values for the Max_Read_Req_Size as defined in the= PCI=0D - Base Specification 4.0=0D -**/=0D -UINT8=0D -SetDevicePolicyPciExpressMrrs (=0D - IN UINT8 MRRS=0D -);=0D -#endif=0D --=20 2.21.0.windows.1