From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.17390.1589127269924431738 for ; Sun, 10 May 2020 09:14:39 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ashraf.javeed@intel.com) IronPort-SDR: fepc6Y03y3Lyeg1PRdUeh0za+hPHWGwkaDLE7Lk6QJWuZik3S3DOfvlkPRfFUh+X9/DFT3ESfb VafyHvFHQiKw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2020 09:14:38 -0700 IronPort-SDR: xM6wrmjFZFNHLqNljEaLYBWtzFYX3FARaV4w/ZZEG9FePlosW23u0hTgtnVKmk1uEwtd7t67e7 wiVxizsqSBqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,376,1583222400"; d="scan'208";a="463129651" Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.37]) by fmsmga006.fm.intel.com with ESMTP; 10 May 2020 09:14:36 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Ray Ni , Jian J Wang , Hao A Wu Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/15] MdeModulePkg/PciBusDxe: Enable MaxPayloadSize feature Date: Sun, 10 May 2020 21:44:04 +0530 Message-Id: <20200510161412.13832-8-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200510161412.13832-1-ashraf.javeed@intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1954 https://bugzilla.tianocore.org/show_bug.cgi?id=2194 https://bugzilla.tianocore.org/show_bug.cgi?id=2313 https://bugzilla.tianocore.org/show_bug.cgi?id=2499 https://bugzilla.tianocore.org/show_bug.cgi?id=2500 Add the Scan and Program phase feature init routines for MaxPayloadSize PCIe feature. Signed-off-by: Ashraf Javeed Signed-off-by: Ray Ni Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni Cc: Ashraf Javeed --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 2 ++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 9 ++++++++- MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 28 ++++++++++++++++++++++++++++ 4 files changed, 157 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf index 0818153..e4b0ed6 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -59,6 +59,8 @@ PciBus.h PcieFeatureSupport.c PcieFeatureSupport.h + PcieFeatures.c + PcieFeatures.h [Packages] MdePkg/MdePkg.dec diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c index 20ef0e8..634e26b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c @@ -8,6 +8,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciBus.h" #include "PcieFeatureSupport.h" +#include "PcieFeatures.h" + EFI_PCI_EXPRESS_PLATFORM_PROTOCOL *mPciePlatformProtocol; GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPcieFeatureConfigurePhaseStr[] = { L"Scan", L"Program" }; @@ -47,7 +49,11 @@ STATIC_ASSERT ( ); PCIE_FEATURE_ENTRY mPcieFeatures[] = { - { 0, FALSE } // a dummy feature to pass build. + // + // Individual PCIE features + // + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxPayloadSize), + TRUE, { TRUE, TRUE }, { MaxPayloadSizeScan, MaxPayloadSizeProgram } }, }; /** @@ -220,6 +226,7 @@ PcieNotifyDeviceState ( CopyMem (&PcieDeviceState, &PciIoDevice->DeviceState, sizeof (PciIoDevice->DeviceState)); + PcieDeviceState.MaxPayloadSize = (UINT8)PciIoDevice->PciExpressCapability.DeviceControl.Bits.MaxPayloadSize; return mPciePlatformProtocol->NotifyDeviceState ( mPciePlatformProtocol, PciIoDevice->Handle, diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c new file mode 100644 index 0000000..d1a78f7 --- /dev/null +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c @@ -0,0 +1,119 @@ +/** @file + PCI standard feature support functions implementation for PCI Bus module.. + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PciBus.h" +#include "PcieFeatureSupport.h" + + +/** + Scan the devices to finalize the MaxPayloadSize settings of each device. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. + + @retval EFI_SUCCESS setup of PCI feature MaxPayloadSize is successful. +**/ +EFI_STATUS +MaxPayloadSizeScan ( + IN PCI_IO_DEVICE *PciDevice, + IN UINTN Level, + IN VOID **Context + ) +{ + UINT8 *MaxPayloadSize; + PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability; + + DEBUG (( + DEBUG_INFO, " %a [%02d|%02d|%02d]: Capability = %x\n", + __FUNCTION__, PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, + PciDevice->PciExpressCapability.DeviceCapability.Bits.MaxPayloadSize + )); + DeviceCapability.Uint32 = PciDevice->PciExpressCapability.DeviceCapability.Uint32; + + if ((PciDevice->DeviceState.MaxPayloadSize != EFI_PCI_EXPRESS_DEVICE_POLICY_AUTO) && + (PciDevice->DeviceState.MaxPayloadSize != EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE)) { + DeviceCapability.Bits.MaxPayloadSize = + MIN (PciDevice->DeviceState.MaxPayloadSize, DeviceCapability.Bits.MaxPayloadSize); + } + + MaxPayloadSize = *Context; + if (MaxPayloadSize == NULL) { + // + // Initialize the Context + // + MaxPayloadSize = AllocatePool (sizeof (*MaxPayloadSize)); + *MaxPayloadSize = (UINT8) DeviceCapability.Bits.MaxPayloadSize; + *Context = MaxPayloadSize; + } else { + // + // Set the Context to the minimum Max Payload Size in the heirarchy. + // + *MaxPayloadSize = MIN (*MaxPayloadSize, (UINT8) DeviceCapability.Bits.MaxPayloadSize); + } + return EFI_SUCCESS; +} + +/** + Program the PCIe Device Control register Max. Payload Size field per platform policy. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + @param Level The level of the PCI device in the heirarchy. + Level of root ports is 0. + @param Context Pointer to feature specific context. + + @retval EFI_SUCCESS The data was read from or written to the PCI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI configuration header of the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. +**/ +EFI_STATUS +MaxPayloadSizeProgram ( + IN PCI_IO_DEVICE *PciDevice, + IN UINTN Level, + IN VOID **Context + ) +{ + UINT8 *MaxPayloadSize; + + ASSERT (Context != NULL); + ASSERT (*Context != NULL); + + if (PciDevice->DeviceState.MaxPayloadSize == EFI_PCI_EXPRESS_DEVICE_POLICY_NOT_APPLICABLE) { + // + // NOT_APPLICABLE means platform requests PciBus doesn't change the setting. + // But the capability of this device is still honored when calculating the aligned value. + // + return EFI_SUCCESS; + } + + MaxPayloadSize = (UINT8 *) *Context; + PciDevice->DeviceState.MaxPayloadSize = *MaxPayloadSize; + + if (PciDevice->PciExpressCapability.DeviceControl.Bits.MaxPayloadSize != PciDevice->DeviceState.MaxPayloadSize) { + DEBUG (( + DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x\n", + __FUNCTION__, PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, + PciDevice->PciExpressCapability.DeviceControl.Bits.MaxPayloadSize, + PciDevice->DeviceState.MaxPayloadSize + )); + PciDevice->PciExpressCapability.DeviceControl.Bits.MaxPayloadSize = PciDevice->DeviceState.MaxPayloadSize; + + return PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl), + 1, + &PciDevice->PciExpressCapability.DeviceControl.Uint16 + ); + } + return EFI_SUCCESS; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h new file mode 100644 index 0000000..7b820e8 --- /dev/null +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h @@ -0,0 +1,28 @@ +/** @file + PCI standard feature support functions implementation for PCI Bus module.. + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_PCI_EXPRESS_FEATURES_H_ +#define _EFI_PCI_EXPRESS_FEATURES_H_ + + +EFI_STATUS +MaxPayloadSizeScan ( + IN PCI_IO_DEVICE *PciDevice, + IN UINTN Level, + IN VOID **Context + ); + +EFI_STATUS +MaxPayloadSizeProgram ( + IN PCI_IO_DEVICE *PciDevice, + IN UINTN Level, + IN VOID **Context + ); + + +#endif -- 2.21.0.windows.1