From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.13630.1589208952939844130 for ; Mon, 11 May 2020 07:55:53 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: ard.biesheuvel@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A77A1D6E; Mon, 11 May 2020 07:55:52 -0700 (PDT) Received: from e123331-lin.nice.arm.com (unknown [10.37.8.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 27B273F68F; Mon, 11 May 2020 07:55:50 -0700 (PDT) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Pete Batard , Jared McNeill , Andrei Warkentin , Samer El-Haj-Mahmoud , Jeremy Linton Subject: [PATCH edk2-platforms v4 7/9] Silicon/Broadcom/BcmGenetDxe: use MemoryFence() for MMIO write ordering Date: Mon, 11 May 2020 16:55:25 +0200 Message-Id: <20200511145527.23453-8-ard.biesheuvel@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200511145527.23453-1-ard.biesheuvel@arm.com> References: <20200511145527.23453-1-ard.biesheuvel@arm.com> ARM synchronization barriers can be used to stall execution and wait for cache or TLB maintenance to complete. TLB maintenance is irrelevant in the context of the GENET driver, but cache maintenance is important for non-cache coherent DMA, and synchronization barriers are needed to ensure that outgoing data is cleaned before starting DMA for TX frames. However, this cache maintenance is already taken care of by the cache maintenance routines, and so all we need to do in our I/O routines is ensure that MMIO writes are issued in the right order, and for this, an ordinary MemoryFence () is sufficient. This means we don't need to depend on ArmLib either. Signed-off-by: Ard Biesheuvel --- Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf | 2 -- Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c | 1 - Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c | 3 +-- 3 files changed, 1 insertion(+), 5 deletions(-) diff --git a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf index 9b3dc5e62ecf..e3e4ebbddb93 100644 --- a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf +++ b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf @@ -27,7 +27,6 @@ [Sources] SimpleNetwork.c [Packages] - ArmPkg/ArmPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec @@ -35,7 +34,6 @@ [Packages] Silicon/Broadcom/Drivers/Net/BcmNet.dec [LibraryClasses] - ArmLib BaseLib BaseMemoryLib DebugLib diff --git a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c index 00fbfbc109bb..630a92ef210b 100644 --- a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c +++ b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c @@ -9,7 +9,6 @@ **/ -#include #include #include #include diff --git a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c index 35a3c7abdf1e..e3ce8614aeb2 100644 --- a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c +++ b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c @@ -8,7 +8,6 @@ #include "GenetUtil.h" -#include #include #include #include @@ -64,7 +63,7 @@ GenetMmioWrite ( { ASSERT ((Offset & 3) == 0); - ArmDataSynchronizationBarrier (); + MemoryFence (); MmioWrite32 (Genet->RegBase + Offset, Data); } -- 2.17.1