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Fri, 15 May 2020 13:39:49 +0000 From: "Daniel Schaefer" To: CC: Abner Chang , Gilbert Chen , Michael D Kinney , Leif Lindholm Subject: [PATCH v2 0/3] New RISC-V Patches Date: Fri, 15 May 2020 15:39:34 +0200 Message-ID: <20200515133937.29909-1-daniel.schaefer@hpe.com> X-Mailer: git-send-email 2.26.1 X-ClientProxiedBy: AM0P190CA0007.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::17) To CS1PR8401MB0726.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:750c::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from x360-nix.fritz.box (93.215.201.203) by AM0P190CA0007.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3000.20 via Frontend Transport; Fri, 15 May 2020 13:39:48 +0000 X-Mailer: git-send-email 2.26.1 X-Originating-IP: [93.215.201.203] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 10e68842-160d-4ef7-718c-08d7f8d5709c X-MS-TrafficTypeDiagnostic: CS1PR8401MB0726: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; 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X-MS-Exchange-AntiSpam-MessageData: lBdbNh7bFs7v0l9PGYD9wwBp7EShr33R0bdFUcXQVz43LAchZO4kXZNY0eCh3KVcieG8UddWaUnEyQ9dfPCda10ecm98W36GwKCXpQobuG8xY5vMYpRblw5WPKa2WOPEg39ONKtXKLLqvRa6fnI/l6KnelvcQIeGaTFTUmEVeq3gKw7SLLm5FFk5joFC5/GhVLZ1j9u7IE3ECTWUrw5ut3ThOW68O5zbN63w4HjpDtnDVYvCj7fPKrxKLbPg5TG7TAC0ldt4fArOnhJ0OCH+RZ3Hxu2y4gCQ6L3a2TgVkqjp13gOoybFnx0aKGJWyu3B3A3YOiWfmBjFJwFT0D/tYpQPgw2HRr78ycf9aMvIWMOZwwbCkBZef0LXL4/O95BCGnfi7v13hJTHG12j/X1QfRtxrTNJfXNDG7GB+WfqVJFHGWb0SM4YsihH8DKaVYUbFtafGlJtQreoAzIHHDrm8hoBC3W8moEG2/6IYZ5qUx8xJ/0G7sfuMjtjePGVTDm/ X-MS-Exchange-CrossTenant-Network-Message-Id: 10e68842-160d-4ef7-718c-08d7f8d5709c X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2020 13:39:49.9077 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 105b2061-b669-4b31-92ac-24d304d195dc X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Q/YlgrrY5OkSzSqLa3IvD04vNFxyyRzEKM5Bjd7CJsCkFl8ZqOwG7Jpy5PHrGJCWw1xralm+OjQLHj8VLxZrsg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CS1PR8401MB0726 X-OriginatorOrg: hpe.com X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216,18.0.676 definitions=2020-05-15_05:2020-05-15,2020-05-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 malwarescore=0 cotscore=-2147483648 clxscore=1011 priorityscore=1501 mlxlogscore=999 suspectscore=4 spamscore=0 impostorscore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2005150117 Content-Transfer-Encoding: 8bit Content-Type: text/plain In this updated version I addressed Leif's comments and made the following changes: - Refactor sbi_call* to SbiCall* (EDKII style) - Use OpenSBI constants if possible - Include Base.h in OpensbiTypes.h - Only use __builtin_expect with Clang and GCC (not MSVC) I'm sorry, I hadn't explained the new branches properly. Previously we had all code going to EDK2 via the RISC-V-V2 branch. Now we're only making the least amount of necessary changes in edk2 and everything else in edk2-platforms. Those changes to edk2 can be grouped into different categories: - Patches for RISC-V EDK2 CI enablement - Patches for edk2 modules other than RISC-V ones, to allow building them with the RISC-V toolchain - Other RISC-V enablement like PE/COFF relocation Those have all been reviewed and merged to edk2 master. Previously we had two packages just for RISC-V on our edk2 branch: RiscVPkg and RiscVPlatformPkg They are now under Platform/RISC-V/PlatformPkg and Silicon/RISC-V/ProcessorPkg in edk2-platforms. You, Leif, have previously reviewed those. In addition to this old code, which was moved, we need some more patches to allow running PEI in S-Mode and building in edk2-platforms. That's what this patch series is about. In the previous version of this patchseries I forgot to attach the biggest new commit, which adds RiscVEdk2SbiLib. It wraps the ecall interface for calling SBI in a C API and lets PEI and DXE call SBI interfaces. Because we need more M-Mode capabilities in PEI and DXE than SBI gives us, we register another SBI extension, that gives us access to the mscratch register. I hope now it makes more sense. - Daniel Cc: Abner Chang Cc: Gilbert Chen Cc: Michael D Kinney Cc: Leif Lindholm Abner Chang (1): ProcessorPkg/Library: Add RiscVOpensbiLib Daniel Schaefer (2): ProcessorPkg/RiscVOpensbLib: Add opensbi submodule ProcessorPkg/Library: Add RiscVEdk2SbiLib Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf | 28 + Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 60 ++ Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h | 72 ++ Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h | 631 ++++++++++++++++ Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h | 73 ++ Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 789 ++++++++++++++++++++ .gitmodules | 3 + Readme.md | 36 + Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi | 1 + 9 files changed, 1693 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c create mode 100644 .gitmodules create mode 160000 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi -- 2.26.1