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From: "Daniel Schaefer" <daniel.schaefer@hpe.com>
To: <devel@edk2.groups.io>
CC: Gilbert Chen <gilbert.chen@hpe.com>,
Leif Lindholm
<leif.lindholm@linaro.org>,
Abner Chang <abner.chang@hpe.com>,
Michael D
Kinney <michael.k.kinney@intel.com>,
Leif Lindholm <leif@nuviainc.com>
Subject: [PATCH v2 2/3] ProcessorPkg/Library: Add RiscVOpensbiLib
Date: Fri, 15 May 2020 15:39:36 +0200
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From: Abner Chang <abner.chang@hpe.com>
EDK2 RISC-V OpenSBI library which pull in external source files under
RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi to the build process.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Michael D Kinney <michael.k.kinney@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
---
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | =
60 +++++++++++++++
Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h | =
79 ++++++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h | =
73 ++++++++++++++++++
3 files changed, 212 insertions(+)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpens=
biLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensb=
iLib.inf
new file mode 100644
index 000000000000..59dbd67d8e03
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.i=
nf
@@ -0,0 +1,60 @@
+## @file=0D
+# RISC-V Opensbi Library Instance.=0D
+#=0D
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D RiscVOpensbiLib=0D
+ FILE_GUID =3D 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7=0D
+ MODULE_TYPE =3D BASE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D RiscVOpensbiLib=0D
+=0D
+[Sources]=0D
+ opensbi/lib/sbi/riscv_asm.c=0D
+ opensbi/lib/sbi/riscv_atomic.c=0D
+ opensbi/lib/sbi/riscv_hardfp.S=0D
+ opensbi/lib/sbi/riscv_locks.c=0D
+ opensbi/lib/sbi/sbi_console.c=0D
+ opensbi/lib/sbi/sbi_ecall.c=0D
+ opensbi/lib/sbi/sbi_ecall_vendor.c=0D
+ opensbi/lib/sbi/sbi_ecall_replace.c=0D
+ opensbi/lib/sbi/sbi_ecall_legacy.c=0D
+ opensbi/lib/sbi/sbi_ecall_base.c=0D
+ opensbi/lib/sbi/sbi_emulate_csr.c=0D
+ opensbi/lib/sbi/sbi_fifo.c=0D
+ opensbi/lib/sbi/sbi_hart.c=0D
+ opensbi/lib/sbi/sbi_hfence.S=0D
+ opensbi/lib/sbi/sbi_illegal_insn.c=0D
+ opensbi/lib/sbi/sbi_init.c=0D
+ opensbi/lib/sbi/sbi_ipi.c=0D
+ opensbi/lib/sbi/sbi_misaligned_ldst.c=0D
+ opensbi/lib/sbi/sbi_scratch.c=0D
+ opensbi/lib/sbi/sbi_string.c=0D
+ opensbi/lib/sbi/sbi_system.c=0D
+ opensbi/lib/sbi/sbi_timer.c=0D
+ opensbi/lib/sbi/sbi_tlb.c=0D
+ opensbi/lib/sbi/sbi_trap.c=0D
+ opensbi/lib/sbi/sbi_unpriv.c=0D
+ opensbi/lib/utils/sys/clint.c=0D
+ opensbi/lib/utils/irqchip/plic.c=0D
+ opensbi/lib/utils/serial/sifive-uart.c=0D
+ opensbi/lib/utils/serial/uart8250.c=0D
+=0D
+[Packages]=0D
+ EmbeddedPkg/EmbeddedPkg.dec # For libfdt.=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ PcdLib=0D
+ RiscVCpuLib=0D
+=0D
+=0D
+=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen=
sbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
new file mode 100644
index 000000000000..c5c0bd6d9b01
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
@@ -0,0 +1,79 @@
+/** @file=0D
+ SBI inline function calls.=0D
+=0D
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef EDK2_SBI_H_=0D
+#define EDK2_SBI_H_=0D
+=0D
+#include <include/sbi/riscv_asm.h> // Reference to header file in opensbi=
=0D
+#include <RiscVImpl.h>=0D
+#include <sbi/sbi_types.h> // Reference to header file wrapper=0D
+=0D
+#define SBI_SUCCESS 0=0D
+#define SBI_ERR_FAILED -1=0D
+#define SBI_ERR_NOT_SUPPORTED -2=0D
+#define SBI_ERR_INVALID_PARAM -3=0D
+#define SBI_ERR_DENIED -4=0D
+#define SBI_ERR_INVALID_ADDRESS -5=0D
+#define SBI_ERR_ALREADY_AVAILABLE -6=0D
+=0D
+#define SBI_BASE_EXT 0x10=0D
+#define SBI_HSM_EXT 0x48534D=0D
+#define SBI_TIME_EXT 0x54494D45=0D
+#define SBI_IPI_EXT 0x735049=0D
+#define SBI_RFNC_EXT 0x52464E43=0D
+=0D
+//=0D
+// Below two definitions should be defined in OpenSBI.=0D
+//=0D
+#define SBI_EXT_FIRMWARE_CODE_BASE_START 0x0A000000=0D
+#define SBI_EXT_FIRMWARE_CODE_BASE_END 0x0AFFFFFF=0D
+=0D
+#define SBI_GET_SPEC_VERSION_FUNC 0=0D
+#define SBI_GET_IMPL_ID_FUNC 1=0D
+#define SBI_GET_IMPL_VERSION_FUNC 2=0D
+#define SBI_PROBE_EXTENSION_FUNC 3=0D
+#define SBI_GET_MVENDORID_FUNC 4=0D
+#define SBI_GET_MARCHID_FUNC 5=0D
+#define SBI_GET_MIMPID_FUNC 6=0D
+=0D
+#define SBI_HART_START_FUNC 0=0D
+#define SBI_HART_STOP_FUNC 1=0D
+#define SBI_HART_GET_STATUS_FUNC 2=0D
+=0D
+#define RISC_V_MAX_HART_SUPPORTED 16=0D
+=0D
+typedef=0D
+VOID=0D
+(EFIAPI *RISCV_HART_SWITCH_MODE)(=0D
+ IN UINTN FuncArg0,=0D
+ IN UINTN FuncArg1,=0D
+ IN UINTN NextAddr,=0D
+ IN UINTN NextMode,=0D
+ IN BOOLEAN NextVirt=0D
+ );=0D
+=0D
+//=0D
+// Keep the structure member in 64-bit alignment.=0D
+//=0D
+typedef struct {=0D
+ UINT64 IsaExtensionSupported; // The ISA extension th=
is core supported.=0D
+ RISCV_UINT128 MachineVendorId; // Machine vendor ID=0D
+ RISCV_UINT128 MachineArchId; // Machine Architecture=
ID=0D
+ RISCV_UINT128 MachineImplId; // Machine Implementati=
on ID=0D
+ RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function t=
o switch the mode of a hart=0D
+} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;=0D
+#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size =
of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC=0D
+ // structure. Referr=
ed by both C code and assembly code.=0D
+=0D
+typedef struct {=0D
+ VOID *PeiServiceTable; // PEI Service table=0D
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_=
SUPPORTED];=0D
+} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;=0D
+=0D
+#endif=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/R=
ISC-V/ProcessorPkg/Include/OpensbiTypes.h
new file mode 100644
index 000000000000..5f3278e8461f
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
@@ -0,0 +1,73 @@
+/** @file=0D
+ RISC-V OpesbSBI header file reference.=0D
+=0D
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+#ifndef EDK2_SBI_TYPES_H_=0D
+#define EDK2_SBI_TYPES_H_=0D
+=0D
+#include <Base.h>=0D
+=0D
+typedef INT8 s8;=0D
+typedef UINT8 u8;=0D
+typedef UINT8 uint8_t;=0D
+=0D
+typedef INT16 s16;=0D
+typedef UINT16 u16;=0D
+typedef INT16 int16_t;=0D
+typedef UINT16 uint16_t;=0D
+=0D
+typedef INT32 s32;=0D
+typedef UINT32 u32;=0D
+typedef INT32 int32_t;=0D
+typedef UINT32 uint32_t;=0D
+=0D
+typedef INT64 s64;=0D
+typedef UINT64 u64;=0D
+typedef INT64 int64_t;=0D
+typedef UINT64 uint64_t;=0D
+=0D
+#define PRILX "016lx"=0D
+=0D
+typedef BOOLEAN bool;=0D
+typedef unsigned long ulong;=0D
+typedef UINT64 uintptr_t;=0D
+typedef UINT64 size_t;=0D
+typedef INT64 ssize_t;=0D
+typedef UINT64 virtual_addr_t;=0D
+typedef UINT64 virtual_size_t;=0D
+typedef UINT64 physical_addr_t;=0D
+typedef UINT64 physical_size_t;=0D
+=0D
+#define __packed __attribute__((packed))=0D
+#define __noreturn __attribute__((noreturn))=0D
+=0D
+#if defined(__GNUC__) || defined(__clang__)=0D
+ #define likely(x) __builtin_expect((x), 1)=0D
+ #define unlikely(x) __builtin_expect((x), 0)=0D
+#else=0D
+ #define likely(x) (x)=0D
+ #define unlikely(x) (x)=0D
+#endif=0D
+=0D
+#undef offsetof=0D
+#ifdef __compiler_offsetof=0D
+#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)=0D
+#else=0D
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)=0D
+#endif=0D
+=0D
+#define container_of(ptr, type, member) ({ \=0D
+ const typeof(((type *)0)->member) * __mptr =3D (ptr); \=0D
+ (type *)((char *)__mptr - offsetof(type, member)); })=0D
+=0D
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)=0D
+#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))=0D
+#define ROUNDDOWN(a, b) ((a) / (b) * (b))=0D
+=0D
+/* clang-format on */=0D
+=0D
+#endif=0D
--=20
2.26.1